register file structure of PIC controller
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The document discusses the register file structure in PIC microcontrollers. It describes that the register file consists of general purpose registers and special function registers. The general purpose registers include the working register and status register, while the special function registers include the program counter, stack pointer and other control registers. The register file is divided into four banks to provide expanded addressable memory. The bank selection bits in the status register allow accessing any of the four banks through direct or indirect addressing modes.
register file structure of PIC controller
- 1. Register File Structure in PIC 16F877a or16F8XX Presented By Nirbhay Kumar Singh nirbhaykumar2008@gmail.com Roll No. 151607 ME – ECE – 2015 Batch NITTTR Chandigarh 27-Dec-16 1
- 2. 27-Dec-16 2 Register File Structure in PIC 16F8xx The Registers A register is a place inside the PIC that can be written to, read from or both. Think of a register as a piece of paper where you can look at and write information on.
- 3. Register File Structure • Register file → locations that an instruction can access via an address. • Register file consists of two component:- 1. General purpose register file (same as RAM) 2. Special purpose register file 27-Dec-16 Nirbhay Kr Singh, Roll No. 151607, ME-MOD-ECE-2015 3
- 4. RAM (96 bytes) Special purpose Register (32 bytes) 27-Dec-16 Nirbhay Kr Singh, Roll No. 151607, ME-MOD-ECE-2015 4 Extra 64 bytes of RAM in PIC 16 C63 16 C65A 16 C73A 16 C74A RAM (32 bytes) Special purpose Register (32 bytes) Bank 0 128 bytes Bank 1 128 bytes 7F 20 1F 00 FF C0 BF A0 9F 80
- 5. 27-Dec-16 5 Register File Structure in PIC 16F8xx Registers in PIC 16F8XX W or working register (8 bit) Status Register (8 bits) SFR (Special Function Registers) GPR (General Purpose Registers)
- 6. 27-Dec-16 6 Register File Structure in PIC 16F8xx • 8 bits wide • Contains one of the source operands during the execution of instructions. • Serve as the destination for the result of the operation. • Only used for ALU operations.. W or Working Register
- 7. 27-Dec-16 7 Register File Structure in PIC 16F8xx Status Register (8 bits) • 1 - Banks 0 and 1 are active (memory location 00h-FFh) • 0 - Banks 2 and 3 are active (memory location 100h-1FFh) IRP - Bit selects register bank. It is used for indirect addressing. • Bits select register bank. They are used for direct addressing.RP1,RP0 • 1 - After power-on or after executing CLRWDT instruction which resets watch-dog timer or SLEEP instruction which sets the microcontroller into low-consumption mode. • 0 - After watch-dog timer time-out has occurred. TO - Time-out bit. • 1 - After power-on or after executing CLRWDT instruction which resets watch-dog timer. • 0 - After executing SLEEP instruction which sets the microcontroller into low-consumption mode. PD - Power-down bit. • 1 - The result of an arithmetic or logic operation is zero. • 0 - The result of an arithmetic or logic operation is different from zero.Z - Zero bit • 1 - A carry-out from the 4th low-order bit of the result has occurred. • 0 - No carry-out from the 4th low-order bit of the result has occurred. DC - Digit carry/borrow bit is changed during addition and subtraction if an “overflow” or a “borrow” of the result occurs. • 1 - A carry-out from the most significant bit of the result has occurred. • 0 - No carry-out from the most significant bit of the result has occurred. C - Carry/Borrow bit is changed during addition and subtraction if an “overflow” or a “borrow” of the result occurs, i.e. if the result is greater than 255 or less than 0.
- 8. 27-Dec-16 8 Register File Structure in PIC 16F8xx Microchip has provided only direct addressing mode for the register file with 7-bits address plus remaining 8th and 9th bits frozen in the STATUS REGISTER bits RP1:RP0. 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) As shown in figure
- 9. 27-Dec-16 9 Register File Structure in PIC 16F8xx Use of IPR bit in indirect addressing mode
- 10. 27-Dec-16 10 Register File Structure in PIC 16F8xx Indirect addressing mode IRP bit is used for indirect addressing. The IRP bit allows selecting either 1= Bank 2 & bank 3 0= Bank 0 & bank 1 The IPR bit and FSR decide the effective 9 bit address. As shown in figure
- 11. 27-Dec-16 11 Register File Structure in PIC 16F8xx Use of IPR bit in indirect addressing mode
- 12. 27-Dec-16 12 Register File Structure in PIC 16F8xx Special Function Register PCL and PCLATH Registers: The size of the program memory of the PIC16F887 is 8K. Therefore, it has 8192 locations for program storing. For this reason the program counter must be 13-bits wide (2^13 = 8192). In order that the contents of some location may be changed in software during operation, its address must be accessible through some SFR. Since all SFRs are 8-bits wide, this register is “artificially” created by dividing its 13 bits into two independent registers: PCLATH and PCL.
- 13. 27-Dec-16 13 Register File Structure in PIC 16F8xx Eight lower bits (the low byte) come from the PCL register which is readable and writable, whereas five upper bits coming from the PCLATH register are writable only. The PCLATH register is cleared on any reset.
- 14. 27-Dec-16 14 Register File Structure in PIC 16F8xx PCL Program Counter byte. PCL is the lower byte of the PC. Cause PCLATH contents to be transferred to the PC higher bit locations. PC of PIC is associated with an 8-level stack. PC always points to the next instruction to be executed. In case of call to subroutines, the returned address is pushed onto the stack. After the return from called subroutine, this return address is retrieved. Stack width and PC width should be same.
- 15. 27-Dec-16 15 Register File Structure in PIC 16F8xx Power control register Contains the flags which can differentiate between the type of reset occurred namely o Power on reset o Brown out reset
- 16. 27-Dec-16 16 Register File Structure in PIC 16F8xx Stack The entire PIC chip has an area for storing the return addresses. This area or unit called Stack is used in some Peripheral interface controllers.
- 17. 27-Dec-16 17 Register File Structure in PIC 16F8xx PIC16F87XA Data Memory Organization Data memory is divided in two four banks, Each bank holds 128 bytes of addressable memory. Contain GPR and SPR. The banked arrangement is necessary because there are only 7 bits are available in the instruction word for the addressing of a register, which gives only 128 addresses. The selection of the banks are determined by control bits RP1, RP0 in the STATUS registers Together the RP1, RP0 and the specified 7 bits effectively form a 9 bit address.
- 18. 27-Dec-16 18 Register File Structure in PIC 16F8xx
- 19. 27-Dec-16 19 Register File Structure in PIC 16F8xx Thanks