Register Transfer Language and Micro Operations

Unit- II - Register Transfer Language and Micro Operations
Dr. N.G.P. Institute of Technology -
Coimbatore-48
(An Autonomous Institution)
COMPUTER ORGANIZATION
&
Dr.N.S.Kavitha,
Assistant Professor
Department of Information Technology

INTRODUCTION
• Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution
– Etc.
• However, to understand how processors work, we will start
with a simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls
the Basic Computer
• We will use this to introduce processor organization and the
relationship of the RTL model to the higher level computer
processor

THE BASIC COMPUTER
• The Basic Computer has two components, a processor and
memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
CPU RAM
0
4095
15 0

INSTRUCTION CODE
• Instruction code
• Has group of bits (0111…..)
• Instruction code organized into 2 parts
• Operand
• Address
4096x16
4096x16
2^12 2^4
12-address part
4-opcode
Instruction program
Operand Data

INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in memory to
use for that operation
• In the Basic Computer, since the memory contains 4096 (=
212) words, we needs 12 bit to specify which memory
address this instruction will use
• In the Basic Computer, bit 15 of the instruction specifies
the addressing mode (0: direct addressing, 1: indirect
addressing)
• Since the memory words, and hence the instructions, are
16 bits long, that leaves 3 bits for the instruction’s opcode
Instruction Format
15 14 0
I Opcode Address
12 11
Addressing
mode

ADDRESSING MODES
• Effective Address (EA)
– The address, that can be directly used without modification to access an
operand for a computation-type instruction, or as the target address for a
branch-type instruction
22 0 ADD 457
Operand
457
35
300
1 ADD 300
1350
Operand
1350
+
AC
+
AC
Direct addressing Indirect addressing

PROCESSOR REGISTERS
• A processor has many registers to hold instructions,
addresses, data, etc
• The processor has a register, the Program Counter (PC) that
holds the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC
only needs 12 bits
• In a direct or indirect addressing, the processor needs to
keep track of what locations in memory it is addressing: The
Address Register (AR) is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The
processor then uses this value as data for its operation
• The Basic Computer has a single general purpose register –
the Accumulator (AC)

BASIC COMPUTER INSTRUCTIONS
I Opcode Address
• Basic Computer Instruction Format
Memory-Reference Instructions (OP-code = 000 ~ 110)
15 14 12 11 0
Register-Reference Instructions
15 12 11
(OP-code = 111, I =
0)
0
0 1 1 1 Register operation
Input-Output Instructions
15 12 11
(OP-code =111, I =
1)
0
1 1 1 1 I/O operation

INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user
can construct machine language programs to evaluate any
function that is known to be computable.
•Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory and the processor
registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

CONTROL UNIT
• Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations
that implement them
• Control units are implemented in one of two ways
• Hardwired Control
– CU is made up of sequential and combinational circuits to generate the
control signals
• Microprogrammed Control
– A control memory on the processor contains microprograms that
activate the necessary control signals
• We will consider a hardwired implementation of the control
unit for the Basic Computer

TIMING AND CONTROL
Control unit of Basic Computer
Instruction register (IR)
15 14 13
12
11 - 0
3 x 8
decoder
7 6 5 4 3 2
1 0
I
D0
15 14 . . . . 2 1 0
4 x 16
decoder
4-bit
sequence
counter
(SC)
Increment (INR)
Clear (CLR)
Clock
Other inputs
Control
signals
D 7
T15
T0
Combinational
Control
logic

TIMING SIGNALS
Clock
T0 T1
T2 T3
T4 D3
CLR SC
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC 
T0 0 T1 T2 T3 T4 T0

INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is executed in
the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction
• After an instruction is executed, the cycle starts again at
step 1, for the next instruction
• Note: Every different processor has its own (different)
instruction cycle

FETCH and DECODE
• Fetch and Decode T0: AR  PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
S2
S1
S0
Bus
7
Memory
unit
Address
Read
AR
LD
PC
INR
IR
LD Clock
1
2
5
Common bus
T1
T0

DETERMINE THE TYPE OF INSTRUCTION
= 0 (direct)
D'7IT3:
D'7I'T3:
D7I'T3:
D7IT3:
AR  M[AR]
Nothing
Execute a register-reference instr.
Execute an input-output instr.
Start
SC  
AR  PC
T0
IR  M[AR], PC  PC + 1
T1
Decode Opcode in IR(12-14), AR
 IR(0-11), I  IR(15)
T2
D7
(Register or I/O) = 1 = 0 (Memory-
reference)
I
I
Execute
register-reference
instruction
SC  0
Execute
input-output
instruction
SC  0
AR  M[AR] Nothing
(I/O) = 1 = 0 (register) (indirect) = 1
T3 T3 T3 T3
Execute
memory-reference
instruction
SC  0
T4

MEMORY REFERENCE INSTRUCTIONS
DR  M[AR]
AC  AC  DR, SC  0
Read operand
AND with AC
D0T4:
D0T5:
ADD
to
AC
D T :
DR  M[AR]
AC  AC + DR, E  Cout, SC  0
Read operand
Add to AC and store carry in
E
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
Symbol
Operation
Decoder
Symbolic Description
AND
ADD
LDA
STA
BUN
BSA
ISZ
D0 D1
D2 D3
D4 D5
D6
AC  AC  M[AR]
AC  AC + M[AR], E  Cout AC  M[AR]
M[AR]  AC PC  AR
M[AR]  PC, PC  AR + 1
M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC 
PC+1

Memory, PC after
execution
20
P
C
=
21
AR = 135
136
0 BSA 135
Next instruction
Subroutine
1 BUN 135
20
21
135
PC
=
136
0 BSA 135
Next instruction
21
Subroutine
1 BUN 135
Memory Memory
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally D4T4:
PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
Memory, PC, AR at time T4

BSA:
D5T4: M[AR]  PC, AR  AR + 1 D5T5: PC  AR, SC  0
ISZ: Increment and Skip-if-Zero D6T4: DR  M[AR] D6T5:
DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0
AND STA
AC  AC + DR
E  Cout SC
 0
AC  DR
SC  0
D0T4
Memory-reference instruction
ADD LDA
D1T4 D2T4 D3T 4
D0T5 D1T5 D2T5
PC  AR
SC  0
M[AR]  PC
AR  AR + 1
DR  M[AR]
BUN BSA ISZ
D4T4 D5T4 D6T4
DR  DR + 1
D5T5 D6T5
PC  AR SC
 0
M[AR]  DR If (DR
= 0)
then (PC  PC + 1)
SC  0
D6T6
AC  AC  DR
SC  0

INPUT-OUTPUT AND INTERRUPT
• Input-Output Configuration
INPR Input register - 8 bits
OUTR Output register - 8 bits
FGI Input flag - 1 bit
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit
- The terminal sends and receives serial information
- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
A Terminal with a keyboard and a Printer
I/O and Interrupt
Input-output
terminal communica
Serial
tion
interface
Computer
registers and
flip-flops
Printer
Keyboard
Receiver
interface
Transmitter
interface
FGO
OUTR
AC
INPR FGI
Serial Communications Path
Parallel Communications Path

INPUT-OUTPUT INSTRUCTIONS
D7IT3 = p
IR(i) = Bi, i = 6, …, 11
p:
pB11:
pB10:
pB9:
pB8:
pB7:
pB6:
SC  0
AC(0-7)  INPR, FGI  0 OUTR
 AC(0-7), FGO  0
if(FGI = 1) then (PC  PC + 1)
if(FGO = 1) then (PC  PC + 1)
IEN  1
IEN  0
Clear SC
INP Input char. to AC
OUT Output char. from AC
SKI Skip on input flag
SKO Skip on output flag
ION Interrupt enable on
IOF Interrupt enable off

PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
Input
LOOP, SKI DEV
BUN LOOP
INP DEV
Output
LOOP, LDA DATA
LOP, SKO DEV
BUN LOP
OUT DEV

INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to be passed --> interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer, it
generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task
it is doing, branches to the service routine to process the data transfer,
and then returns to the task it was performing.
* IEN (Interrupt-enable flip-flop)
- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted

FLOWCHART FOR INTERRUPT CYCLE
R = Interrupt f/f
- The interrupt cycle is a HW implementation of a branch and save
return address operation.
- At the beginning of the next instruction cycle, the instruction that is
read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original program is
"indirect BUN 0"
R
Store return address
in location 0
M[0]  PC
Branch to location 1
PC  1
IEN  0
R  0
=1 Interrupt
cycle
Instruction cycle =0
Fetch and decode
instructions
IEN
FGO
Execute
instructions
R  1
=1
=1
=1
=0
FGI
=0
=0

REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
Register Transfer Statements for Interrupt Cycle
- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1
-The fetch and decode phases of the instruction cycle
must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
-The interrupt cycle :
RT0: AR  0, TR  PC RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
After interrupt cycle
0
1
Before interrupt
255
PC
=
256
112
0
0 BUN 1120
Main Program
I/O Program
1 BUN 0
0
PC = 1
Memory
255
256
112
0
256
0 BUN 1120
Main Program
I/O Program
1 BUN 0

36
COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
=1(Indir) =0(Dir)
start
SC  0, IEN  0, R  0
R
AR  PC
IR  M[AR], PC  PC + 1
R’T1
AR  IR(0~11), I  IR(15)
D0...D7  Decode IR(12 ~ 14)
R’T2
AR  0, TR  PC
RT0
M[AR]  TR, PC  0
RT1
PC  PC + 1, IEN  0 R
 0, SC  0
RT2
D7
=1 (I/O)
I
=0 (Register) I
Execute
I/O
Instruction
Execute
RR
Instructio
n
AR <- M[AR] Idle
D7IT3 D7I’T3 D7’IT3 D7’I’T3
Execute MR
Instruction
=0(Instruction
Cycle)
R’T0
=1(Interrupt
Cycle)
=1(Register or I/O) =0(Memory Ref)
D7’T4

Microoperations
Fetch
Decode
Indirect
Interrupt
AND
ADD
LDA
STA
BUN
BSA
ISZ
RT0:
RT1:
RT2:
D7IT3:
RT2:
Memory-Reference
D0T4:
D0T5:
D1T4:
D1T5:
D2T4:
D2T5:
D3T4:
D4T4:
D5T4:
D5T5:
D6T4:
D6T5:
D6T6:
AR  PC
IR  M[AR], PC  PC + 1
D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
AR  M[AR]
R  1
AR  0, TR  PC M[AR]  TR, PC 
0
PC  PC + 1, IEN  0, R  0, SC  0
DR  M[AR]
AC  AC  DR, SC  0 DR  M[AR]
AC  AC + DR, E  Cout, SC  0 DR 
M[AR]
AC  DR, SC  0
M[AR]  AC, SC  0
PC  AR, SC  0
M[AR]  PC, AR  AR + 1 PC  AR, SC 
0
DR  M[AR] DR  DR + 1
M[AR]  DR, if(DR=0) then (PC  PC + 1),
SC  0
T0T1T2(IEN)(FGI + FGO):
RT0: RT1:

CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
Input-Output
INP
OUT
SKI
SKO
ION
IOF
Register-Reference
D7IT3 = r IR(i) = Bi
r:
rB11:
rB10:
rB9:
rB8:
rB7:
rB6:
rB5:
rB4:
rB3:
rB2:
rB1:
rB0:
D7IT3 =
p IR(i)
= Bi
p:
pB11:
pB10:
pB9:
pB8:
pB7:
pB6:
(Common to all register-reference
instr) (i = 0,1,2, ..., 11)
SC  0
AC  0
E  0
AC  AC E  E
AC  shr AC, AC(15)  E, E  AC(0)
AC  shl AC, AC(0)  E, E  AC(15) AC
 AC + 1
If(AC(15) =0) then (PC  PC + 1)
If(AC(15) =1) then (PC  PC + 1)
If(AC = 0) then (PC  PC + 1)
If(E=0) then (PC  PC + 1) S  0
(Common to all input-output
instructions) (i = 6,7,8,9,10,11)
SC  0
AC(0-7)  INPR, FGI  0 OUTR  AC(0-7),
FGO  0 If(FGI=1) then (PC  PC + 1)
If(FGO=1) then (PC  PC + 1) IEN  1
IEN  0
Microoperations

DESIGN OF BASIC COMPUTER
Hardware Components of BC
A memory unit: 4096 x 16. Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC
Control Logic Gates
-Input Controls of the nine registers
-Read and Write Controls of memory
-Set, Clear, or Complement Controls of the flip-flops
-S2, S1, S0 Controls to select a register for the bus
-AC, and Adder and Logic circuit

CONTROL OF REGISTERS AND MEMORY
LD(AR) = R'T0 + R'T2 + D'7IT3
CLR(AR) = RT0
INR(AR) = D5T4
Address Register; AR
Scan all of the register transfer statements that change the content of AR:
R’T0:
R’T2:
D’7IT3:
RT0:
D5T4:
AR  PC
AR  IR(0-11)
AR  M[AR]
AR  0
AR  AR + 1
LD(AR)
LD(AR)
LD(AR)
CLR(AR)
INR(AR)
AR
INR
CLR
Clock
To bus
From bus
12 12
D'7
I
T3
LD
T2
R
T0
D
T4

CONTROL OF FLAGS
pB7:
pB6:
RT2:
IEN  1 (I/O Instruction)
IEN  0 (I/O Instruction)
IEN  0 (Interrupt)
p = D7IT3 (Input/Output Instruction)
IEN: Interrupt Enable Flag
D7
I
T3
J
K
Q IEN
p
B7
B6
R
T2

CONTROL OF COMMON BUS
For
AR
D4T4: PC  AR D5T5:
PC  AR
x1 = D4T4 + D5T5
x1
x2
x3
x4
x5
x6
x7
Encoder
S 2
Multiplexer
S 1 bus select
inputs
S 0
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0
selected
register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

DESIGN OF ACCUMULATOR LOGIC
Circuits associated with
AC
All the statements that change the content of AC
16
16
8
Adder and
logic
circuit
16
AC
From DR
From INPR
Control
gates
16
To bus
LD INR CLR
Clock
D0T5:
D1T5:
D2T5:
pB11:
rB9:
rB7 :
rB6 :
rB11 :
rB5 :
AC  AC  DR AC  AC +
DR AC  DR
AC(0-7)  INPR
AC  AC
AC  shr AC, AC(15)  E
AC  shl AC, AC(0)  E
AC  0
AC  AC + 1
AND with DR Add
with DR Transfer
from DR
Transfer from INPR
Complement
Shift right
Shift left Clear
Increment

ALU (ADDER AND LOGIC CIRCUIT)
One stage of Adder and Logic
circuit
AND
ADD
DR
INPR
COM
J
K
Q
AC(i)
LD
F
A
C
From
INPR
bit(i)
DR(i)
AC(i)
SHR
AC(i
+1)
SHL
AC(i
-1)
C i
i+1
Ii

Register Transfer Language and Micro Operations

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