SlideShare a Scribd company logo

PHASE LOCKED LOOP FOR GSM 900

C
chirag2003

The document outlines the design of a phase locked loop (PLL) for GSM 900 specifications, detailing key parameters such as input frequency, supply voltage, and output frequency range. It includes simulations and schematics for various components like the phase frequency divider and charge pump, as well as completed tasks such as DRC and LVS checks. Future work involves completing the overall layout and post-layout simulations.

1 of 19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Submitted by: Chirag Patel Ravi Vachhani Vijay Sankar DESIGN OF A PHASE LOCKED LOOP FOR GSM 900
Specifications: Input Frequency: 200 – 220 MHz Supply Voltage: 3.3V DC Technology used: 0.25 μm CMOS Output Frequency Range: 800 - 900 MHz Settling Time: <10us
General block diagram A Phase Locked loop (PLL) is a system which generates an output signal which is synchronized in frequency and phase to an input signal.
Phase Frequency Divider schematic
PFD SIMULATION Case 1 :Ref2 leading Ref 1
PFD SIMULATION Case 2 : Ref 1 leading Ref 2
PFD SIMULATION Case 3 : In phase response
Charge Pump- Schematic
Charge Pump Simulation
Frequency Divider ( by 4) Schematic
Frequency Divider ( by 4)
VCO LC Oscillator
VCO Tuning Range
VCO Output
PLL
PLL Output
Layout
Things done : Schematics, Simulation and Layout of all individual blocks. DRC and LVS of all blocks. Things to do : Complete Layout of the entire system. LVS of the entire system Post Layout simulation
References [1] D.K. Shaeffer, A.R. Shahani, S.S. Mohan, H.Samavati, H.R. Rateh, M. Del Mar Hershenson, M. Xu, C.P, Yue, D.J. Eddleman, and T. Lee, “ A 115mW, 0.5-um CMOS GPS receiver with wide Dynamic-Range Active Filters, “ IEEE J. Solid-State Circuits, Vol.33, No.12, pp. 2219-2231, December 1998 [2] R.Best,&quot;Phase-Locked Loops&quot;, McGrawHill. [3] B.Razavi, &quot;Design of Analog CMOS Integrated Circuits&quot;, McGraw- Hill. [4] F. M. Gardner, &quot;Charge pump phase locked loops&quot; IEEE trans. on communications, Vol. COM-28, NO.11, Nov 1980. [5] Youngmin Kim, Bo Zhai and Byungwok Min, &quot;Frequency Synthesizer for GPS Radio Application&quot;.[6] Jenkin Chan, Vivian Lee, Amar Basu, “A 1.573-GHz Low power, Wide Locking Range GPS Frequency Synthesizer in 0.18-um CMOS”.

More Related Content

PPTX
Phase locked loop
imengineer
 
PDF
Phase locked loop
Muhammad Saad
 
PPTX
Phase locked loop design
Moin Aman
 
PDF
Design of all digital phase locked loop (d pll) with fast acquisition time
eSAT Journals
 
PPTX
Pll ppt
parassini
 
PPT
PHASE LOCK LOOPs
Rabindranath Tagore University, Bhopal
 
PPTX
Pll
katamthreveni
 
PDF
Introduction to pll
sartaj ahmed
 
Phase locked loop
imengineer
 
Phase locked loop
Muhammad Saad
 
Phase locked loop design
Moin Aman
 
Design of all digital phase locked loop (d pll) with fast acquisition time
eSAT Journals
 
Pll ppt
parassini
 
PHASE LOCK LOOPs
Rabindranath Tagore University, Bhopal
 
Pll
katamthreveni
 
Introduction to pll
sartaj ahmed
 

What's hot (20)

PPT
Directed decision phase locked loop
Hitham Jleed
 
PPTX
Phase Locked Loop (PLL)
Debayon Saha
 
PPTX
PLL & DLL DESIGN IN SIMULINK MATLAB
kartik pal
 
PPTX
Phase locked loop
Preet_patel
 
PPTX
DPLL PRESENTATION
Narendra-Naidu Lingutla
 
PPT
All Digital Phase Lock Loop 03 12 09
imranbashir
 
PPTX
Phase Locked Loop with Filter Banks for High Data Rate Satellite Link
chiragwarty
 
PPTX
Phase lock loop (pll)
Sulaim Ab Qais
 
PPT
Frequency Synthesized Signal Generator
DESH D YADAV
 
PPTX
(S.C.E.T) Appliction of pll fm demodulation fsk demodulation
Chirag vasava
 
PPTX
Pll
Satheeshkumar697
 
PDF
Ee443 phase locked loop - presentation - schwappach and brandy
Loren Schwappach
 
PDF
Phase locked loop techniques for fm demodulation and modulation
Harshal Ladhe
 
PDF
Pll Basic Linkedin2
Stanley Goldman
 
PDF
PLL Note
Pei-Che Chang
 
PDF
Phase Locked Loops (PLL) 1
Pei-Che Chang
 
PDF
Sub157
International Journal of Science and Research (IJSR)
 
PPT
Frequency synthesizer(mm)
Mahendra Mishra
 
PPTX
Non ideal effects of pll
Rabindranath Tagore University, Bhopal
 
PPTX
Direct digital frequency synthesizer
Venkat Malai Avichi
 
Directed decision phase locked loop
Hitham Jleed
 
Phase Locked Loop (PLL)
Debayon Saha
 
PLL & DLL DESIGN IN SIMULINK MATLAB
kartik pal
 
Phase locked loop
Preet_patel
 
DPLL PRESENTATION
Narendra-Naidu Lingutla
 
All Digital Phase Lock Loop 03 12 09
imranbashir
 
Phase Locked Loop with Filter Banks for High Data Rate Satellite Link
chiragwarty
 
Phase lock loop (pll)
Sulaim Ab Qais
 
Frequency Synthesized Signal Generator
DESH D YADAV
 
(S.C.E.T) Appliction of pll fm demodulation fsk demodulation
Chirag vasava
 
Pll
Satheeshkumar697
 
Ee443 phase locked loop - presentation - schwappach and brandy
Loren Schwappach
 
Phase locked loop techniques for fm demodulation and modulation
Harshal Ladhe
 
Pll Basic Linkedin2
Stanley Goldman
 
PLL Note
Pei-Che Chang
 
Phase Locked Loops (PLL) 1
Pei-Che Chang
 
Sub157
International Journal of Science and Research (IJSR)
 
Frequency synthesizer(mm)
Mahendra Mishra
 
Non ideal effects of pll
Rabindranath Tagore University, Bhopal
 
Direct digital frequency synthesizer
Venkat Malai Avichi
 
Ad

Similar to PHASE LOCKED LOOP FOR GSM 900 (20)

PDF
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS
IJMEJournal1
 
PDF
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS
IJMEJournal1
 
PDF
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...
VLSICS Design
 
PPTX
Dissertation on lv pll by dhwani sametrya
Dhwani Sametriya
 
PDF
O0704080084
IJERD Editor
 
PDF
RM03D-3_DCOBISC_06_07_09_Final
imranbashir
 
PPT
Si Intro(100413)
imsong
 
PPTX
Sistec ppt
hemant choubey
 
PDF
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATOR
ijseajournal
 
PDF
Fast Transient Response Low Drop-Out Voltage Regulator
ijesajournal
 
PDF
Fast Transient Response Low Drop-Out Voltage Regulator
ijesajournal
 
PPT
On Chip Calibration And Compensation Techniques (11 03 08)
imranbashir
 
PPT
Forharsha basha
Uday Reddy
 
PPT
Thesis presentation
Kangmas Zekon
 
PDF
DESIGN AND PERFORMANCE ANALYSIS OF NINE STAGES CMOS BASED RING OSCILLATOR
VLSICS Design
 
PDF
Project_Kaveh & Mohammad
Kaveh Dehno
 
PDF
MICROWAVE CAD LAB MICROWAVE CAD LABratory
wazie_abdulkawi
 
PDF
Design of High Speed Phase Frequency Detector in 0.18 μm CMOS Process for PLL...
Editor IJCATR
 
PDF
En34855860
IJERA Editor
 
PDF
Jv2416961699
IJERA Editor
 
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS
IJMEJournal1
 
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS
IJMEJournal1
 
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...
VLSICS Design
 
Dissertation on lv pll by dhwani sametrya
Dhwani Sametriya
 
O0704080084
IJERD Editor
 
RM03D-3_DCOBISC_06_07_09_Final
imranbashir
 
Si Intro(100413)
imsong
 
Sistec ppt
hemant choubey
 
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATOR
ijseajournal
 
Fast Transient Response Low Drop-Out Voltage Regulator
ijesajournal
 
Fast Transient Response Low Drop-Out Voltage Regulator
ijesajournal
 
On Chip Calibration And Compensation Techniques (11 03 08)
imranbashir
 
Forharsha basha
Uday Reddy
 
Thesis presentation
Kangmas Zekon
 
DESIGN AND PERFORMANCE ANALYSIS OF NINE STAGES CMOS BASED RING OSCILLATOR
VLSICS Design
 
Project_Kaveh & Mohammad
Kaveh Dehno
 
MICROWAVE CAD LAB MICROWAVE CAD LABratory
wazie_abdulkawi
 
Design of High Speed Phase Frequency Detector in 0.18 μm CMOS Process for PLL...
Editor IJCATR
 
En34855860
IJERA Editor
 
Jv2416961699
IJERA Editor
 
Ad

PHASE LOCKED LOOP FOR GSM 900

  • 1. Submitted by: Chirag Patel Ravi Vachhani Vijay Sankar DESIGN OF A PHASE LOCKED LOOP FOR GSM 900
  • 2. Specifications: Input Frequency: 200 – 220 MHz Supply Voltage: 3.3V DC Technology used: 0.25 μm CMOS Output Frequency Range: 800 - 900 MHz Settling Time: <10us
  • 3. General block diagram A Phase Locked loop (PLL) is a system which generates an output signal which is synchronized in frequency and phase to an input signal.
  • 5. PFD SIMULATION Case 1 :Ref2 leading Ref 1
  • 6. PFD SIMULATION Case 2 : Ref 1 leading Ref 2
  • 7. PFD SIMULATION Case 3 : In phase response
  • 10. Frequency Divider ( by 4) Schematic
  • 15. PLL
  • 18. Things done : Schematics, Simulation and Layout of all individual blocks. DRC and LVS of all blocks. Things to do : Complete Layout of the entire system. LVS of the entire system Post Layout simulation
  • 19. References [1] D.K. Shaeffer, A.R. Shahani, S.S. Mohan, H.Samavati, H.R. Rateh, M. Del Mar Hershenson, M. Xu, C.P, Yue, D.J. Eddleman, and T. Lee, “ A 115mW, 0.5-um CMOS GPS receiver with wide Dynamic-Range Active Filters, “ IEEE J. Solid-State Circuits, Vol.33, No.12, pp. 2219-2231, December 1998 [2] R.Best,&quot;Phase-Locked Loops&quot;, McGrawHill. [3] B.Razavi, &quot;Design of Analog CMOS Integrated Circuits&quot;, McGraw- Hill. [4] F. M. Gardner, &quot;Charge pump phase locked loops&quot; IEEE trans. on communications, Vol. COM-28, NO.11, Nov 1980. [5] Youngmin Kim, Bo Zhai and Byungwok Min, &quot;Frequency Synthesizer for GPS Radio Application&quot;.[6] Jenkin Chan, Vivian Lee, Amar Basu, “A 1.573-GHz Low power, Wide Locking Range GPS Frequency Synthesizer in 0.18-um CMOS”.