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First review-Dissertation-II
11/06/2025
School of Engineering
Department of Electronics and communication
PIP:6002 Dissertation
THIRD REVIEW
Implementation of STFT-Based Audio Processing with LSTM
Acceleration on Cyclone V FPGA
PIP 6002: THIRD REVIEW
Second review-Dissertation-II
11/06/2025
GUIDED BY,
Dr Muthupandi Gandhi,
ASSOCIATE PROFESSOR
PRESENTED BY,
Muskan.S,
20232ESV0002,
M Tech, Embedded and VLSI System.
Second review-Dissertation-II
11/06/2025
ABSTRACT
1.This project implements Short-Time Fourier Transform (STFT)-based audio processing on a Cyclone V FPGA,
integrating Long Short-Term Memory (LSTM) networks to enhance time-frequency analysis.
2.The design incorporates FIR filtering for signal preprocessing, Verilog-based STFT computation, and LSTM
acceleration, ensuring efficient resource utilization and parallel processing on FPGA.
3.The proposed implementation enables real-time spectral analysis of audio signals with improved accuracy and
computational efficiency, demonstrating the feasibility of FPGA-based deep learning acceleration for signal
processing applications.
Second review-Dissertation-II
11/06/2025
PROBLEM STATEMENT
1.Traditional audio processing techniques struggle with real-time spectral analysis due to high
computational complexity and latency, limiting their effectiveness in embedded systems.
2.Implementing STFT on an FPGA requires efficient resource management and optimization to
handle large-scale signal transformations while maintaining accuracy.
3.There is a need for integrating LSTM acceleration to enhance the time-frequency analysis of
audio signals, enabling improved performance in real-time applications.
Second review-Dissertation-II
INFERENCE
Inference:
1.Efficient Real-Time Processing: The implementation of STFT on a Cyclone V FPGA,
combined with LSTM acceleration, enables real-time spectral analysis of audio signals, making it
suitable for low-latency applications.
2.Optimized Resource Utilization: The integration of FIR filtering and hardware-aware
optimizations ensures efficient FPGA resource usage while maintaining computational accuracy
and speed.
3.Enhanced Signal Analysis: The use of LSTM improves the interpretability and performance of
time-frequency analysis, demonstrating the potential of deep learning-based enhancements for
FPGA-based audio processing.
4.Scalability and Future Scope: The project highlights the feasibility of FPGA-accelerated deep
learning for signal processing, paving the way for future improvements such as adaptive filtering,
reduced power consumption, and real-time AI-driven audio enhancement techniques.
Second review-Dissertation-II
11/06/2025
PROPOSED METHOD
1.Preprocessing & FIR Filtering – The input audio signal is filtered using an FIR filter to remove
noise and enhance relevant frequencies.
2.STFT Computation – The signal is divided into frames, and STFT is applied using FFT to obtain
a time-frequency representation, implemented on a Cyclone V FPGA.
3.LSTM Enhancement – An LSTM network processes STFT outputs to capture temporal
dependencies and improve spectral resolution.
4.FPGA Optimization – Parallel processing and pipeline architecture are used to enhance speed,
reduce latency, and optimize resource utilization.
5.Performance Evaluation – The system is tested for accuracy, efficiency, and real-time
processing, demonstrating FPGA-based deep learning acceleration benefits. 🚀
Second review-Dissertation-II
Load the csv to MATLAB
Step2: extracts the values
Step 3:extracting the input waveforms
Generated input signal
Step 4:generating the stft spectogram
Step 5: plotting the frequency response of first filter
Step 8: Filtering the signals
Step 8:Frequency response of the signals
Spectrogram analysis
Implementing on Quartus prime
Steps to add the csv dat to quartus prime and simulate it
1.Convert the data to .mif file
2.Add the .mif file to megawizard pulg in manager as ROM data
3.Generate a hdl file
Results interpreted using the .mif files in matlab
Hardware setup
LED LIGHT INDICATIONS
Testing and Simulation
To validate functionality, a Verilog testbench was created to
simulate the system. The testbench applies clock and reset signals,
test inputs, and monitors the output. The following is an example
testbench code for validation:
Simulated using the Modelsim
MATLAB simulation
stft implementation and lstm implementation
Key Formulas
1. Short-Time Fourier Transform (STFT): S(t, f) = ∫ x( )w( - t)e^(-
τ τ
j2 f )d , where w is the window function.
π τ τ
2. FIR Filter Output: y[n] = (b_k * x[n-k]) for k = 0 to N-1, where b_k
Σ
are filter coefficients.
Example Parameters for FIR Filters
stft implementation and lstm implementation
stft implementation and lstm implementation
Hardware Setup
- Configured Cyclone V FPGA using Quartus Prime.
- Integrated USB Blaster for programming and debugging.
- Verified with ModelSim simulations.
Software Tools
- MATLAB for signal processing simulations.
- Quartus Prime for FPGA configuration.
- ModelSim for waveform and timing analysis.
Conclusion and Future Work
- Successful hardware-software co-design.
- Cyclone V FPGA accelerated system.
- Future Work:
- Multi-channel audio support.
- More complex LSTM models.
- Audio classification integration.
Second review-Dissertation-II
References
1.O'Shaughnessy, D. (2000). Speech Communications: Human and Machine. IEEE Press.
2.Allen, J. B. (1977). Short-term spectral analysis, synthesis, and modification by discrete Fourier transform. IEEE
Transactions on Acoustics, Speech, and Signal Processing, 25(3), 235-238.
3.Hochreiter, S., & Schmidhuber, J. (1997). Long short-term memory. Neural Computation, 9(8), 1735-1780.
4.Lyons, R. G. (2010). Understanding Digital Signal Processing. Prentice Hall.
5.Smith, S. W. (2003). The Scientist and Engineer’s Guide to Digital Signal Processing. California Technical Publishing.
6.Liu, Y., Wang, Y., & Li, S. (2022). FPGA-based implementation of deep learning for real-time signal processing. IEEE
Access, 10, 5423-5435.
7.Sharma, A., Gupta, P., & Verma, R. (2021). A hardware-efficient approach to STFT computation for embedded audio
applications. Journal of Embedded Systems, 15(2), 120-132.
8.IEEE Standard for Floating-Point Arithmetic (IEEE 754-2019). IEEE Computer Society, 2019.
Second review-Dissertation-II
THANK YOU

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stft implementation and lstm implementation

  • 1. First review-Dissertation-II 11/06/2025 School of Engineering Department of Electronics and communication PIP:6002 Dissertation THIRD REVIEW
  • 2. Implementation of STFT-Based Audio Processing with LSTM Acceleration on Cyclone V FPGA PIP 6002: THIRD REVIEW Second review-Dissertation-II 11/06/2025 GUIDED BY, Dr Muthupandi Gandhi, ASSOCIATE PROFESSOR PRESENTED BY, Muskan.S, 20232ESV0002, M Tech, Embedded and VLSI System.
  • 3. Second review-Dissertation-II 11/06/2025 ABSTRACT 1.This project implements Short-Time Fourier Transform (STFT)-based audio processing on a Cyclone V FPGA, integrating Long Short-Term Memory (LSTM) networks to enhance time-frequency analysis. 2.The design incorporates FIR filtering for signal preprocessing, Verilog-based STFT computation, and LSTM acceleration, ensuring efficient resource utilization and parallel processing on FPGA. 3.The proposed implementation enables real-time spectral analysis of audio signals with improved accuracy and computational efficiency, demonstrating the feasibility of FPGA-based deep learning acceleration for signal processing applications.
  • 4. Second review-Dissertation-II 11/06/2025 PROBLEM STATEMENT 1.Traditional audio processing techniques struggle with real-time spectral analysis due to high computational complexity and latency, limiting their effectiveness in embedded systems. 2.Implementing STFT on an FPGA requires efficient resource management and optimization to handle large-scale signal transformations while maintaining accuracy. 3.There is a need for integrating LSTM acceleration to enhance the time-frequency analysis of audio signals, enabling improved performance in real-time applications.
  • 5. Second review-Dissertation-II INFERENCE Inference: 1.Efficient Real-Time Processing: The implementation of STFT on a Cyclone V FPGA, combined with LSTM acceleration, enables real-time spectral analysis of audio signals, making it suitable for low-latency applications. 2.Optimized Resource Utilization: The integration of FIR filtering and hardware-aware optimizations ensures efficient FPGA resource usage while maintaining computational accuracy and speed. 3.Enhanced Signal Analysis: The use of LSTM improves the interpretability and performance of time-frequency analysis, demonstrating the potential of deep learning-based enhancements for FPGA-based audio processing. 4.Scalability and Future Scope: The project highlights the feasibility of FPGA-accelerated deep learning for signal processing, paving the way for future improvements such as adaptive filtering, reduced power consumption, and real-time AI-driven audio enhancement techniques.
  • 6. Second review-Dissertation-II 11/06/2025 PROPOSED METHOD 1.Preprocessing & FIR Filtering – The input audio signal is filtered using an FIR filter to remove noise and enhance relevant frequencies. 2.STFT Computation – The signal is divided into frames, and STFT is applied using FFT to obtain a time-frequency representation, implemented on a Cyclone V FPGA. 3.LSTM Enhancement – An LSTM network processes STFT outputs to capture temporal dependencies and improve spectral resolution. 4.FPGA Optimization – Parallel processing and pipeline architecture are used to enhance speed, reduce latency, and optimize resource utilization. 5.Performance Evaluation – The system is tested for accuracy, efficiency, and real-time processing, demonstrating FPGA-based deep learning acceleration benefits. 🚀
  • 8. Load the csv to MATLAB
  • 10. Step 3:extracting the input waveforms
  • 12. Step 4:generating the stft spectogram
  • 13. Step 5: plotting the frequency response of first filter
  • 14. Step 8: Filtering the signals
  • 15. Step 8:Frequency response of the signals
  • 17. Implementing on Quartus prime Steps to add the csv dat to quartus prime and simulate it 1.Convert the data to .mif file 2.Add the .mif file to megawizard pulg in manager as ROM data 3.Generate a hdl file
  • 18. Results interpreted using the .mif files in matlab
  • 21. Testing and Simulation To validate functionality, a Verilog testbench was created to simulate the system. The testbench applies clock and reset signals, test inputs, and monitors the output. The following is an example testbench code for validation:
  • 25. Key Formulas 1. Short-Time Fourier Transform (STFT): S(t, f) = ∫ x( )w( - t)e^(- τ τ j2 f )d , where w is the window function. π τ τ 2. FIR Filter Output: y[n] = (b_k * x[n-k]) for k = 0 to N-1, where b_k Σ are filter coefficients.
  • 26. Example Parameters for FIR Filters
  • 29. Hardware Setup - Configured Cyclone V FPGA using Quartus Prime. - Integrated USB Blaster for programming and debugging. - Verified with ModelSim simulations.
  • 30. Software Tools - MATLAB for signal processing simulations. - Quartus Prime for FPGA configuration. - ModelSim for waveform and timing analysis.
  • 31. Conclusion and Future Work - Successful hardware-software co-design. - Cyclone V FPGA accelerated system. - Future Work: - Multi-channel audio support. - More complex LSTM models. - Audio classification integration.
  • 32. Second review-Dissertation-II References 1.O'Shaughnessy, D. (2000). Speech Communications: Human and Machine. IEEE Press. 2.Allen, J. B. (1977). Short-term spectral analysis, synthesis, and modification by discrete Fourier transform. IEEE Transactions on Acoustics, Speech, and Signal Processing, 25(3), 235-238. 3.Hochreiter, S., & Schmidhuber, J. (1997). Long short-term memory. Neural Computation, 9(8), 1735-1780. 4.Lyons, R. G. (2010). Understanding Digital Signal Processing. Prentice Hall. 5.Smith, S. W. (2003). The Scientist and Engineer’s Guide to Digital Signal Processing. California Technical Publishing. 6.Liu, Y., Wang, Y., & Li, S. (2022). FPGA-based implementation of deep learning for real-time signal processing. IEEE Access, 10, 5423-5435. 7.Sharma, A., Gupta, P., & Verma, R. (2021). A hardware-efficient approach to STFT computation for embedded audio applications. Journal of Embedded Systems, 15(2), 120-132. 8.IEEE Standard for Floating-Point Arithmetic (IEEE 754-2019). IEEE Computer Society, 2019.