Superscalar and VLIW architectures
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This document discusses superscalar and VLIW architectures. Superscalar processors can execute multiple independent instructions in parallel by checking for dependencies between instructions. VLIW architectures package multiple operations into very long instruction words to execute in parallel on multiple functional units with scheduling done at compile-time rather than run-time. The document compares CISC, RISC, and VLIW instruction sets and outlines advantages and disadvantages of the VLIW approach.
Superscalar and VLIW architectures
- 1. Superscalar and VLIW Architectures Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 2. Outline • Types of architectures • Superscalar • Differences between CISC, RISC and VLIW • VLIW Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 3. Parallel processing Processing instructions in parallel requires three major tasks: 1. checking dependencies between instructions to determine which instructions can be grouped together for parallel execution; 2. assigning instructions to the functional units on the hardware; 3. determining when instructions are initiated placed together into a single word. Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 4. Major categories From Mark Smotherman, “Understanding EPIC Architectures and Implementations” VLIW – Very Long Instruction Word EPIC – Explicitly Parallel Instruction Computing Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 5. Major categories Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 6. Superscalar Processors • Superscalar processors are designed to exploit more instruction-level parallelism in user programs. • Only independent instructions can be executed in parallel without causing a wait state. • The amount of instruction-level parallelism varies widely depending on the type of code being executed. Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 7. Pipelining in Superscalar Processors • In order to fully utilise a superscalar processor of degree m, m instructions must be executable in parallel. This situation may not be true in all clock cycles. In that case, some of the pipelines may be stalling in a wait state. • In a superscalar processor, the simple operation latency should require only one cycle, as in the base scalar processor. Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 8. Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 9. Superscalar Execution Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 10. Superscalar Implementation • Simultaneously fetch multiple instructions • Logic to determine true dependencies involving register values • Mechanisms to communicate these values • Mechanisms to initiate multiple instructions in parallel • Resources for parallel execution of multiple instructions • Mechanisms for committing process state in correct order Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 11. Some Architectures • PowerPC 604 – six independent execution units: • Branch execution unit • Load/Store unit • 3 Integer units • Floating-point unit – in-order issue – register renaming • Power PC 620 – provides in addition to the 604 out-of-order issue • Pentium – three independent execution units: • 2 Integer units • Floating point unit – in-order issue Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 12. The VLIW Architecture • A typical VLIW (very long instruction word) machine has instruction words hundreds of bits in length. • Multiple functional units are used concurrently in a VLIW processor. • All functional units share the use of a common large register file. Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 13. Comparison: CISC, RISC, VLIW Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 14. Dr. Amit Kumar, Dept of CSE, JUET, Guna
- 15. Advantages of VLIW Compiler prepares fixed packets of multiple operations that give the full "plan of execution" – dependencies are determined by compiler and used to schedule according to function unit latencies – function units are assigned by compiler and correspond to the position within the instruction packet ("slotting") – compiler produces fully-scheduled, hazard- free code => hardware doesn't have to "rediscover" dependencies or scheduleDr. Amit Kumar, Dept of CSE, JUET, Guna
- 16. Disadvantages of VLIW Compatibility across implementations is a major problem – VLIW code won't run properly with different number of function units or different latencies – unscheduled events (e.g., cache miss) stall entire processor Code density is another problem – low slot utilization (mostly nops) – reduce nops by compression ("flexible VLIW", "variable-length VLIW")Dr. Amit Kumar, Dept of CSE, JUET, Guna