Tdm to vo ip 2
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This document describes a hardware design that includes components like a codec clock, PLL, and packet memory. It maps these components, describes signal connections between them, and includes processes for transferring data between the memory and codec. The design takes in audio data at 2.048 MHz, converts it to 75 MHz using a PLL, stores it in packet memory, and outputs it to a codec. It handles transferring 160 bytes per packet across two memory banks.
Tdm to vo ip 2
- 1. Guided by Dr. Sunil Kumar. S. Manvi Project Members Abhiroop. M. N Asha. A. R Nagapooja. K Pavan. S
- 2. component codecclk PORT ( inclk0 : IN STD_LOGIC ; c0 : OUT STD_LOGIC ); end component; Codec clkIn clk (25 Mhz) C0 (2.048 Mhz)
- 3. component pll75m PORT ( inclk0 : IN STD_LOGIC ; c0 : OUT STD_LOGIC ); end component; PLL 75MhzIn clk (2.048 Mhz) C0 (75 Mhz)
- 4. component packetmem PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC := '1'; outclock : IN STD_LOGIC ; rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); end component; PLL 75Mhz data In clock Out clock WR Address RD Address WR Enable Q
- 5. codecclk_inst : codecclk PORT MAP ( inclk0 => clkin, c0 => clk2048m ); pll75m_inst : pll75m PORT MAP ( inclk0 => clkin, c0 => clk75m );
- 6. packetmem_init : packetmem PORT MAP( data => rxmemip, inclock => clk2048m, outclock => clk75m, rdaddress => (bytecnt(3 downto 0) +1) & (not bank) & rxmemwa, wraddress => bytecnt(3 downto 0) & bank & rxmemwa, wren => rxmemwe, q => rdatareg_1 ); bytecnt bank rxmemwa
- 7. rdata <= CODEC_VOUT1 when (bytecnt =1 or bytecnt =2 or bytecnt =3 or bytecnt =4) else CODEC_VOUT2 when (bytecnt =5 or bytecnt =6 or bytecnt =7 or bytecnt =8) else CODEC_VOUT3 when (bytecnt =9 or bytecnt =10 or bytecnt =11 or bytecnt =12) else CODEC_VOUT4 when (bytecnt =13 or bytecnt =14 or bytecnt =15 or bytecnt =16) ; SYNC_D(1) <= '1' when (bytecnt =0 and bitcnt =7)else '0'; SYNC_D(2) <= '1' when (bytecnt =1 and bitcnt =7)else '0'; SYNC_D(3) <= '1' when (bytecnt =2 and bitcnt =7) else '0'; SYNC_D(4) <= '1' when (bytecnt =3 and bitcnt =7) else '0'; SYNC_D(5) <= '1' when (bytecnt =4 and bitcnt =7) else '0'; SYNC_D(6) <= '1' when (bytecnt =5 and bitcnt =7) else '0'; SYNC_D(7) <= '1' when (bytecnt =6 and bitcnt =7) else '0'; SYNC_D(8) <= '1' when (bytecnt =7 and bitcnt =7) else '0';
- 8. 1 bit 1byte 160 bytes 1byte 1 bit Codec_Vout0 rdata tdatareg rdatareg Codec_Vin2 160 bytes Bank 0 Bank 1
- 9. rx_sm1:process (clk2048m) begin if ( clk2048m 'event and clk2048m = '0') then rdata1 <= rdata; end if; end process; rx_sm:process (clk2048m) begin if ( clk2048m 'event and clk2048m='1') then if( int_reset = '1') then bitcnt <= (others=>'0'); bytecnt <= (others=>'0'); framecnt <= (others=>'0'); end if; if( framecnt = "10100000") then framecnt <= "00000000"; bank <= not bank; end if;
- 10. if( bitcnt = 1) then rxmemip <= rdatareg ; rxmemwa <= framecnt; rxmemwab <= bank; rxmemwe <= '1'; else rxmemwe <= '0'; end if; end if; end if; else rdatareg1 <= rdatareg1(6 downto 0) & rdata1; bitcnt <= bitcnt + 1; if( bitcnt = 7) then if( bytecnt = framelength ) then bytecnt <= (others=>'0'); framecnt <= framecnt + 1; else bytecnt <= bytecnt + 1; end if; end if; if( bitcnt = 0) then rdatareg <= rdatareg1; end if;
- 11. if ( clk2048m'event and clk2048m='1') then if( bitcnt = 7)then tdatareg0 <= rdatareg_1; else tdatareg0 <= tdatareg0(6 downto 0)& '0'; end if; end if; CODEC_VIN2 <= tdatareg0(7);