![ACEEE International Journal on Communication, Vol 1, No. 2, July 2010
The Analysis of Dead Time on Switching Loss
in High and Low Side MOSFETs of ZVS
Synchronous Buck Converter
N.Z. Yahaya, M.K. Lee, K.M. Begam & M. Awan
Power & Energy Group
Electrical Engineering Department
Universiti Teknologi PETRONAS
Bandar Seri Iskandar, Tronoh, 31750 Perak, MALAYSIA
Email: norzaihar_yahaya@petronas.com.my
Abstract—This work is about the analysis of dead time used, yet there are limitations in the design. When the
variation on switching losses in a Zero Voltage Switching frequency is increased, the gate driving losses will
(ZVS) synchronous buck converter (SBC) circuit. In high experience an increase in power dissipation. This in turn
frequency converter circuits, switching losses are affects the performance of the converter. The duty ratio
commonly linked with high and low side switches of SBC or pulse width, D, dead time, TD, and the resonant
circuit. They are activated externally by the gate driver inductor, Lr are the limiting parameters that influence
circuit. The duty ratio, dead time and resonant inductor the gate driver operation from conducting optimally.
are the parameters that affect the efficiency of the circuit. These parameters had been analyzed in [6] and the
These variables can be adjusted for the optimization results show that the optimized values are found to be
purposes. The study primarily focuses on varying the D = 20 %, TD = 15 ns and Lr = 9 nH at 1 MHz switching
settings of input pulses of the MOSFETs in the resonant frequency. However, the values of switching losses in
gate driver circuit which consequently affects the the MOSFET are still very high. Therefore, the TD
performance of the ZVS synchronous buck converter parameter is adjusted to optimize switching losses. This
circuit. Using the predetermined inductor of 9 nH, the is the primary objective in this work.
frequency is maintained at 1 MHz for each cycle
transition. The switching loss graph is obtained and
switching losses for both S1 and S2 are calculated and II. PROPOSED RGD-SBC CIRCUIT
compared to the findings from previous work. It has Vca
shown a decrease in losses by 13.8 % in S1. A dead time of
15 ns has been determined to be optimized value in the
Vs
SBC design.
Keywords— PSpice Simulation, Resonant Gate Driver,
Synchronous Buck Converter, Switching Losses
I. INTRODUCTION
In megahertz switching frequency, synchronous buck
converter (SBC) circuit may contain losses which are
normally caused by the high and low side switches. The
resonant gate driver (RGD) circuit is applied due to its
suitability in driving MOS-gated power switches in high
frequency applications. High power Metal Oxide
Semiconductor Field Effect Transistor (MOSFET) is
used as a switch in this work of the proposed RGD LEFT CIRCUIT RIGHT CIRCUIT
circuit [1]. At present, there are various types of RGD Figure 1. Proposed RGD Circuit
circuits commercially available [2-4]. The resonant
circuit transfers energy from the parasitic input Fig. 1 shows the proposed RGD circuit which is used
capacitance of the power switching devices. This energy in this work. The circuit is suitable for SBC circuit
transfer prevents dissipation of the capacitive energy in because with a single input voltage, Vin, two output gate
the driver circuit which may otherwise destroy one or voltages will be generated complimentarily. Fig. 2
more components. shows two output waveforms generated from an input
voltage of the SBC circuit.
The resonant circuit includes an inductor in the driver
circuit and one or more discrete capacitors are also
included within the driver circuit to maintain resonance
at a given frequency regardless of parasitic capacitance
variation [5]. Although high frequency MOSFET is
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![ACEEE International Journal on Communication, Vol 1, No. 1, July 2010
20V of TD are unchanged, any changes in D will eventually
Vgs, S1 Vgs, S2
result in different switching losses in the circuit.
10V
0V
SEL>>
III. METHODOLOGY
-10V
V(S1:g,S1:s) V(S2:g,S2:s)
50V
In this work, the proposed RGD-SBC circuit is
simulated using PSpice software. The pulse settings of
Input voltage, Vsource
four MOSFETs in the proposed RGD circuit are
45V
40V
modified carefully resulting in different values of TD.
173.5us 173.6us
V(Vp_source:+)
173.8us 174.0us
Time
174.2us 174.4us 174.6us 174.8us
The RGD circuit accordingly will affect the TD of the
Figure 2. Gate Voltage of S1 and S2 & Input Voltage of SBC synchronous buck converter circuit where the switching
losses of the circuit are measured at the two MOSFET
As it can be seen, the left circuit of the proposed switches of S1 and S2. The results are then measured,
RGD circuit is the DC-RGD while the right circuit is compared and analyzed. The conclusion is then drawn.
just the symmetrical of the left circuit. The circuit has
the advantages with simplicity having symmetrical
pattern which gives better choice of component and IV. RESULTS AND DISCUSSION
parameter mo© 2010 ACEEEdification. In addition, a
bootstrap circuit for high side driver [3] consisting of a A. Proposed RGD Circuit
diode, Da and a capacitor, Ca are added into the circuit. The dead time settings on each pulse generator in the
The importance of bootstrap circuitry is that it aids in
proposed RGD circuit of Fig. 1 are shown in Table I
circuit simplification, symmetrical behavior and also
minimizes switching loss. Besides that, it has less while the pulse width settings are tabulated in Table II.
impact on the parasitic capacitance as well as better Fig. 4 to Fig. 6 indicate the waveforms of dead time,
immunity in dv/dt turn-on. The proposed RGD circuit delay time and pulse width.
can conduct in two modes, complementary mode and
symmetrical mode. In the complementary mode, it TABLE I.
provides two drive signals with duty cycle D and 1-D, SETTINGS FOR DEAD TIME IN PROPOSED RGD CIRCUIT
respectively. This mode is suitable for driving two Dead time Initial Delay time for each
MOSFETs in a synchronous buck converter. delay voltage pulse
In the circuit, the four units of MOSFETs (Q1, Q2, TD= TD3 time, td1 td2 td3 td4
Q3, Q4) settings will be reassigned carefully while other TD1= (ns) td, initial (ns) (ns (ns) (ns)
values which include oscillation frequency = 1 MHz, D TD2 (ns) )
= 20 % and Lr = 9 nH remain unchanged. Theoretically, (ns)
when parameters of MOSFETS, Q1 and Q2 of the RGD 5 23 15 15 22 284 947
circuit are changed, dead time of the left circuit, TD1 will 2
vary. Similarly, when parameter values of Q3 and Q4 are 15 15 15 15 23 284 955
changed, then dead time of the right circuit, TD2 will be 2
also be modified. Consequently, the overall value of TD 30 5 15 15 24 284 969
in the proposed synchronous buck converter circuit as 7
shown in Fig. 3 will also be modified. This gives result
in new values of D and (1-D) in the synchronous buck
circuit. S1 is the high side switch while S2 is the lower
side switch and the switching losses of the circuit will TABLE II
be measured from these two switches. Overall, it is SETTINGS FOR PULSE WIDTH IN PROPOSED RGD CIRCUIT
expected that the by varying the value of TD, the Dead time Pulse Width
performance of the SBC circuit will be affected,
accordingly. TD= TD1= Vp1 Vp2 Vp3 Vp4 PWS1 PWS2
TD2 (ns) (ns) (ns) (ns) (ns) (ns)
(ns)
5 200 786 654 331 201 769
15 200 765 654 312 211 759
30 200 740 654 286 229 741
The dead times are varied in order to evaluate the
performance of the circuit. For different dead times, the
initial delay time, td,initial is set to be constant at 15 ns.
Figure 3. Proposed Synchronous Buck Converter with ZVS Therefore, the first delay time for voltage pulse one, td1
is equal to td,initial. By taking TD=15 ns as reference, it can
When the values of switching frequency equals to 1 be observed that only delay time for voltage pulse 1 and
MHz and Lr = 9 nH, together with the optimized value 3, td1 and td3 , and pulse width of voltage pulse of 1 and
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![ACEEE International Journal on Communication, Vol 1, No. 1, July 2010
3, PW1 and PW3, are changed in order to obtain the dead the dead time when both switches are not conducting.
times of 5 ns and 30 ns. The table also shows that when Fig. 7 shows the operating waveforms generated from
TD1=TD2 increases, TD3 decreases instead. the left side of the proposed RGD circuit in Fig. 1.
6.0V
Q1 Q2 Q1
Q2 Q1 Q2
5.0
iL1
4.0V 0
V(Q1:g,Q1:s) V(Q2:g,Q2:s) - I(L1)
Vp1 Q3 Q4 Q3
5.0
Vp2
2.0V 0
SEL>> iL2
V(Q3:g,Q3:s) V(Q4:g,Q4:s) - I(L2)
TD1 TD1 20V
Vgs,S2 Vgs,S1
0V
0V
-20V
1.9698ms 1.9699ms 1.9700ms 1.9701ms 1.9702ms 1.9703ms 1.9704ms 1.9705ms 1.9706ms 1.9707ms 1.9708ms 1.9709ms 1.9710ms 1.9711ms
V(S1:g,S1:s) V(S2:g,S2:s)
Time
-1.0V
-0.1us 0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us 1.1us 1.2us 1.3us 1.4us
V(Q1:g,Q1:s) V(Q2:g,Q2:s)
Time
Figure 7. Operating Waveforms of Proposed RGD Circuit
Figure 4. Indication of Pulse Width, Dead Time and Delay Time of
Q1 and Q2 MOSFETs for TD=15 ns Pulses from Vp1 and Vp2 are fed into the MOSFETS,
td2 Q1 and Q2 on the left side of RGD circuit. From the
The graph of Fig. 4 is generated from the simulation
td, initial = td1
waveform, Q1 and Q2 are complementary driving pair
of Vgs,Q1 and Vgs,Q2. Both Q1 and Q2 MOSFETs conduct inherited from the conventional driver. First, when Q1 is
complementarily to each other. The time when both switched on, the inductor current of the left circuit, iL1
MOSFETs are not conducting is known as the dead starts to conduct and it is charged to maximum. The
time, TD1. Vp1 is the pulse width of Q1 and similarly to characteristic impedance of the resonant circuit can be
Vp2, the pulse width of Q2. td, initial which is equal to td1 is represented by (1)
the initial delay time, set at a constant value of 15 ns. td2
on the other hand is the delay time before Q2 starts to Zo =
LR
conduct. C in
(1)
6.0V
Q3 Q4 Q3
where LR is the resonant inductor equivalent to 9 nH.
The rise time tr can be estimated by (2)
π
4.0V
Vp3 Vp4 tr = LRCin (2)
2
The duration of this charging current depends on the
2.0V
TD2 TD2
value of LR for being the time constant of the circuit. If
0V
td3 the duration of the discharging current is not sufficient,
td4 it will cause current oscillation when Q1 is turned off
[1]. On the other hand, D1 and D2 are designed to clamp
-1.0V
-0.1us 0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us 1.1us 1.2us 1.3us 1.4us
V(Q3:g,Q3:s) V(Q4:g,Q4:s)
Vgs and to provide low impedance path for the inductor
Time
Figure 5. Indication of Pulse Width, Dead Time and Delay Time of current and recover the driving energy which is
Q3 and Q4 MOSFETs for TD=15 ns
represented by (3)
Fig. 5 shows the pulse width for Q3, Vp3 and Q4,
Vp4. td3 is the delay time before the MOSFET Q3 starts trec = π LRCin (3)
to conduct. Similarly, td4 is the delay time before Q4
turns on. On the other hand, TD2 is the dead time when where Cin is the input gate capacitance of high side
both MOSFETs, Q3 and Q4 are off. switch, S1. On the other hand, the peak time is defined
15V
by (4)
4 LR
S2 2 LR × − RG
2
−1 C in
tan
R
10V S1 S1
PWS2
t rec = (4)
PWS1 TD3
TD3 4 LR
2× − RG 2
5V
C in
0V
After iL1 has been fully charged to peak current and at
2.9698ms 2.9699ms 2.9700ms 2.9701ms 2.9702ms 2.9703ms 2.9704ms 2.9705ms 2.9706ms 2.9707ms 2.9708ms 2.9709ms 2.9710ms 2.9711ms the same moment Vgs,S1 is clamped at Vca by diode D1, iL1
flows according to the path Q1-L1-Vgs,S1. The inductor
V(S1:g,S1:s) V(S2:g,S2:s)
Time
Figure 6. Indication of Pulse Width and Delay Time for S1 and S2 for current can be represented by equation (5).
TD=15 ns
4 LR
R
−RG
2
The gate source voltage of both switches, Vgs,S1 and i L1 (t peak ) =
2Vca − G •t
•e 2 LR •sin
Cin
2 LR
•t
(5)
4 LR
Vgs,S2 is shown in Fig. 6. The maximum of Vgs,S1 is at 10 Cin
−RG
2
V and PWS1 is the pulse width of S1. Vgs,S2 goes to a
maximum value of 12 V with pulse width PWS2. TD3 is
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![ACEEE International Journal on Communication, Vol 1, No. 1, July 2010
C. Switching Losses of SBC at TD = 15 ns It can also be observed that the positive peak is
The power losses of the circuit are interpreted by higher than the negative. This shows that the power
generating the turn-off switching loss waveform of S1 losses are not equally distributed in S1. In the circuit, S1
and turn-on switching loss of S2 as shown in Fig. 9. is dominant in generating the power loss of the SBC
100W
70.096 W 95.242 W circuit. Thus, Ls and Cs has been added to the circuit in
S2 turn-on S1 turn-off parallel with S1 to solve this problem. Meanwhile, Cx
transition transition
has also been added in order to prevent the floating
50W
40 ns 35 ns
0W
drain voltage of S1. Hence, theoretically, Ls, Cs and Cx
Psw,S1 is positive have to be varied to reduce the switching losses at S1.
-50W
However, S2 turn-on switching losses have increased by
15.12 % compared to the study in [1]. Fig. 11 shows
the operating waveforms for S2.
-100W
173.5us 173.6us 173.8us 174.0us 174.2us 174.4us 174.6us 174.8us
V(S1:d,S1:s) * ID(S1) V(S2:d,S2:s) * ID(S2)
Time
Figure 9. Turn-Off Switching Loss of S1 and Turn-On Switching Loss
of S2
From the waveforms, the switching time for S1 turn-
off transition is 35 ns and for S2, 40 ns. The calculation
of switching losses is tabulated in Table IV and the
evaluated results are compared with [1].
TABLE III
COMPARISON OF DATA [1] WITH THIS WORK AT T =15NS D
From [1] From %
this work discrepanc
y
S1 Turn-off Peak 65.000 57.118 - 13.80 %
Vds * Ids W W
S1 Turn-off 1.138 W 1.000 W - 13.80 %
Switching Losses
Figure 11. Operating Waveforms of S2
S2 Turn-on Peak 95.000 64.790 - 46.63 %
Vds * Ids W W Compared to S1, there is no floating point at Vds, S2.
S2 Turn-on 1.100 W 1.296 W + 15.12 % As expected there is reduction in the turn-on switching
Switching Losses losses and in return, the performance and reliability of
From the results, it can be observed that the turn-off the SBC circuit have improved.
switching losses of S1 have decreased. Otherwise, the
problem of floating Vds,S1 can cause the switching power D. Comparison of Circuit Performance for Several
loss to float as well. Conventionally, as most described TDs
in literature, the switching losses will be high and
unfortunately they are ignored. The aim is to generate With other parameter values remain unchanged
the drain voltage of less than 0.7 V during its turn-off or except for TD, the overall performance of the circuit is
near to zero value during the entire turn-off transition analyzed. The circuit performance at TD =5 ns, 15 ns,
time. Similarly to Vds,S2, having a zero drain voltage can and 30 ns is shown in Table V and Table VI.
result in zero switching loss since their drain currents
conduct at this time. This situation can be seen in the TABLE I
Fig. 10. PARAMETER EVALUATION FOR VARYING T S D
100W
TD Vout Iout tbd PCOND PBD
(V) (A) (ns) (W) (W)
0W
Floating switching 5ns 14.06 1.41 30 0.102 0.135
power loss for entire Vds 1
-100W
turn-off time 15ns 13.91 1.391 33 0.100 0.149
V(S1:d,S1:s) * ID(S1)
50 15 ns 10.12 1.520 24 0.068 0.026
25 [1] 8
0 Floating 0 < Vds < 0.7 V 30ns 14.15 1.41 18 0.103 0.082
-25
5
SEL>>
-50
169.6us 169.7us 169.8us 169.9us 170.0us 170.1us 170.2us 170.3us 170.4us 170.5us 170.6us 170.7us 170.8us
V(S1:d,S1:s) ID(S1)
Time
Figure 10. Floating Point of Vds,S1
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![ACEEE International Journal on Communication, Vol 1, No. 1, July 2010
TABLE II MOSFETs as well. Other than these, the simulation
POWER LOSSES FOR VARYING TDS results are acceptable. Nevertheless this work has
TD PSW,S1 PSW,S2 Ploss,total successfully verified that 15 ns dead time is the best
(W) (W) (W) value to be used for the lowest switching loss in the
5ns 1.538 1.145 2.920 converter.
15ns 1.000 1.296 2.296
15 ns [1] 1.138 1.100 2.238 V. CONCLUSION
30ns 1.707 1.823 3.7146
In conclusion, switching losses in converter circuit
Ploss,total is the total of all losses consisting conduction are present due to high and low side switches operating
loss, PCOND , body diode loss, PBD , and also switching in high frequency system. The gate driver circuit plays
losses, PSW,S1 and PSW,S2 . From Table VII, it indicates an important part in activating these switches. In order
that TD at 15 ns gives the lowest total power loss, to reduce the losses, the dead time and duty ratio of the
Ploss,total of 2.296 W. Compared to TD=5 ns and TD=30 ns, RGD circuit must be controlled. The PSpice software is
TD=15 ns is the most energy saving setting to be used.
The switching losses, PSW of the circuit are the major used to implement this project. The switching losses
contributors of losses. PSW comes from the two for both S1 and S2 are calculated and compared to the
switches, S1 and S2, in the synchronous buck converter findings from [1]. It has shown a decrease in losses by
circuit. Theoretically, these losses can be reduced by 13.8 % in S1 but
reducing the switching time or peak power of both increase by 15.12 % in S2, respectively. Moreover,
switches since PSW =0.5*switching time*peak power*fs. further analyses and comparison of the circuit
This means that the faster the MOSFETs can turn off,
the more switching power can be reduced. performance are also made and it can be concluded that
TD =15 ns is the best optimum value.
E. Results Verifications
ACKNOWLEDGMENT
Utilizing Mathcad, equations (2), (3) and (4) are
used to obtain the theoretical values. The results are Authors would like to thank Universiti Teknologi
then compared with the values obtained using Pspice. PETRONAS, for providing financial support in
All parameters are calculated and the comparison is presenting this work.
shown in Table VII.
REFERENCES
TABLE III
COMPARISON OF CALCULATION FROM MATHCAD & PSPICE AT [1] N.Z. Yahaya, K.M. Begam & M. Awan “Design &
T =15NS D
Simulation of An Effective Gate Drive Scheme for Soft-
Switched Synchronous Buck Converter” 3rd Asia
Method %Δ International Conference on Modeling & Simulation,
Parameters PSpice Bandung/Bali, Indonesia, pp. 751-756, May 2009.
Formul PSpice PSpice Calc. [2] K. Yao and F.C. Lee “A Novel Resonant Gate Driver for
a [1]
High Frequency Synchronous Buck Converters” IEEE
Rise time,
tr (ns) 25.810 25.557 25.760 0.79 Transactions on Power Electronics, vol. 17, no. 2, pp.
Recovery time, 180-186, Mar. 2002.
trec (ns) 51.620 58.041 56.645 2.46 [3] Z. Yang, S. Ye and Y. Liu “A New Resonant Gate
Peak current, Driver Circuit for Synchronous Buck Converter” IEEE
iLo(tpeak) (A) 3.572 3.367 3.970 15.19 Transactions on Power Electronics, vol. 22, pp 1311-
Total switching 1320, Jul. 2007.
loss, Psw,total (W) 2.296 2.820 2.240 25.89 [4] Y.H. Chen, F.C. Lee, L. Amoroso and H. Wu “A
Conduction Resonant MOSFET Gate Driver with Energy Efficient
loss, 0.100 0.113 0.068 66.18 Recovery” IEEE Transactions on Power Electronics,
PCOND (W)
vol. 19, no. 2, Mar. 2004.
Body diode
loss, 0.149 0.134 0.025 436 [5] J. Qian “High Efficiency High Frequency Resonant Gate
PBD(W) Driver for Power Converter”, Aug. 2002,
The difference between the results obtained from www.freepatentsonline.com/6441652.html
PSpice done in this work and [1] show significant big [6] N.Z. Yahaya, K.M. Begam & M. Awan “The
margin. The work done in [1] shows lower PBD since the Limitations and Implications on Duty Ratio, Dead Time
proposed RGD design in Fig. 1 gives result in low body and Resonant Inductor on DC-RGD Circuit” 2nd
diode conduction time during TD of 15 ns. This National Postgraduate Conference on Engineering,
corresponds to the conduction loss of the switching Science and Technology, Tronoh, Malaysia, Mar 2009,
unpublished.
21
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The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of ZVS Synchronous Buck Converter
- 1. ACEEE International Journal on Communication, Vol 1, No. 2, July 2010 The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of ZVS Synchronous Buck Converter N.Z. Yahaya, M.K. Lee, K.M. Begam & M. Awan Power & Energy Group Electrical Engineering Department Universiti Teknologi PETRONAS Bandar Seri Iskandar, Tronoh, 31750 Perak, MALAYSIA Email: norzaihar_yahaya@petronas.com.my Abstract—This work is about the analysis of dead time used, yet there are limitations in the design. When the variation on switching losses in a Zero Voltage Switching frequency is increased, the gate driving losses will (ZVS) synchronous buck converter (SBC) circuit. In high experience an increase in power dissipation. This in turn frequency converter circuits, switching losses are affects the performance of the converter. The duty ratio commonly linked with high and low side switches of SBC or pulse width, D, dead time, TD, and the resonant circuit. They are activated externally by the gate driver inductor, Lr are the limiting parameters that influence circuit. The duty ratio, dead time and resonant inductor the gate driver operation from conducting optimally. are the parameters that affect the efficiency of the circuit. These parameters had been analyzed in [6] and the These variables can be adjusted for the optimization results show that the optimized values are found to be purposes. The study primarily focuses on varying the D = 20 %, TD = 15 ns and Lr = 9 nH at 1 MHz switching settings of input pulses of the MOSFETs in the resonant frequency. However, the values of switching losses in gate driver circuit which consequently affects the the MOSFET are still very high. Therefore, the TD performance of the ZVS synchronous buck converter parameter is adjusted to optimize switching losses. This circuit. Using the predetermined inductor of 9 nH, the is the primary objective in this work. frequency is maintained at 1 MHz for each cycle transition. The switching loss graph is obtained and switching losses for both S1 and S2 are calculated and II. PROPOSED RGD-SBC CIRCUIT compared to the findings from previous work. It has Vca shown a decrease in losses by 13.8 % in S1. A dead time of 15 ns has been determined to be optimized value in the Vs SBC design. Keywords— PSpice Simulation, Resonant Gate Driver, Synchronous Buck Converter, Switching Losses I. INTRODUCTION In megahertz switching frequency, synchronous buck converter (SBC) circuit may contain losses which are normally caused by the high and low side switches. The resonant gate driver (RGD) circuit is applied due to its suitability in driving MOS-gated power switches in high frequency applications. High power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is used as a switch in this work of the proposed RGD LEFT CIRCUIT RIGHT CIRCUIT circuit [1]. At present, there are various types of RGD Figure 1. Proposed RGD Circuit circuits commercially available [2-4]. The resonant circuit transfers energy from the parasitic input Fig. 1 shows the proposed RGD circuit which is used capacitance of the power switching devices. This energy in this work. The circuit is suitable for SBC circuit transfer prevents dissipation of the capacitive energy in because with a single input voltage, Vin, two output gate the driver circuit which may otherwise destroy one or voltages will be generated complimentarily. Fig. 2 more components. shows two output waveforms generated from an input voltage of the SBC circuit. The resonant circuit includes an inductor in the driver circuit and one or more discrete capacitors are also included within the driver circuit to maintain resonance at a given frequency regardless of parasitic capacitance variation [5]. Although high frequency MOSFET is 16 © 2010 ACEEE DOI: 01.ijcom.01.02.04
- 2. ACEEE International Journal on Communication, Vol 1, No. 1, July 2010 20V of TD are unchanged, any changes in D will eventually Vgs, S1 Vgs, S2 result in different switching losses in the circuit. 10V 0V SEL>> III. METHODOLOGY -10V V(S1:g,S1:s) V(S2:g,S2:s) 50V In this work, the proposed RGD-SBC circuit is simulated using PSpice software. The pulse settings of Input voltage, Vsource four MOSFETs in the proposed RGD circuit are 45V 40V modified carefully resulting in different values of TD. 173.5us 173.6us V(Vp_source:+) 173.8us 174.0us Time 174.2us 174.4us 174.6us 174.8us The RGD circuit accordingly will affect the TD of the Figure 2. Gate Voltage of S1 and S2 & Input Voltage of SBC synchronous buck converter circuit where the switching losses of the circuit are measured at the two MOSFET As it can be seen, the left circuit of the proposed switches of S1 and S2. The results are then measured, RGD circuit is the DC-RGD while the right circuit is compared and analyzed. The conclusion is then drawn. just the symmetrical of the left circuit. The circuit has the advantages with simplicity having symmetrical pattern which gives better choice of component and IV. RESULTS AND DISCUSSION parameter mo© 2010 ACEEEdification. In addition, a bootstrap circuit for high side driver [3] consisting of a A. Proposed RGD Circuit diode, Da and a capacitor, Ca are added into the circuit. The dead time settings on each pulse generator in the The importance of bootstrap circuitry is that it aids in proposed RGD circuit of Fig. 1 are shown in Table I circuit simplification, symmetrical behavior and also minimizes switching loss. Besides that, it has less while the pulse width settings are tabulated in Table II. impact on the parasitic capacitance as well as better Fig. 4 to Fig. 6 indicate the waveforms of dead time, immunity in dv/dt turn-on. The proposed RGD circuit delay time and pulse width. can conduct in two modes, complementary mode and symmetrical mode. In the complementary mode, it TABLE I. provides two drive signals with duty cycle D and 1-D, SETTINGS FOR DEAD TIME IN PROPOSED RGD CIRCUIT respectively. This mode is suitable for driving two Dead time Initial Delay time for each MOSFETs in a synchronous buck converter. delay voltage pulse In the circuit, the four units of MOSFETs (Q1, Q2, TD= TD3 time, td1 td2 td3 td4 Q3, Q4) settings will be reassigned carefully while other TD1= (ns) td, initial (ns) (ns (ns) (ns) values which include oscillation frequency = 1 MHz, D TD2 (ns) ) = 20 % and Lr = 9 nH remain unchanged. Theoretically, (ns) when parameters of MOSFETS, Q1 and Q2 of the RGD 5 23 15 15 22 284 947 circuit are changed, dead time of the left circuit, TD1 will 2 vary. Similarly, when parameter values of Q3 and Q4 are 15 15 15 15 23 284 955 changed, then dead time of the right circuit, TD2 will be 2 also be modified. Consequently, the overall value of TD 30 5 15 15 24 284 969 in the proposed synchronous buck converter circuit as 7 shown in Fig. 3 will also be modified. This gives result in new values of D and (1-D) in the synchronous buck circuit. S1 is the high side switch while S2 is the lower side switch and the switching losses of the circuit will TABLE II be measured from these two switches. Overall, it is SETTINGS FOR PULSE WIDTH IN PROPOSED RGD CIRCUIT expected that the by varying the value of TD, the Dead time Pulse Width performance of the SBC circuit will be affected, accordingly. TD= TD1= Vp1 Vp2 Vp3 Vp4 PWS1 PWS2 TD2 (ns) (ns) (ns) (ns) (ns) (ns) (ns) 5 200 786 654 331 201 769 15 200 765 654 312 211 759 30 200 740 654 286 229 741 The dead times are varied in order to evaluate the performance of the circuit. For different dead times, the initial delay time, td,initial is set to be constant at 15 ns. Figure 3. Proposed Synchronous Buck Converter with ZVS Therefore, the first delay time for voltage pulse one, td1 is equal to td,initial. By taking TD=15 ns as reference, it can When the values of switching frequency equals to 1 be observed that only delay time for voltage pulse 1 and MHz and Lr = 9 nH, together with the optimized value 3, td1 and td3 , and pulse width of voltage pulse of 1 and 17 © 2010 ACEEE DOI: 01.ijcom.01.02.04
- 3. ACEEE International Journal on Communication, Vol 1, No. 1, July 2010 3, PW1 and PW3, are changed in order to obtain the dead the dead time when both switches are not conducting. times of 5 ns and 30 ns. The table also shows that when Fig. 7 shows the operating waveforms generated from TD1=TD2 increases, TD3 decreases instead. the left side of the proposed RGD circuit in Fig. 1. 6.0V Q1 Q2 Q1 Q2 Q1 Q2 5.0 iL1 4.0V 0 V(Q1:g,Q1:s) V(Q2:g,Q2:s) - I(L1) Vp1 Q3 Q4 Q3 5.0 Vp2 2.0V 0 SEL>> iL2 V(Q3:g,Q3:s) V(Q4:g,Q4:s) - I(L2) TD1 TD1 20V Vgs,S2 Vgs,S1 0V 0V -20V 1.9698ms 1.9699ms 1.9700ms 1.9701ms 1.9702ms 1.9703ms 1.9704ms 1.9705ms 1.9706ms 1.9707ms 1.9708ms 1.9709ms 1.9710ms 1.9711ms V(S1:g,S1:s) V(S2:g,S2:s) Time -1.0V -0.1us 0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us 1.1us 1.2us 1.3us 1.4us V(Q1:g,Q1:s) V(Q2:g,Q2:s) Time Figure 7. Operating Waveforms of Proposed RGD Circuit Figure 4. Indication of Pulse Width, Dead Time and Delay Time of Q1 and Q2 MOSFETs for TD=15 ns Pulses from Vp1 and Vp2 are fed into the MOSFETS, td2 Q1 and Q2 on the left side of RGD circuit. From the The graph of Fig. 4 is generated from the simulation td, initial = td1 waveform, Q1 and Q2 are complementary driving pair of Vgs,Q1 and Vgs,Q2. Both Q1 and Q2 MOSFETs conduct inherited from the conventional driver. First, when Q1 is complementarily to each other. The time when both switched on, the inductor current of the left circuit, iL1 MOSFETs are not conducting is known as the dead starts to conduct and it is charged to maximum. The time, TD1. Vp1 is the pulse width of Q1 and similarly to characteristic impedance of the resonant circuit can be Vp2, the pulse width of Q2. td, initial which is equal to td1 is represented by (1) the initial delay time, set at a constant value of 15 ns. td2 on the other hand is the delay time before Q2 starts to Zo = LR conduct. C in (1) 6.0V Q3 Q4 Q3 where LR is the resonant inductor equivalent to 9 nH. The rise time tr can be estimated by (2) π 4.0V Vp3 Vp4 tr = LRCin (2) 2 The duration of this charging current depends on the 2.0V TD2 TD2 value of LR for being the time constant of the circuit. If 0V td3 the duration of the discharging current is not sufficient, td4 it will cause current oscillation when Q1 is turned off [1]. On the other hand, D1 and D2 are designed to clamp -1.0V -0.1us 0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us 1.1us 1.2us 1.3us 1.4us V(Q3:g,Q3:s) V(Q4:g,Q4:s) Vgs and to provide low impedance path for the inductor Time Figure 5. Indication of Pulse Width, Dead Time and Delay Time of current and recover the driving energy which is Q3 and Q4 MOSFETs for TD=15 ns represented by (3) Fig. 5 shows the pulse width for Q3, Vp3 and Q4, Vp4. td3 is the delay time before the MOSFET Q3 starts trec = π LRCin (3) to conduct. Similarly, td4 is the delay time before Q4 turns on. On the other hand, TD2 is the dead time when where Cin is the input gate capacitance of high side both MOSFETs, Q3 and Q4 are off. switch, S1. On the other hand, the peak time is defined 15V by (4) 4 LR S2 2 LR × − RG 2 −1 C in tan R 10V S1 S1 PWS2 t rec = (4) PWS1 TD3 TD3 4 LR 2× − RG 2 5V C in 0V After iL1 has been fully charged to peak current and at 2.9698ms 2.9699ms 2.9700ms 2.9701ms 2.9702ms 2.9703ms 2.9704ms 2.9705ms 2.9706ms 2.9707ms 2.9708ms 2.9709ms 2.9710ms 2.9711ms the same moment Vgs,S1 is clamped at Vca by diode D1, iL1 flows according to the path Q1-L1-Vgs,S1. The inductor V(S1:g,S1:s) V(S2:g,S2:s) Time Figure 6. Indication of Pulse Width and Delay Time for S1 and S2 for current can be represented by equation (5). TD=15 ns 4 LR R −RG 2 The gate source voltage of both switches, Vgs,S1 and i L1 (t peak ) = 2Vca − G •t •e 2 LR •sin Cin 2 LR •t (5) 4 LR Vgs,S2 is shown in Fig. 6. The maximum of Vgs,S1 is at 10 Cin −RG 2 V and PWS1 is the pulse width of S1. Vgs,S2 goes to a maximum value of 12 V with pulse width PWS2. TD3 is 18 © 2010 ACEEE DOI: 01.ijcom.01.02.04
- 4. ACEEE International Journal on Communication, Vol 1, No. 1, July 2010 iL1 then starts to discharge back to zero through Q2,body From the results, the duty ratio of S2 at 75 % gives ,-L1-D1 and back to Vca, the direct voltage source at diode the lowest switching losses compared to other values. 12 V. After a predetermined TD of either 5 ns, 10 ns or Therefore, it can be concluded that in order to reduce 15 ns, Q2 will turn on instead. At this time Q1 is turned the conduction losses in the circuit, the conduction time off. Then iL1 starts to charge again but to a negative of S2 has to be optimized at 75 % for low switching loss. maximum value. This value will be a little lower compared to the positive value of iL1 because of leakage These two switches conduct complementary to each current. iL1 shows a symmetrical behavior compared to other. Since both of them do not turn on at the same when Q1 is conducting. When iL1 increases back to zero, time, cross conduction will not occur. During TD, when it goes through D2-L1,-Q1,body diode and to Vca. The S1 is turned off, the discharged inductor current at the symmetrical behavior in charging and discharging load will flow into body diode S2, which is also at its off inductor current gives the total RG power loss to be (6). condition. ZVS can be achieved if S2 is completely turned off before S1 is turned on. During the ( ) t2 RG Discontinuous Current Mode (DCM) operation, the Ploss _ RG = 2 × ∫ i L1 • RG • dt ≈ 2 × Q DD × Vca × f s (6) t1 ( RG + Z O ) negative load inductor current can be applied where the body diode of S1 is turned on first before the main body The t1 represents the rise time of the inductor current of the switch itself. Therefore, the switching losses at S1 while t2 is the recovery time of the inductor current. The can be reduced since it has experienced ZVS. The same operation applies for the right hand side of the operating waveforms of the proposed SBC circuit in proposed RGD circuit in Fig. 1 with TD2 = 5 ns, 15 ns or simulation are shown in Fig. 8. 30 ns. The circuit can also be explained in terms of 10A id, S1 energy processing. When Q1 is turned on, energy is 0A transferred from the power source, Vca to the resonant -10A inductor and the gate capacitor. When Vgs of Q1 reaches 10A ID(S1) its peak, freewheeling of energy at inductor occurs. 0A Then, the energy is returned to Vca. Therefore, the -10A id, S2 proposed RGD demonstrates less power consumption 50V ID(S2) Vgs, S1 compared to the conventional gate driver because of the 0V Vds, S1 energy recovery process. -50V V(S1:d,S1:s) V(S1:g,S1:s) The circuit also has the similar circuit operation for 50V 25V Vgs, S2 Vds, S2 the discharging transition. When Q2 is turned on, 0V SEL>> -50V resonance takes place and the capacitive energy is 169.6us 169.7us 169.8us V(S2:d,S2:s) V(S2:g,S2:s) 169.9us 170.0us 170.1us 170.2us 170.3us 170.4us 170.5us 170.6us 170.7us 170.8us transferred to the inductor. When iL1 starts to increase to Time the negative peak value, energy is merely freewheeling Figure 8. Operating Waveforms of SBC Circuit and finally, when the inductor current returns to zero, From the waveforms, the operation of SBC circuit the inductor energy is also returned to the power source, starts when S1 starts to conduct while ids,S2 at its peak Vca. The right circuit operates in similar fashion to the value starts to decrease to zero and turn off. At this left circuit but during different interval. time, it can be seen that Vds, S2 starts to increase to its maximum value which is the Vin value of 48 V while B. Proposed SBC Circuit Vds, S1 works in complimentary pattern and reduces to Referring to Fig. 3, S1 is the high side switch and it zero. The scenario of Vds, S2 going to its peak value while has the primary function of a buck converter, used to Vds, S1 goes to zero should occur at the same time, in convert high input voltage into low output voltage at the other words, there is no time interval. This is because of freewheeling phase of ids, S1. It causes Vgs, S1 to go to zero load. On the other hand, S2 is the low side switch and it first before Vds, S1 reaches its maximum value. For the has a longer conduction time compared to S1. The drain current of S1, it can be observed that ids, S1 starts to purpose is to lower the conduction loss in S2. This can increase exponentially to its highest value. At this be verified by Table III. moment, the conduction of ids, S1 circulates through Ls and Cs in the SBC circuit. TABLE III SWITCHING LOSS FOR VARYING DUTY RATIO OF S2 AT S1 stops conducting when it reaches its highest point. T =15NS But at this moment, S2 does not conduct yet. This indicates a dead time exists when there is a change in D Vgs, Vgs, S1 S2 S1 Turn- S2 conduction of switches. At this time, Vds, S1 starts to S1 S2 Turn- Turn- off Turn-on increase while Vds, S2 starts to decrease. On the other duty duty off on Peak Switchi Switchin hand, ids, S2 starts to decrease to its maximum negative ratio ratio Peak (W) ng g Losses value whereas ids, S1 is at zero. Following that, it can be ,D ,D (W) Losses (W) seen from the figure ids, S2 starts to increase back to zero, (W) which is like the previous state before it increases to its 20% 20% 91.617 109.72 1.603 2.195 highest value while S1 is off. At this moment, it can be 6 observed that ids, S1 is at zero and Vds, S1 is at its peak of 20% 55% 87.060 98. 760 1.524 1.975 the value Vin. This process repeats in the next 20% 70% 66.132 79.336 1.389 1.483 subsequent cycles. 20% 75% 57.118 64.790 1.000 1.296 19 © 2010 ACEEE DOI: 01.ijcom.01.02.04
- 5. ACEEE International Journal on Communication, Vol 1, No. 1, July 2010 C. Switching Losses of SBC at TD = 15 ns It can also be observed that the positive peak is The power losses of the circuit are interpreted by higher than the negative. This shows that the power generating the turn-off switching loss waveform of S1 losses are not equally distributed in S1. In the circuit, S1 and turn-on switching loss of S2 as shown in Fig. 9. is dominant in generating the power loss of the SBC 100W 70.096 W 95.242 W circuit. Thus, Ls and Cs has been added to the circuit in S2 turn-on S1 turn-off parallel with S1 to solve this problem. Meanwhile, Cx transition transition has also been added in order to prevent the floating 50W 40 ns 35 ns 0W drain voltage of S1. Hence, theoretically, Ls, Cs and Cx Psw,S1 is positive have to be varied to reduce the switching losses at S1. -50W However, S2 turn-on switching losses have increased by 15.12 % compared to the study in [1]. Fig. 11 shows the operating waveforms for S2. -100W 173.5us 173.6us 173.8us 174.0us 174.2us 174.4us 174.6us 174.8us V(S1:d,S1:s) * ID(S1) V(S2:d,S2:s) * ID(S2) Time Figure 9. Turn-Off Switching Loss of S1 and Turn-On Switching Loss of S2 From the waveforms, the switching time for S1 turn- off transition is 35 ns and for S2, 40 ns. The calculation of switching losses is tabulated in Table IV and the evaluated results are compared with [1]. TABLE III COMPARISON OF DATA [1] WITH THIS WORK AT T =15NS D From [1] From % this work discrepanc y S1 Turn-off Peak 65.000 57.118 - 13.80 % Vds * Ids W W S1 Turn-off 1.138 W 1.000 W - 13.80 % Switching Losses Figure 11. Operating Waveforms of S2 S2 Turn-on Peak 95.000 64.790 - 46.63 % Vds * Ids W W Compared to S1, there is no floating point at Vds, S2. S2 Turn-on 1.100 W 1.296 W + 15.12 % As expected there is reduction in the turn-on switching Switching Losses losses and in return, the performance and reliability of From the results, it can be observed that the turn-off the SBC circuit have improved. switching losses of S1 have decreased. Otherwise, the problem of floating Vds,S1 can cause the switching power D. Comparison of Circuit Performance for Several loss to float as well. Conventionally, as most described TDs in literature, the switching losses will be high and unfortunately they are ignored. The aim is to generate With other parameter values remain unchanged the drain voltage of less than 0.7 V during its turn-off or except for TD, the overall performance of the circuit is near to zero value during the entire turn-off transition analyzed. The circuit performance at TD =5 ns, 15 ns, time. Similarly to Vds,S2, having a zero drain voltage can and 30 ns is shown in Table V and Table VI. result in zero switching loss since their drain currents conduct at this time. This situation can be seen in the TABLE I Fig. 10. PARAMETER EVALUATION FOR VARYING T S D 100W TD Vout Iout tbd PCOND PBD (V) (A) (ns) (W) (W) 0W Floating switching 5ns 14.06 1.41 30 0.102 0.135 power loss for entire Vds 1 -100W turn-off time 15ns 13.91 1.391 33 0.100 0.149 V(S1:d,S1:s) * ID(S1) 50 15 ns 10.12 1.520 24 0.068 0.026 25 [1] 8 0 Floating 0 < Vds < 0.7 V 30ns 14.15 1.41 18 0.103 0.082 -25 5 SEL>> -50 169.6us 169.7us 169.8us 169.9us 170.0us 170.1us 170.2us 170.3us 170.4us 170.5us 170.6us 170.7us 170.8us V(S1:d,S1:s) ID(S1) Time Figure 10. Floating Point of Vds,S1 20 © 2010 ACEEE DOI: 01.ijcom.01.02.04
- 6. ACEEE International Journal on Communication, Vol 1, No. 1, July 2010 TABLE II MOSFETs as well. Other than these, the simulation POWER LOSSES FOR VARYING TDS results are acceptable. Nevertheless this work has TD PSW,S1 PSW,S2 Ploss,total successfully verified that 15 ns dead time is the best (W) (W) (W) value to be used for the lowest switching loss in the 5ns 1.538 1.145 2.920 converter. 15ns 1.000 1.296 2.296 15 ns [1] 1.138 1.100 2.238 V. CONCLUSION 30ns 1.707 1.823 3.7146 In conclusion, switching losses in converter circuit Ploss,total is the total of all losses consisting conduction are present due to high and low side switches operating loss, PCOND , body diode loss, PBD , and also switching in high frequency system. The gate driver circuit plays losses, PSW,S1 and PSW,S2 . From Table VII, it indicates an important part in activating these switches. In order that TD at 15 ns gives the lowest total power loss, to reduce the losses, the dead time and duty ratio of the Ploss,total of 2.296 W. Compared to TD=5 ns and TD=30 ns, RGD circuit must be controlled. The PSpice software is TD=15 ns is the most energy saving setting to be used. The switching losses, PSW of the circuit are the major used to implement this project. The switching losses contributors of losses. PSW comes from the two for both S1 and S2 are calculated and compared to the switches, S1 and S2, in the synchronous buck converter findings from [1]. It has shown a decrease in losses by circuit. Theoretically, these losses can be reduced by 13.8 % in S1 but reducing the switching time or peak power of both increase by 15.12 % in S2, respectively. Moreover, switches since PSW =0.5*switching time*peak power*fs. further analyses and comparison of the circuit This means that the faster the MOSFETs can turn off, the more switching power can be reduced. performance are also made and it can be concluded that TD =15 ns is the best optimum value. E. Results Verifications ACKNOWLEDGMENT Utilizing Mathcad, equations (2), (3) and (4) are used to obtain the theoretical values. The results are Authors would like to thank Universiti Teknologi then compared with the values obtained using Pspice. PETRONAS, for providing financial support in All parameters are calculated and the comparison is presenting this work. shown in Table VII. REFERENCES TABLE III COMPARISON OF CALCULATION FROM MATHCAD & PSPICE AT [1] N.Z. Yahaya, K.M. Begam & M. Awan “Design & T =15NS D Simulation of An Effective Gate Drive Scheme for Soft- Switched Synchronous Buck Converter” 3rd Asia Method %Δ International Conference on Modeling & Simulation, Parameters PSpice Bandung/Bali, Indonesia, pp. 751-756, May 2009. Formul PSpice PSpice Calc. [2] K. Yao and F.C. Lee “A Novel Resonant Gate Driver for a [1] High Frequency Synchronous Buck Converters” IEEE Rise time, tr (ns) 25.810 25.557 25.760 0.79 Transactions on Power Electronics, vol. 17, no. 2, pp. Recovery time, 180-186, Mar. 2002. trec (ns) 51.620 58.041 56.645 2.46 [3] Z. Yang, S. Ye and Y. Liu “A New Resonant Gate Peak current, Driver Circuit for Synchronous Buck Converter” IEEE iLo(tpeak) (A) 3.572 3.367 3.970 15.19 Transactions on Power Electronics, vol. 22, pp 1311- Total switching 1320, Jul. 2007. loss, Psw,total (W) 2.296 2.820 2.240 25.89 [4] Y.H. Chen, F.C. Lee, L. Amoroso and H. Wu “A Conduction Resonant MOSFET Gate Driver with Energy Efficient loss, 0.100 0.113 0.068 66.18 Recovery” IEEE Transactions on Power Electronics, PCOND (W) vol. 19, no. 2, Mar. 2004. Body diode loss, 0.149 0.134 0.025 436 [5] J. Qian “High Efficiency High Frequency Resonant Gate PBD(W) Driver for Power Converter”, Aug. 2002, The difference between the results obtained from www.freepatentsonline.com/6441652.html PSpice done in this work and [1] show significant big [6] N.Z. Yahaya, K.M. Begam & M. Awan “The margin. The work done in [1] shows lower PBD since the Limitations and Implications on Duty Ratio, Dead Time proposed RGD design in Fig. 1 gives result in low body and Resonant Inductor on DC-RGD Circuit” 2nd diode conduction time during TD of 15 ns. This National Postgraduate Conference on Engineering, corresponds to the conduction loss of the switching Science and Technology, Tronoh, Malaysia, Mar 2009, unpublished. 21 © 2010 ACEEE DOI: 01.ijcom.01.02.04