the-cpu-design-central-processing-unit-design-1

Topic 3
The Central Processing Unit Design
3-1 The Functional Requirements
3-1-1 An Overview of the CPU Functions
As everybody knows, the basic computer system includes a central processing unit
(CPU), a memory system, and an input/output system. The memory includes a read only
memory (ROM) and a random access memory (RAM). The startup programs reside in the
ROM, whereas other executable programs and their relevant data reside in the RAM.
After the completion of the startup process and loading the operating system to the RAM
the CPU executes the programs from the RAM. The program, as defined, is a limited
sequence of instructions which performs a certain task or a group of tasks. So, executing
the program means executing its instructions.
To execute the instruction, the CPU needs to fetch it from the RAM, i.e. reads it from the
RAM. We call this the (instruction Fetch) operation. If the instruction needs to operate on
data residing in the RAM (Memory Operands), the CPU has to fetch (read) it from the
RAM. We call this the (instruction Fetch) operation. The instruction may instruct the
CPU to store the result, or other datum in the RAM. In this case the CPU has to writ data
to the RAM. Apart from fetching and storing data, and in order to execute the instruction,
the CPU must include functional units to understand (decode) and execute the fetched
instruction. So, The CPU must include an Instruction Decoder (ID) and an execution unit,
basically to execute the arithmetic and logic operations; an Arithmetic Logic Unit (ALU).
To keep the instruction for the instruction decoder, the instruction must be latched to an
instruction register (IR). The fetched data or the produced results may need to stay in the
processor pending other instructions to operate on them. So they need a temporary
storage. This means the processor must include a register file to store the data
temporarily, whether for operations or for address generation. So, we can conclude by
saying that the following functional units must be included in the CPU design (Refer to
Figure 3-1 to see the block diagram of the CPU):
1- The Instruction Fetch (IF) Unit: This unit basically provides an access and read
facility to the memory location/s that include/s the instruction. This includes
providing at least, the address of the memory location that includes the instruction
and a read control signal. The address is provided by a unit called the Address
Generator (AG), whereas the read signal is provided by the external control unit
which that is associated with the instruction decoder.
2- The Operand Fetch Unit: The function of this unit is to access the data (the
operands) in the memory. The access includes reading or writing data. The
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address generator and the external control unit cooperate to provide the access by
providing the memory address of the data plus a read or write signal.
Figure 3-1: A block diagram of the CPU
3- The Register File: this includes a set of registers that keeps the data for
operations and address generation.
4- The Instruction Register: This unit keeps the fetched instruction for the
instruction decoder to decode it.
5- The Instruction decoder: this is the main control unit of the CPU. It decodes the
operation code field of the instruction (OPCOF field of the IR) and issues the
control signals necessary to fetch or access the operand/s and to complete the
instruction execution.
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6- The Arithmetic Logic Unit (ALU): Under the control of the instruction decoder,
this unit performs the arithmetic and logic operations on the fetched operand/s.
Attached with this unit is the Flag (Status) register which includes flip/flop flags.
Part of these flags is programmable whereas the flags of the other part indicate the
status of ALU operation result.
In all our demonstrations and discussions, we adopt our abstracted version of the
processor Intel 8086. Figure 3-1 depicts our abstracted block diagram of this
processor.
3-1-2 Designing the Register File
The register file is designed to meet the functions required for this processor. Four
16-bit data register are allocated for temporary storage of the data (operands). These
are AX, BX, CX, and DX. The register AX is called the accumulator and it is
positioned at one of the two ALU inputs. In most cases, the ALU stores the result of
its operations in it. The Processors that use the accumulator to store the result are
called accumulator-based processors. As the status of the result must be indicated for
other instructions (especially the branch instructions), a register that includes
flip/flops that are individually affected by the result must be positioned next to the
ALU in order to receive and be affected by the result. This register must also include
flip/flops to be set or reset in order to control some functions, like the interrupt flag
and the direction flag. This register is called the Flag Register or the Status
Register. Figure 3-2 depicts the abstracted register architecture of the Intel 8086
processor.
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Figure 3-2: The abstracted register file of the Intel 8086 processor.
The Segment and Pointer Registers
The designers of Intel 8086 microprocessor decided to make its memory addressing
capability cover one megabyte of memory. The address bus was made a 20-bit one. They
decide to divide the physical memory range into segments. Each segment includes 64
kilobytes of memory. So, a 16-bit pointer would be enough to point to each location of
the segment. The segment start (Base) address is pointed to by the contents of a segment
register shifted to the left by one hex digit (4 bits). Shifting the contents of the segment
register this way, extends the contents to 20 bits. This makes it point anywhere we like
within one mega, i.e., within the physical range of the memory. In spite of the fact that
one mega makes sixteen 64 kilobyte segments, the processor can operate one segment at
a time.
Regarding the types of segments, it was decided to make four types of segments; the code
segment, the data segment, the extra segment, and the stack segment. The code segment,
as its name suggests, includes the program code, and its base address is pointed to by the
contents of the Code Segment (CS) register. The data segment includes the data
necessary for the program, and its base address is pointed to by the contents of the Data
Segment (DS) register. The Extra segment includes the destination data, and its base
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address is pointed to by the contents of the Extra Segment (ES) register. The Stack
segment includes the stack data of the memory, and its base address is pointed to by the
contents of the Stack Segment (SS) register.
To point to memory location within the segment, we use the contents of the pointer
registers. The contents of the Instruction Pointer (IP) register points to the memory
location that contains the next instruction of the program code. The contents of the
Source Index (SI) register points to the memory location that contains the required data in
the data segment. The contents of the Destination Index (DI) register points to the
memory location that contains the required data in the extra segment. The contents of the
Stack Pointer (SP) register points to the memory location that contains the required data
in the stack segment, where the data access is sequential. The contents of the Stack
Pointer (SP) register points to the memory location that contains the required data in the
stack segment, where the data access is sequential. The contents of the Base Pointer (BP)
register points to the memory location that contains the required data in the stack
segment, where the data access is random.
3-1-3 The Addressing Modes
A very important issue of the processor operations is the way in which it produces the
address to access data in the memory. The ways in which the processor accesses the data
in the memory are called the addressing modes of the processor. The Intel 8086
designers decided make six addressing modes for accessing the memory in addition to
one mode of accessing the data in a processor internal register. A set of data transfer
instruction forms was designed. The operation code of this instruction is MOV. However,
before going to these modes, we first show how the instruction is fetched. The instruction
address is made by adding the contents of the instruction pointer register to the contents
of the code segment register shifted to the left by one hex digit as follows:
The instruction is fetched by applying the physical address through the address bus to the
memory with a read (RD) signal, where the memory responds by outputting and placing
the instruction on the data bus, so that the processor can latch it into the instruction
register. This can be represented by the following sequence of micro-operations:
The Addressing Modes
1- The register-Register Addressing Mode
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In this mode, the source and the destination of the instruction are registers within
the processor. The instruction has the form
MOV D, S; D and S are registers
Example: MOV AX, BX
This instruction moves (copies) the contents of the register BX to AX. In terms of
micro-operation, this is represented by
2- The Immediate Addressing Mode
In this mode, the source data is included within the instruction for, in other words,
it is fetched with the instruction, e.g., MOV AX, 0055h. In this case the data is
part of the fetched instruction, and it is immediately loaded to the register AX. In
terms of micro-operations, this instruction is represented by:
3- The Direct Addressing Mode
In this mode, the value of the pointer that points to the data within the data
segment is included in the instruction. The pointer value is added to the value of
the DS register shifted to the left by one hex digit. Example of this mode are the
instructions MOV AX, [0200h]; and MOV [0200h], AX
In terms of micro-operations, this mode is applied for the first instruction as
follows:
Where the physical address P.A is composed as follows:
In the case of the second instruction (memory location is a destination), the
sequence of the micro operations become:
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4- The register Indirect Addressing Mode
In this mode, the value of the pointer that points to the data within the data
segment is included in a register. The contents of the register are added to the
value of the DS register shifted to the left by one hex digit. Example of this mode
are the instructions MOV AX, [SI]; and MOV [SI], AX
In terms of micro-operations, the data transfer in this mode is applied for the first and
the second instructions as in mode 3 with the physical address composed as follows:
5- The Indexed Addressing Mode
In this mode, the segment is divided into sub-segments, which are pointed to by
the contents of SI. The offset included in the instruction points to the location
inside the sub-segment of the data segment. The contents of the SI register and the
offset are added to the value of the DS register shifted to the left by one hex digit.
Example of this mode is the instruction
MOV AX, [SI] +0150h;
In terms of micro-operations the data transfer of this instruction is applied like the
previous modes, but the physical address is composed as follows:
6- The Based Addressing Mode
the contents of BX. The offset included in the instruction points to the location
inside the sub-segment of the data segment. The contents of the BX register and
the offset are added to the value of the DS register shifted to the left by one hex
digit. Example of this mode is the instruction
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MOV AX, [BX] +0100h;
In terms of micro-operations, the data transfer of this instruction is applied like
the previous modes, but the physical address is composed as follows:
7- The Based indexed Addressing mode
the contents of BX, and these sub-segments are further divided into sub-segments
pointed to by the contents of SI. The offset included in the instruction points to
the location inside the smallest sub-segment of the data segment. The contents of
the BX register and the offset are added to the value of the DS register shifted to
the left by one hex digit. Example of this mode is the instruction
MOV AX, [BX][SI]+0120h;
In terms of micro-operations, the data transfer of this instruction is applied like
the previous modes, but the physical address is composed as follows:
In the following section, we are going to design the address generator which generates
the addresses, both for fetching the instruction, and the data in all addressing modes. It
will be shown how to implement the above specified functions of the addressing modes
in hardware using the IR, the BX, the segment, and pointer registers.
3-1-4 Designing the Instruction Format
Generally, the instruction format includes one to three fields; the operation code field, the
source operand field, and the destination operand field. The designers of Intel 8086
processor decided to include part of the information related to the operands in the
operation code field in addition to the operation code. Only the explicit number part of
the operand or the pointer to the operand is placed in a separate field. Figure 3-3 shows a
format which serves the previously discussed addressing modes and some arithmetic and
logic operations. The op-code field specifies the source and destination as far as it does
not include a number. If the source or destination operand includes a number, like in
based, direct, immediate and indexed addressing modes, a 16-bit additional field is
needed to accommodate this number. The additional field is also needed to accommodate
the branching address in the branch instructions. In figure 3-3, the specified instructions
are coded as follows:
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1- To determine a particular instruction op-code, you need only select the
appropriate bits for the iii, rr, and mmm fields. The rr field contains the
destination register (except for the MOV instruction whose iii field is 111) and the
mmm field encodes the source operand. For example, to encode the "MOV BX,
AX);" instruction you would select iii=110 ("mov (reg, reg) ;), rr=00 (AX), and
mmm=001 (BX). This produces the one-byte instruction 11000001 binary or C0H.
Figure 3-3: Example of Intel 8086 instruction coding
2- Some Y86 instructions require more than one byte. For example, the instruction
"mov( [1000], ax );" loads the AX register from memory location 1000 hex. The
encoding for the op-code is 11000110 binary or C6 hex. However, the encoding for
the "mov( [2000], ax );" instruction op-code is also C6 hex. Clearly these two
instructions do different things, one loads the AX register from memory location
1000 hex while the other loads the AX register from memory location 2000 hex. To
encode an address for the [xxxx] or [xxxx+bx] addressing modes, or to encode the
constant for the immediate addressing mode, you must follow the op-code with the
16-bit address or constant, with the low byte immediately following the op-code in
memory and the high byte after that. So the three byte encoding for "mov( [1000],
ax );" would be C6, 00, 10 hex, and the three byte encoding for "mov( [2000], ax );"
would be C6, 00, 20 hex.
Exercise: write the instruction code for all the addressing modes that were discussed in
section 3-1-3
In the following section, we are going to design the processor parts to meet the specified
functional requirements that were discussed in section 3-1.
3-2 Designing the Functional Units
In this section we are going to design the functional units which implement the functions
that were specified in section 3-1. These functional units are: the register file, the mode
address generator, the instruction decoder, and the arithmetic logic unit.
3-2-1 Designing the Register File
Apart from the status register, the registers of the Intel 8086, as abstracted, are divided
into three types; the segment registers, the pointer registers, and the data registers. The
inputs and the outputs of all these registers must be connected to the internal data register
in order to be loaded with values and to read the loaded values back. The control signal
which enables writing the data to these registers and reading from them come from the
instruction decoder (The processor control unit). Alternatively, the register file can be
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provided with decoders where the inputs of these decoders come from the instruction
decoder. In all cases, a proper bus separation mechanism must be provided so that only
one source and one destination exist on the bus, otherwise the data will be corrupted.
Figure 3-4 shows all the registers of the register file.
Figure 3-4: The register file design
3-2-2 The Address Generator
In this section, we are going to present the design of an address generator which can
generate the address for fetching the next instruction in addition to seven addressing
modes used in fetching the data necessary to complete the instruction execution. As
explained in section 3-1-3, in the process of forming the address, the segment
registers are shifted one hex digit (four bits) to the left to form the base (start) address
of the segment before adding the contents of the offset components (pointer registers,
base register, and direct addresses coming from the IROF) in order to make the
physical address of the required data. Note that in figure 3-5, we connect the contents
of pointer bus to the first 16 bits of X input of the 20-bit adder and ground the last
four bits. At the same time we ground the first 4 bits of input Y of the 20-bit adder
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and connect the contents of the segment bus to the last 16-bits. This makes the
contents of the segment register shifted one hex digit to the left before being added to
the offset. The same thing is applied to port Y of the second 20-bit adder.
Note that in figure 3-5, we use four separate buses to separate the four possible
components of the address, i.e. the segment register, the pointer registers, the base
register BX, and the IROF contents.
Each input of the first level adders is provided with two transceivers; one of them
connects one of the four buses to the relevant adder input in case it is needed, and the
second connects zero to the port inputs in the case that the bus contents are not
required.
The pointer registers are provided with circuits in order to update their contents if it is
required by the instruction or the fetch process to do so. Examples are:
- The IP circuit adds the length of the current instruction to the current value in
order to point to the next instruction in the next instruction fetch cycle.
- The SI and DI registers are incremented or decremented by one or two after some
string instructions
Note also that the internal data bus IDB is connected to the inputs of all segment and
pointer register so that the processor can load them with suitable values.
All control signals that control the registers and the transceivers come from the
instruction decoder of the processor.
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Figure 3-5: The address Generator
3-2-3 The Design of the Instruction Decoder
The instruction decoder presented in this section is a micro-programmed one.
The control bits are stored as data bits in the micro-programmed memory of the
decoder. The control signals of each instruction are stored in this memory starting
from a unique physical address. In order to produce these signals, synchronized to
clock, the following steps are performed by the instruction decoder:
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Part A: The Instruction Fetch
At the beginning, when we reset the CPU, the instruction register the counter cleared,
and zero op-code is presented to the look-up table. The look-up table produces the
base address which is added to zero output of the counter to make the physical
address of the instruction fetch signals in the memory. With each rising edge of the
clock, the counter is incremented and a new set of signals are produced until the first
two bytes of the instruction are fetched (this includes the op-code). When the op-code
is loaded to the IR, the counter is cleared and a new op-code value is presented to the
look-up table.
Part B: Completing the Instruction Execution
As the op-code of the fetched instruction is applied to the look-up table, the base
address of the current instruction control signal is added to the zero output of the
counter to make the first physical address which points to the first group of the
instruction control signals. With each rising edge of the clock, the counter is
incremented and a new set of signals are produced until the operand is fetched (in
case it is required) and the instruction execution is completed.
Note: The CAM
The look-up table is implemented using a CAM (Content Addressable Memory). In
the CAM, each memory location includes two fields; the data field and the tag field.
Tags like op-code are stored in the tag field, and the associated addresses are stored in
the data field as data. Each location is provided with a comparator to compare the
applied tag with the stored tag. If a match occurs, the location outputs the associated
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data to the data bus. In our case, we apply the op-code and obtain the associated the
base address.
3-2-4 The ALU Design
For the design of the ALU and an alternative design of the 4-bit shifter, refer to pages
2-5 of the ALU design pdf file of the e-class topics.
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