tutorial about dic_lec_04_layout1_v01.pdf

Lecture 04
CMOS Layout (1)
Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
Dr. Hesham A. Omran
Digital IC Design
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6 January 2022 3
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1443
This lecture is mainly based on “CMOS VLSI Design”, 4th edition, by N. Weste and D. Harris and
its accompanying lecture notes

CMOS Inverter
❑ Ideally, there is no static (idle) power consumption
04: CMOS Layout (1) 2

Layout vs Cross-Section
n+
p substrate
p+
n well
A
Y
GND VDD
n+
p+
substrate tap
well
tap
n+ p+
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor

Detailed Mask Views
❑ Six masks
1. N-well
2. Polysilicon
3. n+ diffusion
4. p+ diffusion
5. Contact
6. Metal
❑ The transistor is formed by the
intersection of polysilicon and
diffusion
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well

Layout Design Rules (DRs)
❑ The contract between the designer and the process engineer
❑ Same layer: min width and min spacing
❑ Different layers: min spacing, min enclosure (overlap), and min extension
❑ What happens to transistor if min extension of poly is not observed?
[H. Kaeslin, 2008]

Layout DRs cont'd
❑ Real-life layout DRs are very complicated
▪ Checked by a software CAD tool
▪ DRC: Design rule check
▪ Mentor Calibre is the industry standard DRC tool
▪ Checks the layout using a “rule file” (a.k.a. rule deck) and generates a list of DRC errors

Layout DRs cont’d
❑ Generally, the foundry will not accept any design with DRC errors
▪ All errors must be fixed
▪ Sometimes the errors are not real and can be ignored (you must check with the
foundry)
▪ In special cases, minor DRC errors can be accepted by the foundry (but you must
request an official DRC error waiver)

λ-Based Layout DRs
❑ Simplified scalable conservative rules to get you started
❑ Feature size f = 2l =distance between source and drain
▪ Set by minimum width of polysilicon
❑ Feature size improves 30% every 3 years or so
❑ Normalize layout design rules in terms of l = f/2
▪ E.g. l = 0.3 mm in 0.6 mm process

λ-Based Layout DRs cont'd
❑ Simplified scalable conservative rules to get you started
❑ Real-life DRs are in microns and are much more complex

Inverter Layout
❑ Transistor dimensions specified as Width / Length
▪ Minimum size is 4l / 2l, sometimes called 1 unit
▪ In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long

Systematic Layout
❑ Layout can be very time consuming
▪ Design gates to fit together nicely
▪ Build a library of standard cells
❑ Line of diffusion style
▪ Simple and straightforward layout style for standard cells
▪ Four horizontal strips:
1. metal ground at the bottom
2. n-diffusion
3. p-diffusion
4. metal power at the top
▪ Polysilicon lines run vertically to form transistor gates
▪ Metal wires connect the transistors appropriately

A
VDD
GND
B C
Y
metal1
poly
ndiff
pdiff
contact
NAND3
Stick Diagrams
❑ Stick diagrams help plan layout quickly
▪ Need not be to scale
▪ Draw with color pencils or dry-erase markers
❑ Transistor = intersection of poly and diffusion
❑ Note source and drain sharing
c
A
VDD
GND
Y
INV

Stick Diagrams cont'd
❑ Metal1 GND rail at bottom
❑ Horizontal N-diffusion and p-diffusion strips
❑ Metal1 VDD rail at top
❑ Vertical polysilicon gates
❑ Metal1 makes connections
A
VDD
GND
B C
Y
metal1
poly
ndiff
pdiff
contact
NAND3
c
A
VDD
GND
Y
INV

Area Estimation (Using λ-Based DRs)
❑ A wiring track (WT) is the space required for a wire
▪ 4 l width, 4 l spacing from neighbor = 8 l pitch
❑ Transistors also consume one WT (if W is min)
❑ Wells must surround transistors by 6 l
▪ Implies 12 l between opposite transistor flavors
▪ Leaves room for one WT → total equivalent to 3 WT (if W is min)

Area Estimation cont'd
❑ Estimate area by counting wiring tracks (WT)
▪ Multiply by 8 to express in l
❑ For the inverter: 2 WT by 5 WT → 16 l by 40 l
❑ For the NAND3: 4 WT by 5 WT → 32 l by 40 l
A
VDD
GND
B C
Y
metal1
poly
ndiff
pdiff
contact
NAND3
c
A
VDD
GND
Y
INV

INV and NAND3 Cells
❑ INV area: 16 l by 40 l → exactly as estimated!
❑ NAND3 area: 32 l by 40 l → exactly as estimated!
❑ Note source and drain sharing
❑ Practically: Use MANY substrate and well taps

Example
❑ Find the logic expression for the following gate.
A
VDD
GND
B C
Y
D

Example
❑ Estimate the cell width and height of the cell using min size transistors
A
VDD
GND
B C
Y
D

Example: O3AI
❑ Estimate the cell width and height of the cell using min size transistors
A
VDD
GND
B C
Y
D
6 tracks =
48 l
5 tracks =
40 l

Standard Cell Design
❑ Standard cell design methodology
▪ VDD and GND supply rails in M1 (uniform cell
height)
▪ nMOS at bottom and pMOS at top (uniform well
height)
▪ Adjacent gates should satisfy design rules
▪ All gates include well and substrate contacts
▪ Cells connected by abutment

Standard Cell Design cont’d

Antenna Rules
❑ Antenna effect:
▪ Metal wires charge up when it is plasma-etched
▪ May damage thin gate oxide (plasma-induced gate-oxide damage)
❑ Antenna rules define max metal area to gate oxide area to avoid damage

Antenna Rules cont'd
❑ Ways to fix it:
1) Jump to upper metal layer just before the gate
2) Add a reverse-biased diode (bleeds off the charges during the high-temperature
plasma-etch process)
3) Use M1 only: D/S diffusion is already a reverse-biased diode

Layer Density Rules
❑ Each layer must have adequate density to ensure uniform etching and proper CMP
❑ A metal layer may have to satisfy minimum density (e.g., 30%) and maximum density (e.g.,
70%)
❑ There are both global (whole chip) and local (e.g., 100µmx100µm area) density rules
❑ If not already satisfied by the design dummy structures (and holes) must be added to fix
the errors
❑ Foundries usually provide a “metal-fill” script to add dummy structures (and holes)
automatically
▪ May add parasitic capacitances or cause mismatch
▪ Should be disabled over sensitive analog circuitry (by using “fill-stop” layout layer)

Metal Slotting Rules
❑ Wide metal wires are usually used for global wires
(e.g., power routing) to decrease resistance
❑ Slots must be added parallel to the current flow to
provide stress relief and ensure proper fabrication
❑ Foundries usually provide a script to automate this
process

Latchup
❑ Ordinarily, both parasitic bipolar transistors are OFF.
❑ If substantial current flows in the substrate:
▪ Vsub  turning ON the npn transistor
▪ Vwell  turning ON the pnp-transistor
❑ A positive feedback loop is triggered with a large current flowing between VDD and GND
Find the mistake

Latchup
❑ Latchup prevention is easily accomplished by minimizing Rsub
and Rwell
▪ Use MANY substrate/well taps close to each transistor
❑ I/O pads are more prone to latchup because external
voltages can ring below GND or above VDD
▪ Current may flow into the substrate
▪ Guard rings should be used (a low resistance path to
collect stray currents)
❑ Latchup is not important for:
▪ SOI processes (no parasitic BJT)
▪ DSM nodes with VDD < 1.4 (no enough voltage to turn on
two BJTs)

Electromigration
❑ Electromigration refers to the gradual displacement of the metal atoms of a conductor as a
result of the current flowing through that conductor.
[http://eesemi.com/emig.htm] [https://en.wikipedia.org/wiki/Electromigration]

Transistor Layout
❑ The transistor is formed by the
intersection of polysilicon and diffusion
❑ Add “good” contacts to drain, source, and
substrate/well.
[F. Maloberti, Layout of Analog CMOS IC]
BAD GOOD

Multiple or Single Contact/Via?
❑ Curvature in the metal layer can cause fractures
02: CMOS Layout 30

Multi-finger Transistor Layout
❑ Transistors often have large W/L ratio
❑ Multi-finger layout is commonly used
▪ Compact layout
▪ Smaller parasitic capacitances
▪ Smaller gate resistance
02: CMOS Layout 31

Multi-finger Transistor Layout
02: CMOS Layout 32
[www.eda-utilities.com]

Multifinger Transistor Layout
❑ Transistors often have large W/L ratio
❑ Multifinger layout is commonly used
▪ Smaller parasitic capacitances
▪ Smaller gate resistance

FinFET Layout
[King Liu, Berkeley]
❑ Fin width, height, and pitch (Pfin) are
fixed by technology
❑ The channel width is quantized
❑ FinFET orientation is limited by DRs

Additional Topics
❑ FinFET Design
▪ https://www.youtube.com/watch?v=fPMBtEdfBVM
▪ https://www.youtube.com/watch?v=5D5HDyRbzxk
❑ Design and layout in FD-SOI 22nm technology
▪ https://www.globalfoundries.com/resources/technical-webinar-series/analog-design-
workshop-22fdx-22nm-fd-soi-technology-part-one
▪ https://www.globalfoundries.com/resources/technical-webinar-series/analog-design-
workshop-22fdx-22nm-fd-soi-technology-part-two
▪ https://www.globalfoundries.com/resources/technical-webinar-series/top-5-design-
guidelines-successfully-implement-22fdx-fd-soi-technology
02: CMOS Layout 35

Thank you!

Extra Material
FYI (For Your Information)

Interdigitated Devices
❑ Matching is extremely important for analog
❑ Current should be flowing in same direction
❑ Use interdigitated structures
▪ Each of A and B is 4 fingers
▪ AABBAABB
▪ ABBAABBA
1
2 3
A B

Common Centroid Layout
❑ Matched devices are laid out such that they have the same axis of symmetry
❑ First order process gradients are compensated
❑ Metal and poly connections are more complex

Dummy Structures
❑ Structures at the ends have different boundary
conditions compared to structures in the middle
❑ Dummy structures MUST be used
❑ Applies for transistors, resistors, and capacitors

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