UNIT-3-FIELD CONTROLLED DEVICES AND APPLICATIONS

P.SRIDHAR,AP/EEE,KONGUNADU COLLEGE OF ENGINEERING AND
TECHNOLOGY,TRICHY
3.1
KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY
(AUTONOMOUS)
NAMAKKAL-TRICHY MAIN ROAD, THOTTIAM, TRICHY -621 215
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
24EE302-ELECTRON DEVICES AND CIRCUITS
UNIT III
FIELD CONTROLLED DEVICES
JFET Construction, operation and characteristics:
The Field Effect Transistor (FET) is a three-terminal device used for a variety of
applications. The primary difference between the two types of transistors is the fact that the BJT
transistor is a current-controlled device, while the JFET transistor is a voltage controlled device
i.e. the output current is controlled by the electric field created by the applied potential to the
control terminal. Hence, the name “Field Effect Transistor”. BJT is a bipolar device i.e. the
conduction level is a function of two charge carriers, electrons and holes. The FET is a unipolar
device depending on either electron (n-channel) or hole (p-channel) conduction. The important
characteristic of the FET is its high input impedance.
Types of FET
Field Effect Transistor can be divided into three main types
1. Junction FET
2. Metal-Oxide Semiconductor FET or Insulated Gate FET
3. Metal-Semiconductor FET (MESFET)
JFET – JUNCTION FIELD EFFECT TRANSISTOR
Construction of n-Channel MOSFET
The basic structure of a JFET is shown in the figure.
Structure of n-channel & p-channel JFET

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 A FET consists of a P-type or N-type semiconductor bar with two PN junctions at the opposite
sides of its middle part. The space between the junctions is called a channel.
 If the bar is of N-type, it is called N-Channel FET and if the bar i of P-type, it is called P-
channel FET. The regions forming diodes are connected internally and a single wire is taken
out in the form of a terminal called the Gate(G).
 The electrical connections are made to both endsof the semiconductor bar and are taken out in
the form of two terminals called Drain (D) and Source (S).
Source: The source S is the terminal through which the majority carriers enter the bar.
Conventional current entering the bar at S is designated by IS.
Drain: The drain D is the terminal through which the majority carriers enter the bar.
Conventional current entering the bar at D is designated by ID.
Gate: On both sides of the semiconductor bar heavily doped regions of other type impurities
have been formed for creating p-n junctions. These impurity regions are called the gate G.
Between the gate and source a voltage VGS is applied in the direction to reverse-bias the p-n
junction. Conventional current entering the bar at G is designated IG.
Channel: The region in the semiconductor bar between the two gate regions throughwhich
majority carriers move from source to drain is called the channel.The source and drain
terminals are interchangeable (i.e.) either end can be used as asource with other end used as a
drain.
Symbol for n-channel JFET.
shows the schematic symbol for a N-channel JFET. In an N- channel JFET, the arrow points
towards the vertical line. The vertical line represents the N-channel.
Operation of JFET
(i) VGS=0V, VDS = some positive value
If VDS is increased to a level where it appears that the two depletion regions would
"touch" (the depletion regions cannot actually meet), a condition referred to as pinch-off
will result.
The level of VDS that establishes this condition is referred to as pinch-off voltage
and is denoted by VP. The high electric field prevents the depletion region from meeting.

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JFET at VGS =0V and VDS>0V
ID versus VDS for VGS=0V
 Hence, the current saturates i.e. for further increase in drain-to-source voltage, the drain
current remains constant. This region is called "pinch-off region”.
 As VDS is increased beyond VP, the region between the two depletion regions will increase in
length along the channel, but the level of ID, remains the same.
 When VDS>VP, the JFET has the characteristics of a current source i.e. the current is fixed at
ID=IDSS, but the voltage VDS (for levels > VP) is determined by the applied load.
VGS < 0V
 The voltage from gate to source, denoted by VGS is the controlling voltage of the JFET. For
the n-channel device the controlling voltage VGS is made more and more negative from its
VGS=0V level.
Application of a Negative Voltage to the Gate of JFET
 Positive voltage VDS has been applied across the channel and the gate has been connected
directly to the source to establish the condition VGS=0V. The instant the voltage VDD
(=VDS) is applied, the electrons will be drawn the drain terminal.

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 The path of charge flow reveals that the drain and source currents are equivalent (ID=IS). The
flow of charge is limited by the resistance of the n-channel between drain and source.
 As VDS is increased, the cross-sectional area of the channel will be reduced and the depletion
region is wider near the top of both p-type materials. The reason for the change in width of the
region is that the greater the applied reverse bias, the wider the depletion region.
 As the voltage VDS is increased from 0 to a few volts, the current will increase. The relative
straightness of the plot reveals that for the region of low values of VDS, the resistance is
constant. As VDS increases and approaches a level referred to as VP, the depletion regions will
widen, causing reduction in the channel width.
 The reduced path of conduction causes the resistance to increase and the curve in the graph to
occur as shown in figure.
Pinch-off (VGS=0V, VDS=VP)
Characteristics Curve
 As VGS increases (VGS< 0) by increasing reverse bias voltage, the depletion region widens
than for VGS=0V and pinch-off occurs at a lower value of VDS.
 Eventually, VGS when VGS =-V, will be sufficiently negative to establish a saturation level
that is 0mA, and the device will be "turned off.”
JFET characteristics:
 The V–I characteristics of a JFET is useful to understand the behaviour of the device.
These characteristics are plotted graphically with voltage on one axis and current on the
other axis.
 The two important characteristics of a JFET are,
1. Drain characteristics,

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2. Transfer characteristics
 Drain characteristics of a n-channel JFET is shown in figure 4.8. Drain characteristics
is a plot of drain current ID versus drain to source voltage VDS at different values of gate to
source voltage VGS.
(i) Cut-off region: With increase in the negative VGS voltage, the channel width available
for conduction decreases. At a certain voltage, VGS(off) the depletion region touch each
other to close the channel completely. The cut-off region corresponds to ID= 0 and
VGS>VGS(off).
(ii) Saturation region : Saturation region is that portion of the characteristics where ID
remains constant and does not change with changes in VDS. To use FET as an amplifier, it
is operated in this saturation region.
(iii) Ohmic region : In the ohmic region, the drain current ID varies with variation in the
drain to source voltage VDS. The JFET operates as a voltage variable resistance in the
ohmic region. The resistance offered by the JFET decreases with decrease in the value of
negative gate to source bias voltage (i.e.) negative VGS.
(iv) Breakdown region : If the value of VDS increased beyond pinch-off voltage VPthe drain
current ID remains constant, upto certain value of VDS. If VDS is further increased, the
voltage will be reached at which the gate-channel junction breaks down, due to avalanche
effect. At this point, the drain current (ID) increases very rapidly, and the device may be
destroyed.
Transfer characteristics:
The transfer characteristics of n-channel JFET is shown in figure.The curve represents
relationship between the drain current ID and gate to source voltage VGS:

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The transfer curve is obtained using Shockley's equation:
𝐈𝐃 = 𝐈𝐃𝐒𝐒 [𝟏 −
𝐕𝐆𝐒
𝐕𝐏
]2
The squared term of the equation results in a non-linear relationship between ID and
VGS, producing a curve that grows exponentially with decreasing magnitudes of VGS.
The transfer curve shows the operating limits of a JFET.
When VGS = 0V, ID = IDSS
When VGS = −VP[i. e. VGS(off), ID = 0mA
Characteristic parameters of JFET:
In a JFET, the drain current ID depends upon the drain voltage VDS and the gate voltage
VGS. Any one of these variables may be fixed and the relation between the other two is
determined.
Combined Characteristics Curve

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(1) Mutual conductance or transconductance (gm)- It is the ratio of a small change in the
drain current to the corresponding small change in the gate voltage at a constant drain
voltage. It has the unit of conductance in mho.
𝐠𝐦 = [
𝛛𝐈𝐃
𝛛𝐕𝐆𝐒
]𝐕𝐃𝐒𝐒
=
∆𝐈𝐃
∆𝐕𝐆𝐒
, 𝐕𝐃𝐒 𝐂𝐨𝐧𝐬𝐭𝐚𝐧𝐭
(2) Drain resistance (rd): It is the ratio of a small change in the drain voltage to the
corresponding small change in the drain current at a constant gate voltage. It has the unit
resistance of ohms.
𝐫𝐝 = [
𝛛𝐕𝐃𝐒
𝛛𝐈𝐃
]𝐕𝐆𝐒
=
∆𝐕𝐃𝐒
∆𝐈𝐃
, 𝐕𝐆𝐒 𝐂𝐨𝐧𝐬𝐭𝐚𝐧𝐭
(3) Amplification factor (µ): It is the ratio of a small change in the drain voltage to the
corresponding small change in the gate voltage at a constant drain current.
𝛍 = [
𝛛𝐕𝐃𝐒
𝛛𝐕𝐆𝐒
]𝐈𝐃
=
∆𝐕𝐃𝐒
∆𝐕𝐆𝐒
, 𝐈𝐃 𝐂𝐨𝐧𝐬𝐭𝐚𝐧𝐭
P-channel JFET:
The p-channel JFET is constructed in the same manner as the n-channel but with a
reversal of the p and n-type materials as shown in figure.
P-channel JFET
 The current directions are reversed and also the polarities for the voltages VGS and VDS. The
drain current flows due to the majority carriers holes.

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 The drain current increases with increase in the negative VDS voltage. The gate to source
voltage VGS is positive and the drain current decreases with increase the positive VGS voltage
due to reduction in the channel width.
Characteristics of a p-channel JFET:
(i) Drain characteristics
The drain characteristics of a p-channel JFET is shown in figure.
Drain Characteristics of a p-channel JFET
The shape of these characteristics is same as that for the n-channel JFET except for the
reversal of polarities of VDS and VGS.
(ii) Transfer Characteristics:
Figure shows the transfer characteristics of a p-channel JFET.
Transfer characteristics of a p-channel JFET

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It is mathematically expressed by using Shockley's equation.
ID = IDSS[1 −
VGS
VP
]2
Even though ID has reversed its direction, ID is not taken negative current. This is
because ID and IDSSboth have reversed their directions. VGS and VP are positive for the p-
channel JFET.
Comparison of JFET & BJT:
1. FET operation depends only on the flow of majority carriers - holes for P-channel FETs
and electrons for N-channel FETs. Therefore they are called Unipolar devices. Bipolar
transistor (BJT) operation depends on both minority and majority current carriers.
2. As FET has no junctions and the conduction is through an N-type or
semiconductor material. FET is less noisy than BJT.
3. As the input circuit of FET is reverse biased, FET exhibits a much higher input
impedance in the order of 100 MΩ) and low output impedance and there will be high
degree of isolation between input and output. So, FET can act as an excellent buffer
amplifier but the BJT has low input impedance because its input circuit is forward
biased.
4. FET is a voltage controlled device, i.e. voltage at the input terminal controls the output
current, whereas BJT is a current controlled device, i.e. the input current controls the
output current.
5. FETs are much easier to fabricate and are particularly suitable for ICs because they
occupy less space than BJTs.
6. The performance of BJT is degraded by neutron radiation because of the reduction in
minority-carrier lifetime, whereas FET can tolerate a much higher level of radiation
since they do not rely on minority carriers for their operation.
7. The performance of FET is relatively unaffected by ambient temperature
changes. As it has a negative temperature coefficient at high current levels, it
prevents the FET from thermal breakdown. The BJT has a positive temperature
coefficient at high current levels which leads to thermal breakdown.
8. Since FET does not suffer from minority carrier storage effects, it has higher
switching speeds and cut-off frequencies. BJT suffers from minority carrier
storage effects and therefore has lower switching speeds and cut-off frequencies.
9. FET amplifiers have low gain bandwidth product due to the junction capacitive effects
and produce more signal distortion except for small signal operation.
Applications of JFET:

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1. FET is used as a buffer in measuring instruments, receivers since it has high input
impedance and low output impedance.
2. FETs are used in RF amplifiers in FM tuners and communication equipment for the low
noise level.
3. Since the input capacitance is low, FETs are used in cascade amplifiers in
measuring and test equipments.
4. Since the device is voltage controlled, it is used as a voltage variable resistor in
operational amplifiers and tone controls.
5. FETs are used in mixer circuits in FM and TV receivers, and communication equipment
because inter modulation distortion is low.
6. It is used in oscillator circuits because frequency drift is low.
7. As the coupling capacitor is small, FETs are used in low frequency amplifiers in
hearing aids and inductive transducers.
8. FETs are used in digital circuits in computers and memory circuits because of its small
size.
MOSFET Construction, operation and characteristics:
MOSFET is the common term for the Insulated Gate Field Effect Transistor
(IGFET).There are two basic forms of MOSFET (i) Enhancement MOSFET and (ii) Depletion
MOSFET. The terms depletion and enhancement define their basic mode of operation.
Principle: By applying a transverse electric field across an insulator, deposited on the
semiconductor material, the thickness and hence the resistance of a conducting channel of a
semi conducting material can be controlled.
In depletion MOSFET, the controlling electric field reduces the number of minority
carriers available for conduction, where as in the enhancement MOSFET, application of
electric field causes an increase in the majority carrier density in the conducting regions of the
transistor.
n-channel depletion MOSFET
Depletion type MOSFET operates both in the enhancement and depletion mode. D-
MOSFET has physical channel.
Construction
 A slab of p-type material is formed from a silicon base and is referred to as the substrate.
The substrate is internally connected to the source terminal.
 Two highly doped n+
regions are diffused in a lightly doped substrate of p-type silicon
substrate. One n+
region is called the source S and the other one is called the drain D.

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 A thin insulating layer of SiO2 is grown over the surface of the structure and holes are cut
into the oxide layer, allowing contact with the source and drain.
 Then a thin layer of metal aluminum is formed over the layer of SiO2.
This metal layer covers the entire channel region and it forms the gate G. SiO2 is a
particular type of insulator referred to as a dielectric that sets up opposing electric fields
within the dielectric when exposed to an externally applied field.
 In this construction an n-channel is diffused between the source and drain to the basic
structure of MOSFĘT.
n- channel depletion type MOSFET
 The primary difference between the construction of depletion-type and enhancement-type
MOSFET is that there is absence of channel in the enhancement type whereas there is a
diffused channel in the depletion type.
n-Channel depletion type MOSFET with VGS=0V and Applied Voltage VDD
 The gate-to-source (VGS) voltage is set to zero volts by the direct connection from one
terminal to the other, a voltage VDS is applied across the drain-to-source terminals.

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 The result is an attraction for the positive potential at the drain by the free electrons of the
n-channel and a current is established through the channel. The resulting current with
VDS=0V is labelled as IDSS.
Reduction in Free Carriers in a Channel due to a Negative Potential at the Gate Terminal
 Now set the VGS at a negative voltage. The negative potential at the gate will tend to pressure
electrons toward the p-type substrate (like charges repel) and attract holes from the p-type
substrate (opposite charges attract).
 Depending on the magnitude of the negative bias established by VGS a level of recombination
between electrons and holes will occur that will reduce the number of free electrons in the n-
channel available for conduction.
 The more negative the bias, the higher the rate of recombination. The resulting level of drain
current is therefore reduced with increasing negative bias for VGS.
Drain and Transfer Characteristics for an n-channel Depletion type MOSFET
p-channel depletion MOSFET

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The construction of a p-channel depletion type MOSFET is exactly the reverse of n-
channel depletion MOSFET. That is, now there is an n-type substrate and p-type channel
asshown in figure 4.18.
p-channel depletion type MOSFET
As shown in the figure 4.19 voltage polarities and current directions are reversed. The
drain characteristics would appear exactly as in n-channel depletion type MOSFET but with
VDS having negative values, ID having positive values and VDS having opposite polarities as
shown in figure 4.19.
Drain Characteristics for p-channel Depletion type MOSFET
The reversal in VGS will result in a mirror image about the ID axis for the transfer
characteristics as shown in figure

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Transfer Characteristic for p-channel Depletion type MOSFET
The drain current will increase from cut-off at VGS = VP in the positive VGS region to
IDSS and then continue to increase for negative values of VGS.
Symbols : The symbols for n-and p-channel depletion type MOSFET is shown in figure 4.21.
Graphic symbols for (a) n-channel depletion type MOSFET(b) p-channel depletion type
MOSFET
The symbols reflect the construction of the device, due to gate insulation there is no
direct connection between the gate and the channel is represented by a space between the gate
and the other terminals of the symbol.
n-channel Enhancement MOSFET
Enhancement type MOSFET operates only in the enhancement mode and has no
depletion-mode. E-MOSFET has no physical channel.
Construction
 The construction of the n-channel enhancement type MOSFET is shown infigure4.22.A slab
of p-type material is formed from a silicon base and is referred to as the substrate. The
substrate is internally connected to the source terminal.
 Two highly doped n+
regions are diffused in a lightly doped substrate of p-type silicon
substrate. One n+
region is called the source S and the other one is called the drain D.

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 A thin insulating layer of SiO2 is grown over the surface of the structure and holes are cut
into the oxide layer allowing contact with the source and drain. Then a thin layer of metal
aluminium is formed over the layer of SiO2.
 This metal layer covers the entire channel region and it forms the gate G. SiO2 is a particular
type of insulator referred to as a dielectric that sets up opposing electric fields within the
dielectric when exposed to an externally applied field.
 There is no channel present between the two n-doped regions.
n-channel Enhancement type MOSFET
 The metal area of the gate, in conjunction with the insulating oxide layer of SiO2 and the
semiconductor channel forms a parallel plate capacitor. This device is called the insulated gate
FET because of the insulating layer of SiO2.
 This layer gives extremely high input impedance for the MOSFET.As there is no continuous
channel in an enhancement MOSFET, this condition is represented by broken line in the
symbols.
Operation and Characteristics
Channel Formation in the n-channel Enhancement type MOSFET

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 If VGS is set at 0V and a voltage applied between the drain and source, the absence of an n-
channel will result in a current of effectively zero amperes.
 If both VDS and VGS have been set at some positive voltage greater than 0V, establishing the
drain and gate at a positive potential with respect to the source.
 The positive potential at the gate will pressure the holes (since like charges repel) in the p-
substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p-
substrate. The result is a depletion region near the SiO2, insulating layer void of holes.
 However, the electrons to the p-substrate (the minority carriers of the material) will be
attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer.
As VGS is increased beyond the threshold level, the density of free carriers in the induced
channel will increase, resulting in an increased level of drain current.
Change in Channel and Depletion Region with Increasing level of VDS for a Fixed value of VGS
 However, if we keep VDS as constant and increase the level of VDS, the drain current will
reach the saturation level. The leveling of ID is due to a pinching-off process by the narrower
channel at the drain end of the induced channel.
Characteristics of n-channel Enhancement MOSFET

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 Reveals that as the level of VGS increases from VT to 8V the resulting saturation level for ID
also increases, from a level of 0mA to 10mA.
 The spacing between the levels of VGS increases as the magnitude of VGS increases and hence
the drain current increases. If VGS> VT, the drain current is related to the applied gate-to-
source voltage (VGS) by the following nonlinear relationship.
𝐈𝐃 = 𝐊(𝐕𝐆𝐒 − 𝐕𝐓)𝟐
 The squared term results in the nonlinear (i.e. curved) relationship between ID and
VGS. K is a constant term that is a function of the construction of the device. The value of K is
determined by the following equation.
𝐊 =
𝐈𝐃(𝐨𝐧)
(𝐕𝐆𝐒(𝐨𝐧)−𝐕𝐓)𝟐
Where, ID(on) and VGS(on) are the values at a particular point on the characteristics of the
device.
P-channel Enhancement type MOSFET
The characteristics of the p-channel enhancement type MOSFET is exactly the reverse
of that of n-channel enhancement type MOSFET. In this case, the substrate is of n-type and p-
doped regions under the drain and source connections as shown in figure 4.26.
p-Channel Enhancement type MOSFET
The drain characteristics will appear as shown in figure. The drain characteristics
appear with increasing levels of current for increasing negative values of VGS.

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Drain Characteristics of p-channel Enhancement MOSFET
The transfer characteristics of p-channel enhancement type MOSFET is shown in figure
Transfer characteristics of p-channel enhancement MOSFET
The transfer characteristics is the mirror image about the ID axis of the transfer curve with
ID increases for increasing negative values of VGS beyond VT.
Symbols:
 The graphic symbols for the n and p-channel enhancement type MOSFET are shown in.
The symbols reflect the actual construction of the device.
 The dashed line between drain and source reflect the fact that a channel does not exist
between the two under no-bias conditions. This is the only difference between the symbols for
the depletion-type and enhancement-type MOSFETs.
Symbols for (a) n-channel E-MOSFET and (b) p-channel E-MOSFET

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Comparison of MOSFET with JFET
1. In enhancement and depletion types of MOSFET, the transverse electric field induced
across an insulating layer deposited on the semiconductor material controls the
conductivity of the channel. In the JFET the transverse electric field a cross the reverse
biased PN junction controls the conductivity of the channel.
2. The gate leakage current in a MOSFET is of the order of 10-12
A. Hence the input
resistance of a MOSFET is very high in the order of 1010
Ω to 1015
Ω. The gate leakage
current of a JFET is of the order of 10-9
A and its input resistance is of the order of
108
Ω.
3. JFETs are operated only in the depletion mode. The depletion type MOSFET may be
operated in both depletion and enhancement mode.
4. Comparing to JFET, MOSFETs are easier to fabricate.
5. MOSFET has zero offset voltage. As it is a symmetrical device, the source and
drain can be interchanged. These two properties are very useful in analog signal
switching.
6. MOSFETs are widely used in digital VLSI circuits than JFETs because of their
advantages.
MOSFET SMALL SIGNAL MODEL
Depletion Type MOSFETS
The Shockley’s equation used for JFETs is also applicable to depletion-type MOSFETs
(D-MOSFETs) results in the same equation for gm. The AC equivalent model for D-MOSFETs
is exactly the same as that used for JFETs as shown in figure 4.30.
D-MOSFET AC Equivalent Model

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UNI JUNCTION TRANSISTOR (UJT)
A Uni Junction Transistor is a three terminal silicon semiconductor device.UJT has only
one PN junction like an ordinary diode. However, it is different from the ordinary diode in the
sense that it has three terminals.
Construction and its Symbol
Basic construction of UJT
It consists of an N-type silicon semiconductor bar and a P-type silicon region.
The N-type bar is called a base and the P-type region as the emitter. Thus a PN junction is
formed between the emitter and base regions. The emitter region is heavily doped, while the
base region is lightly doped. Due to this reason, the resistivity of the base material is very high.
Three terminals are taken out of the whole structure one from the emitter region and the two
from the ends of the base regions. These terminals are labelled as Emitter (E), Base 1(B1) and
base 2 (B2).
Equivalent Circuit of UJT
It consists of a diode and a resistance. The Diode (D) represents the PN junction, while
the resistance (rB1& rB2) is the internal bulk resistance of the silicon bar from one end to the
other. The resistance rBB represents the total resistance between the base terminals and is called
the inter base resistance. The resistance rBB is represented by the sum of two separate
resistances rB1& rB2
Equivalent Circuit

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The resistance rB1, represents the bulk resistance between the Emitter (E) and Base
1(B1),whereas resistance rB2, is the bulk resistance between the emitter (E) and base 2(B2).
∴ 𝐫𝐁𝐁 = 𝐫𝐁𝟏 + 𝐫𝐁𝟐
When there is no voltage applied to the UJT, the value of resistance, rBB 5Ω to 10 KΩ.
The resistance RB1, is shown as a variable resistance because the value of resistance RB1,varies
inversely with the emitter current (IE). Depending upon the values of emitter current, the value
of resistance rB1, can vary from 4 KΩ to 40Ω.
Intrinsic stand-off ratio (η)
Intrinsic stand-off ratio
As the emitter is open, the applied voltage VBB, divides itself across resistance rB1 and
rB2.The voltage across the resistance rB1 is
𝑉1 =
𝑟𝐵1
rB1+rB2
× 𝑉𝐵𝐵 =
𝑟𝐵1
rBB
× 𝑉𝐵𝐵
The resistance ratio
𝑟𝐵1
rBB
is known as intrinsic stand-off ratio and is designated by η. The
value of η is between 0.5 and 0.8.
The voltage drop across the resistance rB1 is called intrinsic stand off voltage. It reverse
biases the emitter side.
UJT Operation
Operation of UJT

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The emitter diode (D) is reverse biased by a voltage drop across the resistance rB1. (=η.
VBB) and its own barrier potential (VD). Thus the total reverse bias voltage across a diode is
equal to the sum of η. VBB and VD. This voltage reverse biases the PN junction and emitter
current is cut-off. But a small leakage current flows from B2 to emitter due to minority carriers.
𝐕𝐏 = 𝛈𝐕𝐁𝐁 + 𝐕𝐃
As the emitter voltage reaches the peak-point voltage, the diode conducts (i.e., it
becomes forward biased) and the emitter current begins to flow. Under this condition, the UJT
is said to be fired, triggered or turned ON.
Under this condition, holes are injected into N-type bar. These holes are repelled by the
terminal B1 and are attracted by the terminal B2. The presence of excess holes slightly reduces
the resistance RB1, which in turn reduces the intrinsic stand-off voltage (η.VBB). As a result of
this, the emitter current increases, while the voltage at the emitter (VE =η.VBB+) decreases.It
produces a negative resistance region in the V-I characteristic of UJT, and the UJT switches
from its OFF position to ON position.
V-I Characteristics of UJT
V-I Characteristics of UJT
There are two important points on the characteristics curve namely the peak point and
the valley point. These points divide the curve into three important regions i.e. cut-off region,
negative resistance region and saturation region.
(i) Cut-off region:
The region to the left of peak-point is called cut-off region. In the region, the
emitter voltage is below the peak-point voltage (VP) and the emitter current is
approximately zero. The UJT is in its OFF position in this region.

TECHNOLOGY,TRICHY
3.23
(ii) Negative resistance region:
The region between the peak-point and the valley point is called negative
resistance region. In this region, the emitter voltage decreases from VP to VV and the
emitter current increases from IP to IV. The increase in emitter current is due to the
decrease in resistance rB1.It is because of this fact that this region is called negative-
resistance region.
(iii) Saturation region:
The region beyond the valley point is called saturation region. In this region, the
device is in its ON position. The emitter voltage (VE) remains almost constant with the
increasing emitter current.
Applications :
1. Trigger device for SCRs and TRIACs
2. Non-sinusoidal oscillators
3. Saw-tooth generators
4. Timing circuits
UJT Relaxation Oscillator (or) Saw tooth Oscillator
(a) UJT Relaxation Oscillator(b) Output Waveforms
The relaxation oscillator using UJT is used to generate saw tooth waveform. It consists
of a UJT and a capacitor C which is charged through R as the supply voltage VBB is switched
ON. The voltage across the capacitor increases exponentially and when the capacitor voltage
reaches the peak point voltage VP(= VD+ η.VBB), the UJT starts conducting and the capacitor

TECHNOLOGY,TRICHY
3.24
voltage is discharged through EB1 and R1.After the peak point voltage of UJT is reached, it
provides negative resistance to the discharge path which is useful in the working of the
relaxation oscillator.
Frequency of Oscillation:
The time period and hence the frequency of the saw tooth wave can be calculated as
follows: Assuming that the capacitor is initially uncharged, the voltage V, across the capacitor
prior to the breakdown is given by,
𝐕𝐂 = 𝐕𝐕 + 𝐕𝐁𝐁 (𝟏 − 𝐞−
𝐭
𝐑𝐂)
The discharge of the capacitor occurs when VC is equal to the peak-point voltage.
𝐕𝐏 = 𝐕𝐃 + 𝛈𝐕𝐁𝐁
Substituting (4.26) and (4.25) we get
𝐕𝐃 + 𝛈𝐕𝐁𝐁 = 𝐕𝐕 + 𝐕𝐁𝐁 (𝟏 − 𝐞−
𝐭
𝐑𝐂)
By neglecting VD and VV ,
𝛈𝐕𝐁𝐁 = 𝐕𝐁𝐁 (𝟏 − 𝐞−
𝐭
𝐑𝐂)
𝐞−
𝐭
𝐑𝐂 = (𝟏 − 𝛈)
Take logarithm on both sides, (e−
t
RC) = ln(1 − η)
If the discharge time of the capacitor is neglected, then t=T, the period of the wave.
Therefore, frequency of oscillation of sawtooth wave.
−
t
RC
= ln (1 − η)
T= -RC ln(1-η)
T=RC ln (1-η)-1
T = RC ln (
1
1 − η
)
∴ 𝐓 = 𝟐. 𝟑𝟎𝟑 𝐑𝐂 𝐥𝐨𝐠𝟏𝟎 (
𝟏
𝟏−𝛈
)
If the discharge time of the capacitor is neglected, then t=T, the period of the wave.
Therefore, frequency of oscillation of saw tooth wave is given by,
𝒇 =
𝟏
𝑻
=
𝟏
𝟐.𝟑𝟎𝟑 𝐑𝐂𝐥𝐨𝐠𝟏𝟎
𝟏
(𝟏−𝛈)
Staff in charge HoD

UNIT-3-FIELD CONTROLLED DEVICES AND APPLICATIONS

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