Universal Reconfigurable Processing Platform For Space Rev Voice4

Universal Reconfigurable Processing Platform for Space Presented by Dorian Seagrave Gordonicus LLC

Introduction MAPLD 2009 Gordonicus LLC An increasing number of spacecraft system engineers and scientists are demanding: More processing power Flexible architecture Standard / COTS communication interfaces Multiple Mission Modes / Reconfigurability Small form factor Mission hardware reuse Low power High speed SERDES High Reliability

Features Reconfigurable State-of-the-Art High Speed Data Processing Capabilities MAPLD 2009 Gordonicus LLC STS125 Mission No blind and buried vias Flight Board meets NASA and IPC 6012 class 3 standards 1553 100 Mb Ethernet 200 Mb Spacewire routers COTs Interfaces: cPCI (33MHz) & High Speed SERDES on P2 This hardware platform provides these needs by combining: A Rad Hard LEON3FT Processor 1 Gbyte protected SDRAM Aeroflex LEON3FT UT699

LEON3FT Processing Applications Guidance, Navigation and Control (GNC) Control and Data Handling (CDH) Xilinx Monitoring and Reconfiguration MAPLD 2009 Gordonicus LLC

Xilinx Processing Applications High Speed DSP Algorithm Processing Image Processing Pose Estimation Algorithms Communications / Radio Data Encryption / Decryption Waveform Processing Instrument Data Validation and Compression Application Reconfigurable While in Flight MAPLD 2009 Gordonicus LLC

SPECIFICATIONS 5 PROCESSORS LEON3FT ASIC AeroFlex UT699 SPARC TM V8/LEON 3FT 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg 4 x 350 MHz PowerPC™ 405 Heritage Implementation Dual Xilinx QV4 FX60 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) STANDARD I/O INTERFACES 10 SPACEWIRE PORTS Up to 200Mbps (Configurable) Supports Cross stapping Multiple configurations CompactPCI 32 Bit, 33MHz Master and Slave Mode Supported PCI 2.2 Compliant NASA Hypertronics connectors Mil-Std-1553 A/B Mil-Std-1553 BC/RT/MT Based on the Actel Core1553 IP CONSOLE PORT LEON3FT UART Rate configurable MAPLD 2009 Gordonicus LLC FRONT PANEL DEVELOPMENT / DEBUG PORTS DEVELOPMENT LEON3FT 10T/100 Ethernet port Xilinx 10T/100 Ethernet port DEBUG LEON Debug Serial Port RTAX Debug Serial Port Xilinx Debug Serial Port JTAG MEMORY 1 GByte SDRAM Reed Solomon Protected corrects for 2 nibble upsets 8 GByte FLASH stored in two banks 16 Gbit SDRAM 4Gbits per PPC405 2 MBbyte SRAM Protected (Self Scrubbing) 32 KByte PROM CONFIGURABLE I/O 10 RS422/LVDS Transmit Ports Xilinx configured (Quad redundant) 10 RS422/LVDS Receive Ports Xilinx configured (Quad redundant) 39 Xilinx Backplane I/O 12 Actel I/O 2 LEON GPIO 2 Backplane Spacewire Backplane Ethernet SMALL SIZE DIMENSIONS Standard 3U cPCI Single slot front panel configuration supports: 4 SpaceWire, 1553 A/B , Console port and Debug. Dual slot front panel configuration supports additional SpaceWire ports. LOW POWER LEON3FT 2.5Volt Core Xilinx 1.2Volt Core

LEON3FT PROCESSOR & MEMORY LEON 3FT AeroFlex UT699 SPARC TM V8 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg MAPLD 2009 Gordonicus LLC MEMORY 1GByte SDRAM Reed Solomon Protected corrects for 2 nibble upsets 8GByte FLASH Stored in two banks 2MBbyte SRAM Protected (Self Scrubbing) 32KByte PROM

MAPLD 2009 Gordonicus LLC LEON3FT PROCESSOR & MEMORY LEON3FT Aeroflex UT699 2MByte SRAM (Internal EDAC ) 32KB PROM 1GByte SDRAM (Reed Solomon) 4GByte FLASH Actel RTAX TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg 52.8 MIPS 4GByte FLASH

Xilinx QV4 FX60 FPGAs & MEMORY Quad redundant or independent PPC processing Mixed operating systems Partial or Full reconfiguration CONFIGURABLE LOGIC per FX60 Logic Cells: 56,880 Slices: 25,880 Distributed RAM: 395kb XtremeDSP Slices: 128 Block RAM: 4,176Kb MAPLD 2009 Gordonicus LLC EMBEDDED PowerPC 405 350 MHz operation 16 KB instruction cache 16 KB data cache 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) MEMORY 16Gbit SDRAM 4Gbits per PPC405

MAPLD 2009 Gordonicus LLC Xilinx QV4 FX60 PPC 405 PPC 405 Xilinx QV4 FX60 XILINX PPC405 PROCESSORS & MEMORY PPC 405 512MByte SDRAM 200Mbps SpaceWire(4) Dual Xilinx QV4 FX60 PPC 405 700 DMIPs TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) 512MByte SDRAM 512MByte SDRAM 512MByte SDRAM LEON3FT Aeroflex UT699 Based on Heritage Architecture Implementation

Xilinx DSP Processing Architecture MAPLD 2009 Gordonicus LLC PPC1 PPC3 PPC0 PPC2 4 Designs = Quad Redundant or Single Strand 2 Designs = 1 Design per Xilinx 1 Design TMRed using both Xilinx Flexible Design Options : Node Interconnections

Xilinx Reconfiguration MAPLD 2009 Gordonicus LLC A Singe Node can be reconfigured with PPC1 PPC3 PPC0 PPC2 Bottom Xilinx QV4 FX60 Top Xilinx QV4 FX60 Xilinx Resources consist of 4 nodes. Node = PPC + surrounding FPGA fabric. Control Logic SDRAM SelectMap PPC Operating system PPC application code or Xilinx fabric reconfiguration WITHOUT disruption to the other nodes FLASH

STANDARD INTERFACES CompactPCI Console Port Async UART 1553 SpaceWire MAPLD 2009 Gordonicus LLC

CompactPCI MIL-STD-1553 A/B LEON3FT Console Port MAPLD 2009 Gordonicus LLC

SpaceWire Ports MAPLD 2009 Gordonicus LLC LEON3FT SpW Router 5 Port SpW Router 5 Port RTAX 200Mbps Configurable 200/100/50 Mbps 200Mbps Front Panel Conn. Thru-hole Jumpers F R O N T P A N E L C P C I P 2 Xilinx 200Mbps 10 Front Panel 4 Backplane 2 Backplane via Jumpers 200Mbps Configurable

Configurable I/O What if my instrument interface is not SpaceWire? What if I need a custom interface on the backplane? ie: I2C What if I forgot to add a control line to a device? MAPLD 2009 Gordonicus LLC

73 User Defined I/O MAPLD 2009 Gordonicus LLC LVDS OR RS422 LEON3FT F R O N T P A N E L C P C I P 2 Xilinx 39 User Defined I/O LVDS OR RS422 LVDS OR RS422 LVDS OR RS422 LVDS OR RS422 Sync / Async Serial IF I2C 1 Wire Protocol 10 Bi-Dir User Defined I/O 2 GPIO ACTEL 12 User Defined I/O

Development & Debug Ports LEON 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) Xilinx 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) LEON and Xilinx Ethernet ports can be connected LEON Dedicated Debug Port (DSU) Xilinx I/O to be used as serial ports Xilinx JTAG LEON JTAG ACTEL JTAG All Debug / Development ports are accessible from the front panel. Facilitates Hardware Reuse GSE reconfiguration without opening the box MAPLD 2009 Gordonicus LLC

RTAX 2000 CONFIGURATIONS CG624 Package Supports ALDEC RTAX development Suite. Flexible architecture using Gaisler/Aeroflex Cores MAPLD 2009 Gordonicus LLC

512MB 512MB 512MB MAPLD 2009 Gordonicus LLC Application RTAX SpW Router DownLink0 512MB SpaceWire SpaceWire SpW Router DownLink1 MissionCrd0 MissionCrd1 MissionCrd2 MissionCrd3 PPC 405 uP PPC 405 uP PPC 405 uP LEON3FT PPC 405 uP

Availability Contact Aeroflex Colorado Springs MAPLD 2009 Gordonicus LLC

Future …. MAPLD 2009 Gordonicus LLC Xilinx SIRF V5 Xilinx SIRF V5

Next Effort MAPLD 2009 Gordonicus LLC LEON3FT 16 MBytes EEPROM 8 Port SpW Router 16 GBytes FLASH 1 GByte SDRAM 1553 3U cPCI

Gordonicus LLC www.gordonicus.com Hardware Gordon Seagrave [email_address] Dorian Seagrave [email_address] Software Peter Cavender [email_address] John Gemmill [email_address] MAPLD 2009 Gordonicus LLC

Universal Reconfigurable Processing Platform For Space Rev Voice4

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