Verification strategies

Verification Strategies

Vinchip Systems
(a Design and Verification Company)

Chennai.

What is Verification ?

 A process used to demonstrate the functional correctness of a design
 To ensure that the result of some transformation is as expected

Verification Problems

 Was the spec correct ?
 Did the design team understand the spec?
 Was the blocks implemented correctly?
 Were the interfaces between the blocks correct?
 Does it implement the desired
 functionality?
 ……

Verification Approaches

 Top-down verification approach
 From system to individual components
 Bottom-up verification approach
 From individual components to system
 Platform-based verification approach
 Verify the developed IP’s in an existing platform
 System interface-based verification approach
 Model each block at the interface level
 Suitable for final integration verification

Advs. of Bottom-up Approach

 Locality
 Catching bugs is easier and faster with foundational IPs (sub-blocks)
 Design the SoC chip with these highly confidence “bug-free”IPs

Terminology
 Verification environment
 Commonly referred as test bench (environment)
 Definition of a Testbench
 A verification environment containing a set of components
 The Components are
 Bus functional models (BFMs),
 Bus monitors,
 Memory modules
 Interconnect of such components with the design-under-verification (DUV)
 Verification (test) suites (stimuli, patterns, vectors)
 Test signals and the expected response under given test benches

Testbench Design

 Auto or semi-auto stimulus generator is preferred
 Automatic response checking is highly recommended
 May be designed with the following techniques
 Testbench in HDL
 Testbench in programming language interface (PLI)
 Waveform-based
 Transaction-based
 Specification-based

Types of Verification Tests (1/2)

 Random testing
 Try to create scenarios that engineers do not anticipate
 Functional testing
 User-provided functional patterns
 Compliances testing
 Corner case testing
 Real code testing (application SW)
 Avoid misunderstanding the spec.

Types of Verification Tests (2/2)

 Regression testing
 Ensure that fixing a bug will not introduce another bug(s)
 Regression test system should be automated
 Add new tests
 Check results and generate report
 Distribute simulation over multiple computer
 Time-consuming process when verification suites become large

BugTracking

 A central database collecting known bugs and fixes
 Avoid debugging the same bug multiple times
 Good bug report system helps knowledge accumulation

VerificationPlan

 Verification plan is a part of the design reports
 Contents
 Test strategy for both blocks and top-level module
 Test bench components –BFM, bus monitors, …...
 Required verification tools and flows
 Simulation environment including block diagram
 Key features needed to be verified in both levels
 Regression test environment and procedure
 Clear criteria to determine whether the verification is successfully complete

Benefits of Verification Plan

 Verification plan enables
 Developing the test bench environment early
 Developing the test suites early
 Developing the verification environment in parallel with the design task by
a separate team
 Focusing the verification effort to meet the product shipment criteria
 Forcing designers to think through the time-consuming activities before
performing them

Verification strategies

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