SlideShare a Scribd company logo
1
Verilog HDLVerilog HDL
ASIC DESIGN USING
FPGA
BEIT VII
KICSIT
October 2 2012 Lecture 15
2
Time Scales
October 2 2012
• Delay values in one module need to be defined
by using certain time unit, e.g., 1 µs,
• Delay values in another module need to be
defined by using a different time unit, e.g. 100
ns.
•Verilog HDL allows the reference time unit for
modules to be specified with the `timescale
compiler directive.
`timescale <reference_time_unit> / <time_precision>
Lecture 15
3
Time Scales
October 2 2012
• The <reference_time_unit> specifies the unit of
measurement for times and delays.
• The <time_precision> specifies the precision to
which the delays are rounded off during
simulation.
• Only 1, 10, and 100 are valid integers for
specifying time unit and time precision.
Lecture 15
4
Time Scales
October 2 2012
• Example
Lecture 15
5
Time Scales
October 2 2012
• Example
Lecture 15
6
Time Scales
October 2 2012
• The two modules dummy1 and dummy2 are
identical in all respects, except that the time unit
for dummy1 is 100 ns and the time unit for
dummy2 is 1 µs.
• Thus the $display statement in dummy1
will be executed 10 times for each $display
executed in dummy2.
Lecture 15
7
Time Scales
October 2 2012
• The $time task reports the simulation time in
terms of the reference time unit for the module in
which it is invoked.
• The first few $display statements are
shown in the simulation output below to illustrate
the effect of the `timescale directive.
• Notice that the $display statement in
dummy2 executes once for every ten $display
statements in dummy1.
Lecture 15
8
Time Scales
October 2 2012 Lecture 15

More Related Content

PDF
Qsam simulator in IBM Quantum Lab cloud
PDF
Azure Quantum with IBM Qiskit and IonQ QPU
PPTX
Se 381 - lec 26 - 26 - 12 may30 - software design - detailed design - se de...
PPTX
Beit 381 se lec 3 - 46 - 12 feb14 - sd needs teams to develop intro
PPTX
Beit 381 se lec 1 - 30 - 12 feb07
PPTX
Transmission media presentation
PPT
Assic 11th Lecture
PDF
Software process improvement ten traps to avoid
Qsam simulator in IBM Quantum Lab cloud
Azure Quantum with IBM Qiskit and IonQ QPU
Se 381 - lec 26 - 26 - 12 may30 - software design - detailed design - se de...
Beit 381 se lec 3 - 46 - 12 feb14 - sd needs teams to develop intro
Beit 381 se lec 1 - 30 - 12 feb07
Transmission media presentation
Assic 11th Lecture
Software process improvement ten traps to avoid

Similar to Assic 15th Lecture (20)

PPTX
KiddieKiosk: Fun and Easy Self-Ordering System
PPTX
Digital signals design Module 2 - HDLs (1).pptx
PDF
Comparative Study of Delay Line Based Time to Digital Converter using FPGA
PPTX
SDC_file_vlsi_designFlow synopsys design.pptx
PDF
Lock free programming- pro tips
PDF
VLSI Static Timing Analysis Timing Checks Part 4 - Timing Constraints
PDF
SOC Chip Basics
PPT
Use Models for Extending IEEE 1687 to Analog Test
PDF
[Back2School] Constraint Develop.pdf- Chapter 3
PPTX
A_Brief_Summary_on_Summer_Courses[1]
DOCX
CIS3110 Winter 2016CIS3110 (Operating Systems) Assig.docx
PDF
PPTX
Lotstreaming
PPTX
Lecture 4 - Engineering project Scheduling.pptx
PPTX
VLSI Logic synthesis (1).pptx %ighdhdhshsgsgshshshfghhhhj
PDF
PGRR085_RIWG_Aug24.pdf
PPT
Unit 4 - Features of Verilog HDL (1).ppt
PPT
Presentation on CMOS based Domino Logic Design
PDF
Precision Timing for KPI Measurements
PPT
Assic 13th Lecture
KiddieKiosk: Fun and Easy Self-Ordering System
Digital signals design Module 2 - HDLs (1).pptx
Comparative Study of Delay Line Based Time to Digital Converter using FPGA
SDC_file_vlsi_designFlow synopsys design.pptx
Lock free programming- pro tips
VLSI Static Timing Analysis Timing Checks Part 4 - Timing Constraints
SOC Chip Basics
Use Models for Extending IEEE 1687 to Analog Test
[Back2School] Constraint Develop.pdf- Chapter 3
A_Brief_Summary_on_Summer_Courses[1]
CIS3110 Winter 2016CIS3110 (Operating Systems) Assig.docx
Lotstreaming
Lecture 4 - Engineering project Scheduling.pptx
VLSI Logic synthesis (1).pptx %ighdhdhshsgsgshshshfghhhhj
PGRR085_RIWG_Aug24.pdf
Unit 4 - Features of Verilog HDL (1).ppt
Presentation on CMOS based Domino Logic Design
Precision Timing for KPI Measurements
Assic 13th Lecture
Ad

More from babak danyal (20)

DOCX
applist
PPT
Easy Steps to implement UDP Server and Client Sockets
PPT
Java IO Package and Streams
PPT
Swing and Graphical User Interface in Java
PPT
Tcp sockets
PPTX
block ciphers and the des
PPT
key distribution in network security
PPT
Lecture10 Signal and Systems
PPT
Lecture8 Signal and Systems
PPT
Lecture7 Signal and Systems
PPT
Lecture6 Signal and Systems
PPT
Lecture5 Signal and Systems
PPT
Lecture4 Signal and Systems
PPT
Lecture3 Signal and Systems
PPT
Lecture2 Signal and Systems
PPT
Lecture1 Intro To Signa
PPT
Lecture9 Signal and Systems
PPT
Lecture9
PPT
Cns 13f-lec03- Classical Encryption Techniques
PPT
Classical Encryption Techniques in Network Security
applist
Easy Steps to implement UDP Server and Client Sockets
Java IO Package and Streams
Swing and Graphical User Interface in Java
Tcp sockets
block ciphers and the des
key distribution in network security
Lecture10 Signal and Systems
Lecture8 Signal and Systems
Lecture7 Signal and Systems
Lecture6 Signal and Systems
Lecture5 Signal and Systems
Lecture4 Signal and Systems
Lecture3 Signal and Systems
Lecture2 Signal and Systems
Lecture1 Intro To Signa
Lecture9 Signal and Systems
Lecture9
Cns 13f-lec03- Classical Encryption Techniques
Classical Encryption Techniques in Network Security
Ad

Recently uploaded (20)

PDF
Physiotherapy_for_Respiratory_and_Cardiac_Problems WEBBER.pdf
PPTX
Final Presentation General Medicine 03-08-2024.pptx
PDF
Chapter 2 Heredity, Prenatal Development, and Birth.pdf
PPTX
Pharma ospi slides which help in ospi learning
PDF
RMMM.pdf make it easy to upload and study
PPTX
IMMUNITY IMMUNITY refers to protection against infection, and the immune syst...
PDF
O7-L3 Supply Chain Operations - ICLT Program
PDF
TR - Agricultural Crops Production NC III.pdf
PDF
Pre independence Education in Inndia.pdf
PDF
Basic Mud Logging Guide for educational purpose
PDF
Computing-Curriculum for Schools in Ghana
PDF
VCE English Exam - Section C Student Revision Booklet
PPTX
PPT- ENG7_QUARTER1_LESSON1_WEEK1. IMAGERY -DESCRIPTIONS pptx.pptx
PPTX
Cell Structure & Organelles in detailed.
PPTX
Pharmacology of Heart Failure /Pharmacotherapy of CHF
PPTX
human mycosis Human fungal infections are called human mycosis..pptx
PDF
BÀI TẬP BỔ TRỢ 4 KỸ NĂNG TIẾNG ANH 9 GLOBAL SUCCESS - CẢ NĂM - BÁM SÁT FORM Đ...
PPTX
PPH.pptx obstetrics and gynecology in nursing
PDF
Black Hat USA 2025 - Micro ICS Summit - ICS/OT Threat Landscape
PPTX
Institutional Correction lecture only . . .
Physiotherapy_for_Respiratory_and_Cardiac_Problems WEBBER.pdf
Final Presentation General Medicine 03-08-2024.pptx
Chapter 2 Heredity, Prenatal Development, and Birth.pdf
Pharma ospi slides which help in ospi learning
RMMM.pdf make it easy to upload and study
IMMUNITY IMMUNITY refers to protection against infection, and the immune syst...
O7-L3 Supply Chain Operations - ICLT Program
TR - Agricultural Crops Production NC III.pdf
Pre independence Education in Inndia.pdf
Basic Mud Logging Guide for educational purpose
Computing-Curriculum for Schools in Ghana
VCE English Exam - Section C Student Revision Booklet
PPT- ENG7_QUARTER1_LESSON1_WEEK1. IMAGERY -DESCRIPTIONS pptx.pptx
Cell Structure & Organelles in detailed.
Pharmacology of Heart Failure /Pharmacotherapy of CHF
human mycosis Human fungal infections are called human mycosis..pptx
BÀI TẬP BỔ TRỢ 4 KỸ NĂNG TIẾNG ANH 9 GLOBAL SUCCESS - CẢ NĂM - BÁM SÁT FORM Đ...
PPH.pptx obstetrics and gynecology in nursing
Black Hat USA 2025 - Micro ICS Summit - ICS/OT Threat Landscape
Institutional Correction lecture only . . .

Assic 15th Lecture

  • 1. 1 Verilog HDLVerilog HDL ASIC DESIGN USING FPGA BEIT VII KICSIT October 2 2012 Lecture 15
  • 2. 2 Time Scales October 2 2012 • Delay values in one module need to be defined by using certain time unit, e.g., 1 µs, • Delay values in another module need to be defined by using a different time unit, e.g. 100 ns. •Verilog HDL allows the reference time unit for modules to be specified with the `timescale compiler directive. `timescale <reference_time_unit> / <time_precision> Lecture 15
  • 3. 3 Time Scales October 2 2012 • The <reference_time_unit> specifies the unit of measurement for times and delays. • The <time_precision> specifies the precision to which the delays are rounded off during simulation. • Only 1, 10, and 100 are valid integers for specifying time unit and time precision. Lecture 15
  • 4. 4 Time Scales October 2 2012 • Example Lecture 15
  • 5. 5 Time Scales October 2 2012 • Example Lecture 15
  • 6. 6 Time Scales October 2 2012 • The two modules dummy1 and dummy2 are identical in all respects, except that the time unit for dummy1 is 100 ns and the time unit for dummy2 is 1 µs. • Thus the $display statement in dummy1 will be executed 10 times for each $display executed in dummy2. Lecture 15
  • 7. 7 Time Scales October 2 2012 • The $time task reports the simulation time in terms of the reference time unit for the module in which it is invoked. • The first few $display statements are shown in the simulation output below to illustrate the effect of the `timescale directive. • Notice that the $display statement in dummy2 executes once for every ten $display statements in dummy1. Lecture 15
  • 8. 8 Time Scales October 2 2012 Lecture 15