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VLSI DESIGN LECTURE NOTE 10 SEQUENTIAL CIRCUITS.ppt

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SR latch , D latch and flipflop, static and dynamic sequential circuits.

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VLSI Design Insights
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Introduction to CMOS VLSI Design Sequential Circuits
Sequential Logic Slide 2 CMOS VLSI Design Outline  Sequencing  Sequencing Element Design  Max and Min-Delay  Clock Skew  Time Borrowing  Two-Phase Clocking
Sequential Logic Slide 3 CMOS VLSI Design Sequencing  Combinational logic – output depends on current inputs  Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline CL clk in out clk clk clk CL CL Pipeline Finite State Machine
Sequential Logic Slide 4 CMOS VLSI Design Sequencing Cont.  If tokens moved through pipeline at constant speed, no sequencing elements would be necessary  Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses  This is called wave pipelining in circuits  In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones.
Sequential Logic Slide 5 CMOS VLSI Design Sequencing Overhead  Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.  Inevitably adds some delay to the slow tokens  Makes circuit slower than just the logic delay – Called sequencing overhead  Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence
Sequential Logic Slide 6 CMOS VLSI Design Sequencing Elements  Latch: Level sensitive – a.k.a. transparent latch, D latch  Flip-flop: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register  Timing Diagrams – Transparent – Opaque – Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop)
Sequential Logic Slide 7 CMOS VLSI Design Sequencing Elements  Latch: Level sensitive – a.k.a. transparent latch, D latch  Flip-flop: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register  Timing Diagrams – Transparent – Opaque – Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop)
Sequential Logic Slide 8 CMOS VLSI Design Latch Design  Pass Transistor Latch  Pros + +  Cons – – – – – – D Q 
Sequential Logic Slide 9 CMOS VLSI Design Latch Design  Pass Transistor Latch  Pros + Tiny + Low clock load  Cons – Vt drop – nonrestoring – backdriving – output noise sensitivity – dynamic – diffusion input D Q  Used in 1970’s
Sequential Logic Slide 10 CMOS VLSI Design Latch Design  Transmission gate + - D Q  
Sequential Logic Slide 11 CMOS VLSI Design Latch Design  Transmission gate + No Vt drop - Requires inverted clock D Q  
Sequential Logic Slide 12 CMOS VLSI Design Latch Design  Inverting buffer + + + Fixes either • • – D   X Q D Q  
Sequential Logic Slide 13 CMOS VLSI Design Latch Design  Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input – Inverted output D   X Q D Q  
Sequential Logic Slide 14 CMOS VLSI Design Latch Design  Tristate feedback + –     Q D X
Sequential Logic Slide 15 CMOS VLSI Design Latch Design  Tristate feedback + Static – Backdriving risk  Static latches are now essential     Q D X
Sequential Logic Slide 16 CMOS VLSI Design Latch Design  Buffered input + +   Q D X  
Sequential Logic Slide 17 CMOS VLSI Design Latch Design  Buffered input + Fixes diffusion input + Noninverting   Q D X  
Sequential Logic Slide 18 CMOS VLSI Design Latch Design  Buffered output +   Q D X  
Sequential Logic Slide 19 CMOS VLSI Design Latch Design  Buffered output + No backdriving  Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading   Q D X  
Sequential Logic Slide 20 CMOS VLSI Design Latch Design  Datapath latch + -     Q D X
Sequential Logic Slide 21 CMOS VLSI Design Latch Design  Datapath latch + Smaller, faster - unbuffered input     Q D X
Sequential Logic Slide 22 CMOS VLSI Design Flip-Flop Design  Flip-flop is built as pair of back-to-back latches D Q     X D     X Q Q    
Sequential Logic Slide 23 CMOS VLSI Design Enable  Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew D Q Latch D Q en en   Latch D Q  0 1 en Latch D Q  en D Q  0 1 en D Q  en Flop Flop Flop Symbol Multiplexer Design Clock Gating Design
Sequential Logic Slide 24 CMOS VLSI Design Reset  Force output low when reset asserted  Synchronous vs. asynchronous D     Q Q     reset D       Q   D reset   Q   D reset reset   reset Synchronous Reset Asynchronous Reset Symbol Flop D Q Latch D Q reset reset     Q reset
Sequential Logic Slide 25 CMOS VLSI Design Set / Reset  Set forces output high when enabled  Flip-flop with asynchronous set and reset D       Q   reset set reset set
Sequential Logic Slide 26 CMOS VLSI Design Sequencing Methods  Flip-flops  2-Phase Latches  Pulsed Latches Flip-Flops Flop Latch Flop clk 1 2 p clk clk Latch Latch p p 1 1 2 2-Phase Transparent Latches Pulsed Latches Combinational Logic Combinational Logic Combinational Logic Combinational Logic Latch Latch Tc Tc /2 tnonoverlap tnonoverlap tpw Half-Cycle 1 Half-Cycle 1
Sequential Logic Slide 27 CMOS VLSI Design Timing Diagrams Flop A Y tpd Combinational Logic A Y D Q clk clk D Q Latch D Q clk clk D Q tcd tsetup thold tccq tpcq tccq tsetup thold tpcq tpdq tcdq tpd Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay tpcq Latch D-Q Cont. Delay tsetup Latch/Flop Setup Time thold Latch/Flop Hold Time Contamination and Propagation Delays
Sequential Logic Slide 28 CMOS VLSI Design Max-Delay: Flip-Flops F1 F2 clk clk clk Combinational Logic Tc Q1 D2 Q1 D2 tpd tsetup tpcq   sequencing overhead pd c t T        
Sequential Logic Slide 29 CMOS VLSI Design Max-Delay: Flip-Flops F1 F2 clk clk clk Combinational Logic Tc Q1 D2 Q1 D2 tpd tsetup tpcq   setup sequencing overhead pd c pcq t T t t        
Sequential Logic Slide 30 CMOS VLSI Design Max Delay: 2-Phase Latches Tc Q1 L1 1 2 L2 L3 1 1 2 Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3 Q1 D2 Q2 D3 D1 tpd1 tpdq1 tpd2 tpdq2   1 2 sequencing overhead pd pd pd c t t t T          
Sequential Logic Slide 31 CMOS VLSI Design Max Delay: 2-Phase Latches Tc Q1 L1 1 2 L2 L3 1 1 2 Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3 Q1 D2 Q2 D3 D1 tpd1 tpdq1 tpd2 tpdq2   1 2 sequencing overhead 2 pd pd pd c pdq t t t T t       
Sequential Logic Slide 32 CMOS VLSI Design Max Delay: Pulsed Latches Tc Q1 Q2 D1 D2 Q1 D2 D1 p p p Combinational Logic L1 L2 tpw (a) tpw > tsetup Q1 D2 (b) tpw < tsetup Tc tpd tpdq tpcq tpd tsetup   sequencing overhead max pd c t T           
Sequential Logic Slide 33 CMOS VLSI Design Max Delay: Pulsed Latches Tc Q1 Q2 D1 D2 Q1 D2 D1 p p p Combinational Logic L1 L2 tpw (a) tpw > tsetup Q1 D2 (b) tpw < tsetup Tc tpd tpdq tpcq tpd tsetup   setup sequencing overhead max , pd c pdq pcq pw t T t t t t               
Sequential Logic Slide 34 CMOS VLSI Design Min-Delay: Flip-Flops cd t  CL clk Q1 D2 F1 clk Q1 F2 clk D2 tcd thold tccq
Sequential Logic Slide 35 CMOS VLSI Design Min-Delay: Flip-Flops hold cd ccq t t t   CL clk Q1 D2 F1 clk Q1 F2 clk D2 tcd thold tccq
Sequential Logic Slide 36 CMOS VLSI Design Min-Delay: 2-Phase Latches 1, 2 cd cd t t  CL Q1 D2 D2 Q1 1 L1 2 L2 1 2 tnonoverlap tcd thold tccq Hold time reduced by nonoverlap
Sequential Logic Slide 37 CMOS VLSI Design Min-Delay: 2-Phase Latches 1, 2 hold nonoverlap cd cd ccq t t t t t    CL Q1 D2 D2 Q1 1 L1 2 L2 1 2 tnonoverlap tcd thold tccq Hold time reduced by nonoverlap
Sequential Logic Slide 38 CMOS VLSI Design Min-Delay: Pulsed Latches cd t  CL Q1 D2 Q1 D2 p tpw p L1 p L2 tcd thold tccq Hold time increased by pulse width
Sequential Logic Slide 39 CMOS VLSI Design Min-Delay: Pulsed Latches hold cd ccq pw t t t t    CL Q1 D2 Q1 D2 p tpw p L1 p L2 tcd thold tccq Hold time increased by pulse width
Sequential Logic Slide 40 CMOS VLSI Design Time Borrowing  In a flop-based system: – Data launches on one rising edge – Must setup before next rising edge – If it arrives late, system fails – If it arrives early, time is wasted – Flops have hard edges  In a latch-based system – Data can pass through latch while transparent – Long cycle of logic can borrow time into next – As long as each loop completes in one cycle
Sequential Logic Slide 41 CMOS VLSI Design Time Borrowing Example Latch Latch Latch Combinational Logic Combinational Logic Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary (a) (b) Latch Latch Combinational Logic Combinational Logic Loops may borrow time internally but must complete within the cycle 1 2 1 1 1 2 2
Sequential Logic Slide 42 CMOS VLSI Design How Much Borrowing? Q1 L1 1 2 L2 1 2 Combinational Logic 1 Q2 D1 D2 D2 Tc Tc/2 Nominal Half-Cycle 1 Delay tborrow tnonoverlap tsetup   borrow setup nonoverlap 2 c T t t t    2-Phase Latches borrow setup pw t t t   Pulsed Latches
Sequential Logic Slide 43 CMOS VLSI Design Clock Skew  We have assumed zero clock skew  Clocks really have uncertainty in arrival time – Decreases maximum propagation delay – Increases minimum contamination delay – Decreases time borrowing
Sequential Logic Slide 44 CMOS VLSI Design Skew: Flip-Flops F1 F2 clk clk clk Combinational Logic Tc Q1 D2 Q1 D2 tskew CL Q1 D2 F1 clk Q1 F2 clk D2 clk tskew tsetup tpcq tpdq tcd thold tccq   setup skew sequencing overhead hold skew pd c pcq cd ccq t T t t t t t t t               
Sequential Logic Slide 45 CMOS VLSI Design Skew: Latches Q1 L1 1 2 L2 L3 1 1 2 Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3     sequencing overhead 1 2 hold nonoverlap skew borrow setup nonoverlap skew 2 , 2 pd c pdq cd cd ccq c t T t t t t t t t T t t t t              2-Phase Latches     setup skew sequencing overhead hold skew borrow setup skew max , pd c pdq pcq pw cd pw ccq pw t T t t t t t t t t t t t t t t                          Pulsed Latches
Sequential Logic Slide 46 CMOS VLSI Design Two-Phase Clocking  If setup times are violated, reduce clock speed  If hold times are violated, chip fails at any speed  Working chips are most important – Analyzing clock skew difficult  An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times  Call these clocks 1, 2 (ph1, ph2)
Sequential Logic Slide 47 CMOS VLSI Design Safe Flip-Flop  Flip-flop with nonoverlapping clocks – Very slow – nonoverlap adds to setup time – But no hold times  In industry, use a better timing analyzer – Add buffers to slow signals if hold time is at risk D  X Q Q       
Sequential Logic Slide 48 CMOS VLSI Design Summary  Flip-Flops: – Very easy to use, supported by all tools  2-Phase Transparent Latches: – Lots of skew tolerance and time borrowing  Pulsed Latches: – Fast, some skew tol & borrow, hold time risk

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VLSI DESIGN LECTURE NOTE 10 SEQUENTIAL CIRCUITS.ppt

  • 2. Sequential Logic Slide 2 CMOS VLSI Design Outline  Sequencing  Sequencing Element Design  Max and Min-Delay  Clock Skew  Time Borrowing  Two-Phase Clocking
  • 3. Sequential Logic Slide 3 CMOS VLSI Design Sequencing  Combinational logic – output depends on current inputs  Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline CL clk in out clk clk clk CL CL Pipeline Finite State Machine
  • 4. Sequential Logic Slide 4 CMOS VLSI Design Sequencing Cont.  If tokens moved through pipeline at constant speed, no sequencing elements would be necessary  Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses  This is called wave pipelining in circuits  In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones.
  • 5. Sequential Logic Slide 5 CMOS VLSI Design Sequencing Overhead  Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.  Inevitably adds some delay to the slow tokens  Makes circuit slower than just the logic delay – Called sequencing overhead  Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence
  • 6. Sequential Logic Slide 6 CMOS VLSI Design Sequencing Elements  Latch: Level sensitive – a.k.a. transparent latch, D latch  Flip-flop: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register  Timing Diagrams – Transparent – Opaque – Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop)
  • 7. Sequential Logic Slide 7 CMOS VLSI Design Sequencing Elements  Latch: Level sensitive – a.k.a. transparent latch, D latch  Flip-flop: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register  Timing Diagrams – Transparent – Opaque – Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop)
  • 8. Sequential Logic Slide 8 CMOS VLSI Design Latch Design  Pass Transistor Latch  Pros + +  Cons – – – – – – D Q 
  • 9. Sequential Logic Slide 9 CMOS VLSI Design Latch Design  Pass Transistor Latch  Pros + Tiny + Low clock load  Cons – Vt drop – nonrestoring – backdriving – output noise sensitivity – dynamic – diffusion input D Q  Used in 1970’s
  • 10. Sequential Logic Slide 10 CMOS VLSI Design Latch Design  Transmission gate + - D Q  
  • 11. Sequential Logic Slide 11 CMOS VLSI Design Latch Design  Transmission gate + No Vt drop - Requires inverted clock D Q  
  • 12. Sequential Logic Slide 12 CMOS VLSI Design Latch Design  Inverting buffer + + + Fixes either • • – D   X Q D Q  
  • 13. Sequential Logic Slide 13 CMOS VLSI Design Latch Design  Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input – Inverted output D   X Q D Q  
  • 14. Sequential Logic Slide 14 CMOS VLSI Design Latch Design  Tristate feedback + –     Q D X
  • 15. Sequential Logic Slide 15 CMOS VLSI Design Latch Design  Tristate feedback + Static – Backdriving risk  Static latches are now essential     Q D X
  • 16. Sequential Logic Slide 16 CMOS VLSI Design Latch Design  Buffered input + +   Q D X  
  • 17. Sequential Logic Slide 17 CMOS VLSI Design Latch Design  Buffered input + Fixes diffusion input + Noninverting   Q D X  
  • 18. Sequential Logic Slide 18 CMOS VLSI Design Latch Design  Buffered output +   Q D X  
  • 19. Sequential Logic Slide 19 CMOS VLSI Design Latch Design  Buffered output + No backdriving  Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading   Q D X  
  • 20. Sequential Logic Slide 20 CMOS VLSI Design Latch Design  Datapath latch + -     Q D X
  • 21. Sequential Logic Slide 21 CMOS VLSI Design Latch Design  Datapath latch + Smaller, faster - unbuffered input     Q D X
  • 22. Sequential Logic Slide 22 CMOS VLSI Design Flip-Flop Design  Flip-flop is built as pair of back-to-back latches D Q     X D     X Q Q    
  • 23. Sequential Logic Slide 23 CMOS VLSI Design Enable  Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew D Q Latch D Q en en   Latch D Q  0 1 en Latch D Q  en D Q  0 1 en D Q  en Flop Flop Flop Symbol Multiplexer Design Clock Gating Design
  • 24. Sequential Logic Slide 24 CMOS VLSI Design Reset  Force output low when reset asserted  Synchronous vs. asynchronous D     Q Q     reset D       Q   D reset   Q   D reset reset   reset Synchronous Reset Asynchronous Reset Symbol Flop D Q Latch D Q reset reset     Q reset
  • 25. Sequential Logic Slide 25 CMOS VLSI Design Set / Reset  Set forces output high when enabled  Flip-flop with asynchronous set and reset D       Q   reset set reset set
  • 26. Sequential Logic Slide 26 CMOS VLSI Design Sequencing Methods  Flip-flops  2-Phase Latches  Pulsed Latches Flip-Flops Flop Latch Flop clk 1 2 p clk clk Latch Latch p p 1 1 2 2-Phase Transparent Latches Pulsed Latches Combinational Logic Combinational Logic Combinational Logic Combinational Logic Latch Latch Tc Tc /2 tnonoverlap tnonoverlap tpw Half-Cycle 1 Half-Cycle 1
  • 27. Sequential Logic Slide 27 CMOS VLSI Design Timing Diagrams Flop A Y tpd Combinational Logic A Y D Q clk clk D Q Latch D Q clk clk D Q tcd tsetup thold tccq tpcq tccq tsetup thold tpcq tpdq tcdq tpd Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay tpcq Latch D-Q Cont. Delay tsetup Latch/Flop Setup Time thold Latch/Flop Hold Time Contamination and Propagation Delays
  • 28. Sequential Logic Slide 28 CMOS VLSI Design Max-Delay: Flip-Flops F1 F2 clk clk clk Combinational Logic Tc Q1 D2 Q1 D2 tpd tsetup tpcq   sequencing overhead pd c t T        
  • 29. Sequential Logic Slide 29 CMOS VLSI Design Max-Delay: Flip-Flops F1 F2 clk clk clk Combinational Logic Tc Q1 D2 Q1 D2 tpd tsetup tpcq   setup sequencing overhead pd c pcq t T t t        
  • 30. Sequential Logic Slide 30 CMOS VLSI Design Max Delay: 2-Phase Latches Tc Q1 L1 1 2 L2 L3 1 1 2 Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3 Q1 D2 Q2 D3 D1 tpd1 tpdq1 tpd2 tpdq2   1 2 sequencing overhead pd pd pd c t t t T          
  • 31. Sequential Logic Slide 31 CMOS VLSI Design Max Delay: 2-Phase Latches Tc Q1 L1 1 2 L2 L3 1 1 2 Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3 Q1 D2 Q2 D3 D1 tpd1 tpdq1 tpd2 tpdq2   1 2 sequencing overhead 2 pd pd pd c pdq t t t T t       
  • 32. Sequential Logic Slide 32 CMOS VLSI Design Max Delay: Pulsed Latches Tc Q1 Q2 D1 D2 Q1 D2 D1 p p p Combinational Logic L1 L2 tpw (a) tpw > tsetup Q1 D2 (b) tpw < tsetup Tc tpd tpdq tpcq tpd tsetup   sequencing overhead max pd c t T           
  • 33. Sequential Logic Slide 33 CMOS VLSI Design Max Delay: Pulsed Latches Tc Q1 Q2 D1 D2 Q1 D2 D1 p p p Combinational Logic L1 L2 tpw (a) tpw > tsetup Q1 D2 (b) tpw < tsetup Tc tpd tpdq tpcq tpd tsetup   setup sequencing overhead max , pd c pdq pcq pw t T t t t t               
  • 34. Sequential Logic Slide 34 CMOS VLSI Design Min-Delay: Flip-Flops cd t  CL clk Q1 D2 F1 clk Q1 F2 clk D2 tcd thold tccq
  • 35. Sequential Logic Slide 35 CMOS VLSI Design Min-Delay: Flip-Flops hold cd ccq t t t   CL clk Q1 D2 F1 clk Q1 F2 clk D2 tcd thold tccq
  • 36. Sequential Logic Slide 36 CMOS VLSI Design Min-Delay: 2-Phase Latches 1, 2 cd cd t t  CL Q1 D2 D2 Q1 1 L1 2 L2 1 2 tnonoverlap tcd thold tccq Hold time reduced by nonoverlap
  • 37. Sequential Logic Slide 37 CMOS VLSI Design Min-Delay: 2-Phase Latches 1, 2 hold nonoverlap cd cd ccq t t t t t    CL Q1 D2 D2 Q1 1 L1 2 L2 1 2 tnonoverlap tcd thold tccq Hold time reduced by nonoverlap
  • 38. Sequential Logic Slide 38 CMOS VLSI Design Min-Delay: Pulsed Latches cd t  CL Q1 D2 Q1 D2 p tpw p L1 p L2 tcd thold tccq Hold time increased by pulse width
  • 39. Sequential Logic Slide 39 CMOS VLSI Design Min-Delay: Pulsed Latches hold cd ccq pw t t t t    CL Q1 D2 Q1 D2 p tpw p L1 p L2 tcd thold tccq Hold time increased by pulse width
  • 40. Sequential Logic Slide 40 CMOS VLSI Design Time Borrowing  In a flop-based system: – Data launches on one rising edge – Must setup before next rising edge – If it arrives late, system fails – If it arrives early, time is wasted – Flops have hard edges  In a latch-based system – Data can pass through latch while transparent – Long cycle of logic can borrow time into next – As long as each loop completes in one cycle
  • 41. Sequential Logic Slide 41 CMOS VLSI Design Time Borrowing Example Latch Latch Latch Combinational Logic Combinational Logic Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary (a) (b) Latch Latch Combinational Logic Combinational Logic Loops may borrow time internally but must complete within the cycle 1 2 1 1 1 2 2
  • 42. Sequential Logic Slide 42 CMOS VLSI Design How Much Borrowing? Q1 L1 1 2 L2 1 2 Combinational Logic 1 Q2 D1 D2 D2 Tc Tc/2 Nominal Half-Cycle 1 Delay tborrow tnonoverlap tsetup   borrow setup nonoverlap 2 c T t t t    2-Phase Latches borrow setup pw t t t   Pulsed Latches
  • 43. Sequential Logic Slide 43 CMOS VLSI Design Clock Skew  We have assumed zero clock skew  Clocks really have uncertainty in arrival time – Decreases maximum propagation delay – Increases minimum contamination delay – Decreases time borrowing
  • 44. Sequential Logic Slide 44 CMOS VLSI Design Skew: Flip-Flops F1 F2 clk clk clk Combinational Logic Tc Q1 D2 Q1 D2 tskew CL Q1 D2 F1 clk Q1 F2 clk D2 clk tskew tsetup tpcq tpdq tcd thold tccq   setup skew sequencing overhead hold skew pd c pcq cd ccq t T t t t t t t t               
  • 45. Sequential Logic Slide 45 CMOS VLSI Design Skew: Latches Q1 L1 1 2 L2 L3 1 1 2 Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3     sequencing overhead 1 2 hold nonoverlap skew borrow setup nonoverlap skew 2 , 2 pd c pdq cd cd ccq c t T t t t t t t t T t t t t              2-Phase Latches     setup skew sequencing overhead hold skew borrow setup skew max , pd c pdq pcq pw cd pw ccq pw t T t t t t t t t t t t t t t t                          Pulsed Latches
  • 46. Sequential Logic Slide 46 CMOS VLSI Design Two-Phase Clocking  If setup times are violated, reduce clock speed  If hold times are violated, chip fails at any speed  Working chips are most important – Analyzing clock skew difficult  An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times  Call these clocks 1, 2 (ph1, ph2)
  • 47. Sequential Logic Slide 47 CMOS VLSI Design Safe Flip-Flop  Flip-flop with nonoverlapping clocks – Very slow – nonoverlap adds to setup time – But no hold times  In industry, use a better timing analyzer – Add buffers to slow signals if hold time is at risk D  X Q Q       
  • 48. Sequential Logic Slide 48 CMOS VLSI Design Summary  Flip-Flops: – Very easy to use, supported by all tools  2-Phase Transparent Latches: – Lots of skew tolerance and time borrowing  Pulsed Latches: – Fast, some skew tol & borrow, hold time risk