Vlsi design notes l7 a&b batch , ece , sngce

MODULE 1
Silicon Crystal Growth
Electronic-Grade Silicon (EGS) is the raw material that is used for the preparation of single-
crystal silicon. EGS is actually a polycrystalline material of high purity. EGS has some
major impurities like boron, carbon, and residual donors. The pure EGS will have doping
elements in the parts per billion (ppb) range, and carbon less than 2 parts per million (ppm).
The step by step procedure regarding the production of EGS is shown in the block diagram
below.
Fig: Production of EGS from MGS
The process starts by the production of Metallurgical Grade Silicon (MGS) by charging it
with quartzite and carbon in an arc furnace. Quartzite is a relatively pure form of sand (SiQ2),
and carbon is obtained in the form of coal, coke, and wood chips.
The overall reaction in the furnace is given below.
SiC+Si02 = Si + SiO + CO

VLSI DESIGN
The MGS after being drawn off, has to be solidified at a purity of 98%. But this purity is not
enough for the manufacture of semiconductor devices. So, the MGS has to be pulverized
mechanically and reacted with anhydrous hydrogen chloride (HCI) to form trichlorosilane
(SiHCI3). The reaction is shown below.
Si + 3HCl = SiHCI3 + H2
With the help of a catalyst, the reaction takes place at a nominal temperature of 300°C. The
reaction creates products like silicon tetrachloride (SiCl4) and the chlorides of impurities. At
this point the purification process occurs. The purification process has to be done by
fractional distillation method as the products trichlorosilane and unwanted chlorides are
liquids at room temperature.
The purified SiHCI3 is subjected to chemical vapor deposition (CVD). The chemical
reaction is a hydrogen reduction of SiHCl3.
The chemical reaction is shown below.
2SiHCl3 + 2H2 = 2Si + 6HCl
The reaction takes place in a CVD reactor. A resistance heated Si-rod (4-mm diameter),
called a slim-rod, is used as the nucleation point for the deposition of silicon. Through the
process rods of EGC are obtained. which are up to 0.2 meters (or more) in diameter and
several meters in length. EGS can be cut from these rods as single chunks or crushed into
nuggets.
In order to achieve high overall efficiency, a feedback or recycling of reaction of by-products
is done. This is also shown in the figure above.
EGS can also be produced by pyrolysis method in which silane (SiH4) will be reacted with
heat. The reaction takes place at a high temperature of 900°C. The main advantage of using
silane instead of trichlorosilane is the lower production cost and less production of harmful
reaction by-products.
SiH4 + HEAT = Si + 2H2
In this process the CVD reactor is operated at about 900°C and supplied with silane instead
of trichlorosilane. The advantages of producing EGS from silane are lower cost and less
harmful reaction by-products.
Crystal Structure and Growing
The silicon wafermust be single crystal, but it does not represent an ideal crystal due to
following reasons:
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◾The wafer has finite boundaries; thus, atoms at the surfaces are incompletely bonded as
against those in the bulk of the wafer material.
◾The atoms are displaced from their ideal locations by thermal agitation.
Czochralski Crystal Growth Process (refer written notes)
The highly refined silicon (EGS) though free from impurities, is still polycrystalline. Hence it
is to be processed to become single crystal. The Czochralski crystal growth process is often
used for producing single-crystal silicon ingots. The diagram is given below.
Since monolithic ICs are usually fabricated on a substrate which is doped with impurity, the
poly-crystalline silicon with an appropriate amount of dopant is-put into a quartz crucible,
which is then placed inside a crystal growth furnace. The material is then heated to a
temperature that is slightly in excess of the silicon melting pint of 1420 degree Celsius. A
small single-crystal rod of silicon called a seed crystal is then dipped into the silicon melt.
The conduction of heat up the seed crystal will produce a reduction in the temperature of the
melt in contact with the seed crystal to slightly below the silicon melting point. The silicon
will therefore freeze onto the end of the seed crystal, and as the seed crystal is slowly pulled
up out of the melt it will pull up with it a solidified mass of silicon that will be a
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crystallographic continuation of the seed crystal. Both the seed crystal and the crucible are
rotated but in opposite directions during the crystal pulling process in order to produce
crystalline ingots of circular cross section.
The liquid solid interface remains near to the surface of the melt if the temperature and
pulling rate are correctly chosen. Even a long single crystal silicon is pulled from it. The
diameter of the ingot is controlled by the pulling rate and the melt temperature, with ingot
diameters of about 100 to 150 mm (4 to 6 inches) being the most common. The ingot length
will generally be of the order of 3 meter, and several hours are required for the “pulling” of a
complete ingot. The crystal pulling is done in an inert-gas atmosphere (usually argon or
helium), and sometimes a vacuum is used. This is done to prevent oxidation”
The pull-rate is closely related to the heat input and losses, crystal properties and dimensions.
The conditions for crystal pulling are therefore carefully controlled. For example, the melt
temperature is monitored with a thermocouple and feedback controller. Longer diameter
crystals have commercial advantages and can be grown. However, difficulties may be
encountered because of resistivity gradient across finished slices.
The crystal growth apparatus shown in the figure above consists of the following parts.
• Furnace
• Crystal pulling mechanism
• Ambient control facility
• Control system circuitry
The furnace consists of a crucible, susceptor (crucible support) and rotational mechanism,
heating element and power supply, and a chamber. As the crucible contains the melt, it is the
most important component of the growth apparatus. The crucible material should be
chemically unreactive with molten silicon. Also, the material should have high melting point,
thermal stability, and hardness. The materials for crucible, which satisfy these properties, are
silicon nitride (Si3N4) and fused silica (SiO2). The latter is in exclusive use nowadays. Fused
silica; however, reacts with silicon, releasing silicon and oxygen into the melt. In tins process
the crucible undergoes erosion. The susceptor, is used to support the silica crucible. It also
provides for better thermal conditions. Graphite is the material of choice because of its high-
temperature properties. The graphite should be pure to prevent contamination of the crystal
from impurities that would be volatilized from the graphite at the temperature involved. The
susceptor rests on a pedestal whose shaft is connected to a motor that provides rotation. The
whole assembly can usually be raised and lowered to keep the melt level equidistant from a
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fixed reference point, which is needed for automatic diameter control.
The chamber housing the furnace must provide easy
access to the furnace components to facilitate maintenance and cleaning. The furnace
structure must be airtight to prevent contamination from the atmosphere, and have a specific
design that does not allow any part of the chamber to become so hot that its vapour pressure
would be a factor in contaminating the crystal. Hottest parts of the apparatus are water cooled
Insulation is usually provided between the heater and the chamber wall.
The crystal-pulling mechanism consists of seed shaft or
chain, rotation mechanism, and seed chuck. The mechanism controls two parameters of die
growth process: pull rate and crystal rotation. Also, the pulling mechanism must have
minimum vibration and great precision. The seed holder and pulling mechanism must
maintain precise orientation perpendicular to the melt surface.
From the figure shown above you can see that the crystal leaves the furnace
through a purge tube, where ambient gas, if present, is directed along the surface of the
crystal to cool it. From the purge tube, the crystal enters an upper chamber, which is usually
separated from the furnace by an isolation valve.
The ambient control for the crystal growth apparatus consists of gas source, flow
control, purge lube, and exhaust or vacuum system. The crystal growth must be conducted in
an inert gas or vacuum as staled earlier. This is necessary because
• The hot graphite parts must be protected from oxygen to prevent erosion and
• The gas around the process should not react with the molten silicon. Growth in
vacuum meets these requirements.
Growth in a gaseous atmosphere, generally used on large growers, must use an inert gas such
as helium or argon. The inert gas may be at atmospheric pressure or at reduced pressure.
The control system for crystal growing may consist of micro processing sensors, and outputs
and provides control of process parameters such as temperature, crystal diameter, pull rate
and rotation speed. The use of digital or microprocessor-based systems for control is more
common because these rely less on operator intervention and have many parts of the process
pre-programmed.
Silicon Wafer Preparation
Ingot Trimming and Slicing
As soon as the crystal ingot is obtained using the above processes, the extreme top and
bottom portions of the ingot are cut off and the ingot surface is grounded to produce a
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constant and exact diameter. The normal diameter is usually 100,125, or 150 mm. A
crystallographic orientation flat is also ground along the length of the ingot. The ingot is then
sliced using a large-diameter stainless steel saw blade with industrial diamonds embedded
into the inner-diameter cutting edge. This will help in producing circular slices or wafers that
are about 600 to 1000 micro meters thick. The orientation flat serves as a useful reference
plane for various device processes.
Wafer Polishing and Cleaning
When the wafer is sliced, its surface will be heavily damaged. This can be made normal only
by polishing. The reasons for polishing are given below.
• To remove the damaged silicon from the sawn surface.
• To produce a highly planar or flat surface that will be required for the photo-
lithographic process especially when flue-line geometries are involved.
• To improve the parallel.
The sliced wafer will have saw marks and is 0.6 to 1 mm thick. This is quite rough. Hence it
has to be lapped to produce a flat surface. The wafer, before polishing, may have a surface
damage in the order of 75 micro meters. Even through lapping, only 60 micro meters can be
polished and scraped. The remaining 15 micro meters has to be removed with the help of
etching process. The chemical etch consists of an acid mixture, including nitric acid to
oxidize the surface and hydrofluoric acid to dissolve the oxide.
The wafer is then made into a mirror like finish by polishing it. This polishing is carried out
by using aluminium abrasive powders of decreasing grit size (down to a final 1 micro meters
diameter). Even after the polishing, the wafer will still have a surface damage of around 2
micro meters deep. This is removed by an additional chemical etching stage, which can
sometimes be simultaneous with the final polishing stage.
In most cases, only one side of the wafer s carefully polished to produce a mirror like image.
The other side is given a normal lapping procedure to provide a somewhat flat surface with
agreeable parallelism. After the wafer polishing operations are completed, the wafers are
thoroughly cleaned, and dried, and they are now ready to be used for the various processing
steps described in the following sections. Before discussing these steps let us discuss some
processing considerations necessary to maintain the purity and perfection of the material.
Wafer Processing Considerations
1. Chemical Cleaning
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The wafers are cleaned thoroughly as soon as the polishing is completed. Originally, the
silicon wafers are cleaned so as to remove all organic films, heavy metals, and particulars:.
The commonly used cleaning agents are aqueous mixtures of NH4OH – H2O2, HCI –
H2O2,and,H2SO4-H2O2.
All of the above solutions are good enough in removing metallic impurities, but, out of the
lot, the HCI – H2O2, mixture is the best
2. Gettering Treatments
The transition group elements which act as the metallic impurities are located at the
interstitial or substitutional lattice sites and act as generation-recombination centres for the
carriers. The precipitated forms of these impurities are usually silicides. These silicides are
known to be electrically conductive . In the case of VLSI circuits, these transition group
elements decrease their performance, especially in the case of dynamic random access
memories and narrow-base bipolar transistors, as they are sensitive to conductive impurity
precipitates.
Normally, a process called gettering treatment is carried out to remove the impurities.
Gettering is a process that removes,and harms the impurities or defects them from the
regions in a wafer where devices are fabricated. Pregettering refers to a gettering treatment
provided to silicon wafers that are used for IC processing. When the wafer with sinks are
developed for device processing, the impurities are absorbed with the help of pregettering
process. The common techniques that are used for gettering treatment are given below:
• Common mechanical abrasion methods like lapping and sand blasting are carried out
to damage the back surface of the wafer.
• A focused heat beam from a Q-pulsed, Nd-YAG laser is used to damage the wafer.
Dislocations are made in the wafer by rastering the laser beam along the wafer’s back
surface. Thus they become favorable trapping sites for fast-diffusing species.
• Intrinsic gettering - As told earlier, when an impurity oxygen precipitates, defects
are generated. The defects generated by oxygen precipitation are useful as trapping
sites. As the wafer is needed for device fabrication, high temperature cycle is
employed to lower the oxygen content near the surface of the wafer. Additional
thermal cycles are added to promote the formation of oxygen precipitates and defects
in the interior of the wafer.
Diffusion of Dopant Impurities
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The process of junction formation, that is transition from p to n type or vice versa, is typically
accomplished by the process of diffusing the appropriate dopant impurities in a high
temperature furnace. Impurity atoms are introduced onto the surface of a silicon wafer and
diffuse into the lattice because of their tendency to move from regions of high to low
concentration. Diffusion of impurity atoms into silicon crystal takes place only at elevated
temperature, typically 900 to 1100°C.
Although these are rather high temperatures, they are still well below the melting point of
silicon, which is at 1420°C. The rate at which the various impurities diffuse into silicon will
be of the order of 1 micro meter per hour at a temperature range stated above, and the
penetration depth that are involved in most diffusion processes will be of the order of 0.3 to
30 micro meter. At room temperature the diffusion process will be so extremely slow such
that the impurities can be considered to be essentially frozen in place.
A method of p-n junction formation which was popular in the early days is the grown
junction technique. In this method the dopant is abruptly changed in the melt during the
process of crystal growth. A convenient technique for making p-n junction is the alloying of a
metal containing doping atoms on a semiconductor with the opposite type of dopant. This is
called the alloyed junction technique. The p-n junction using epitaxial growth is widely used
in ICs. An epitaxial grown junction is a sharp junction. In terms of volume of production, the
most common technique for forming p-n junctions is the impurity diffusion process. This
produces diffused junction. Along with diffusion process the use of selective masking to
control junction geometry, makes possible the wide variety of devices available in the form
of IC’s. Selective diffusion is an important technique in its controllability, accuracy and
versatility.
Nature of Impurity Diffusion
The diffusion of impurities into a solid is basically the same type of process as occurs when
excess carriers are created non-uniformly in a semiconductor which cause carrier gradient. In
each case, the diffusion is a result of random motion, and particles diffuse in the direction of
decreasing concentration gradient The random motion of impurity atoms in a solid is, of
course, rather limited unless the temperature is high. Thus diffusion of doping impurities into
silicon is accomplished at high temperature as stated above.
There are mainly two types of physical mechanisms by which the impurities can diffuse
into the lattice. They are
1. Substitutional Diffusion
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VLSI DESIGN
At high temperature many atoms in the semiconductor move out of their lattice site, leaving
vacancies into which impurity atoms can move. The impurities, thus, diffuse by this type of
vacancy motion and occupy lattice position in the crystal after it is cooled. Thus,
substitutional diffusion takes place by replacing the silicon atoms of parent crystal by
impurity atom. In other words, impurity atoms diffuse by moving from a lattice site to a
neighbouring one by substituting for a silicon atom which has vacated a usually occupied site
as shown in the figure below.
Substitutional diffusion mechanism is applicable to the most common diffusants, such as
boron, phosphorus, and arsenic. These dopants atoms are too big to fit into the interstices or
voids, so the only way they can enter the silicon crystal is to substitute for a Si atom.
In order for such an impurity atom to move to a neighbouring vacant site, it has to overcome
energy barrier which is due to the breaking of covalent bonds. The probability of its having
enough thermal energy to do this is proportional to an exponential function of temperature.
Also, whether it is able to move is also dependent on the availability of a vacant neighbouring
site and since an adjacent site is vacated by a Si atom due to thermal fluctuation of the lattice,
the probability of such an event is again an exponent of temperature.
The jump rate of impurity atoms at ordinary temperatures is very slow, for example about 1
jump per 1050
years at room temperature! However, the diffusion rate can be speeded up by
an increase in temperature. At a temperature of the order 1000 degree Celsius, substitutional
diffusion of impurities is practically realized in sensible time scales.
2. Interstitial Diffusion
In such, diffusion type, the impurity atom does not replace the silicon atom, but instead
moves into the interstitial voids in the lattice. The main types of impurities diffusing by such
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VLSI DESIGN
mechanism are Gold, copper, and nickel. Gold, particularly, is introduced into silicon to
reduce carrier life time and hence useful to increase speed at digital IC’s.
Because of the large size of such metal atoms, they do not usually substitute in the silicon
lattice. To understand interstitial diffusion, let us consider a unit cell of the diamond lattice of
the silicon which has five interstitial voids. Each of the voids is big enough to contain an
impurity atom. An impurity atom located in one such void can move to a neighbouring void,
as shown in the figure below.
In doing so it again has to surmount a potential barrier due to the lattice, this time, most
neighbouring interstitial sites are vacant so the frequency of movement is reduced. Again, the
diffusion rate due to this process is very slow at room temperature but becomes practically
acceptable at normal operating temperature of around 1000 degree Celsius. It will be noticed
that the diffusion rate due to interstitial movement is much greater than for substitutional
movement. This is possible because interstitial diffusants can fit in the voids between silicon
atoms. For example, lithium acts as a donor impurity in silicon, it is not normally used
because it will still move around even at temperatures near room temperature, and thus will
not be frozen in place. This is true of most other interstitial diffusions, so long-term device
stability cannot be assured with this type of impurity.
Fick’s Laws of Diffusion
The diffusion rate of impurities into semiconductor lattice depends on the following
• Mechanism of diffusion
• Temperature
• Physical properties of impurity
• The properties of the lattice environment
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• The concentration gradient of impurities
• The geometry of the parent semiconductor
The behaviour of diffusion particles is governed by Fick’s Law, which when solved for
appropriate boundary conditions, gives rise to various dopant distributions, called profiles
which are approximated during actual diffusion processes.
In 1855, Fick drew analogy between material transfer in a solution and heat transfer by
conduction. Fick assumed that in a dilute liquid or gaseous solution, in the absence of
convection, the transfer of solute atoms per unit area in a one-dimensional flow can be
described by the following equation
F = -D ∂N(x,t)/∂x = -∂F(x,t)/∂x
where F is the rate of transfer of solute atoms per unit area of the diffusion flux density
(atoms/cm2
-sec). N is the concentration of solute atoms (number of atoms per unit
volume/cm3
), and x is the direction of solute flow. (Here N is assumed to be a function of x
and t only), t is the diffusion time, and D is the diffusion constant (also referred to as
diffusion coefficient or diffusivity) and has units of cm2
/sec.
The above equation is called Fick’s First law of diffusion and states that the local rate of
transfer (local diffusion rate) of solute per unit area per unit time is proportional to the
concentration gradient of the solute, and defines the proportionality constant as the
diffusion constant of the solute. The negative sign appears due to opposite direction of
matter flow and concentration gradient. That is, the matter flows in the direction of
decreasing solute concentration.
Fick’s first law is applicable to dopant impurities used in silicon. In general the dopant
impurities are not charged, nor do they move in an electric field, so the usual drift mobility
term (as applied to electrons and holes under the influence of electric field) associated with
the above equation can be omitted. In this equation N is in general function of x, y, z and t.
The change of solute concentration with time must be the same as the local decrease of
the diffusion flux, in the absence of a source or a sink. This follows from the law of
conservation of matter. Therefore we can write down the following equation
∂N(x,t)/∂t = -∂F(x,t)/∂x
Substituting the above equation to ‘F’. We get
∂N(x,t)/∂t = ∂/∂x[D*∂N(x,t)/∂x]
When the concentration of the solute is low, the diffusion constant at a given temperature can
be considered as a constant.
Thus the equation becomes,
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∂N(x,t)/∂t = D[∂2
N(x,t)/∂x2
]
This is Ficks second law of distribution.
Diffusion Profiles
Depending on boundary equations the Ficks Law has two types of solutions. These solutions
provide two types of impurity distribution namely constant source distribution following
complimentary error function (erfc) and limited source distribution following Gaussian
distribution function.
1)Constant Source (erfc) Distribution
In this impurity distribution, the impurity concentration at the semiconductor surface is
maintained at a constant level throughout the diffusion cycle. That is,
N (o,t) = NS = Constant
The solution to the diffusion equation which is applicable in this situation is most easily
obtained by first considering diffusion inside a material in which the initial concentration
changes in same plane as x=0, from NS to 0. Thus the equation can be written as
N (o,t) = NS = Constant and N(x,t) = 0
Shown below is a graph of the complementary error function for a range of values of its
argument. The change in concentration of impurities with time, as described by the equation
is also shown in the figure below. The surface concentration is always held at NS, falling to
some lower value away from the surface. If a sufficiently long time is allowed to elapse, it is
possible for the entire slice to acquire a dopant level of NS per m3
.
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VLSI DESIGN
If the diffused impurity type is different from the resistivity type of the substrate material, a
junction is formed at the points where the diffused impurity concentration is equal to the
background concentration already present in the substrate.
In the fabrication of monolithic IC’s, constant source diffusion is commonly used for the
isolation and the emitter diffusion because it maintains a high surface concentration by a
continuous introduction of dopant.
There is an upper limit to the concentration of any impurity that can be accommodated at the
semiconductor wafer at some temperature. This maximum concentration which determines
the surface concentration in constant source diffusion is called the solid solubility of the
impurity.
2)Limited Source Diffusion or Gaussian Diffusion
Here a predetermined amount of impurity is introduced into the crystal unlike constant source
diffusion. The diffusion takes place in two steps.
1. Predeposition Step – In this step a fixed number of impurity atoms are deposited on the
silicon wafer during s short time.
2. Drive-in step – Here the impurity source is turned off and the amounts of impurities
already deposited during the first step are allowed to diffuse into silicon water.
The essential difference between the two types of diffusion techniques is that the surface
concentration is held constant for error function diffusion. It decays with time for the
Gaussian type owing to a fixed available doping concentration Q. For the case of modelling
the depletion layer of a p-n junction, the erfc is modelled as a step junction and the Gaussian
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as a linear graded junction. In the case of the erfc, the surface concentration is constant,
typically the maximum solute concentration at that temperature or solid solubility limit.
Parameters which affect diffusion profile
• Solid Solubility – In deciding which of the availability impurities can be used, it is
essential to know if the number of atoms per unit volume required by the specific
profile is less than the diffusant solid solubility.
• Diffusion temperature – Higher temperatures give more thermal energy and thus
higher velocities, to the diffused impurities. It is found that the diffusion coefficient
critically depends upon temperature. Therefore, the temperature profile of diffusion
furnace must have higher tolerance of temperature variation over its entire area.
• Diffusion time – Increases of diffusion time, t, or diffusion coefficient D have
similar effects on junction depth as can be seen from the equations of limited and
constant source diffusions. For Gaussian distribution, the net concentration will
decrease due to impurity compensation, and can approach zero with increasing
diffusion tunes. For constant source diffusion, the net Impurity concentration on the
diffused side of the p-n junction shows a steady increase with time.
• Surface cleanliness and defects in silicon crystal - The silicon surface must be
prevented against contaminants during diffusion which may interfere seriously with
the uniformity of the diffusion profile. The crystal defects such as dislocation or
stacking faults may produce localized impurity concentration. This results in the
degradation of junction characteristics. Hence silicon crystal must be highly perfect.
Basic Properties of the Diffusion Process
Following properties could be considered for designing and laying out ICs.
• When calculating the total effective diffusion time for given impurity profile, one
must consider the effects of subsequent diffusion cycles.
• The erfc and Gaussian functions show that the diffusion profiles are functions of (x/
√Dt). Hence, for a given surface and background concentration, the junction depth x1
and x2 associated with the two separate diffusions having different times and
temperature
• Lateral Diffusion Effects – The diffusions proceed sideways from a diffusion
window as well as downward. In both types of distribution function, the side diffusion
is about 75 to 80 per cent of the vertical diffusion.
Dopants and their Characteristics
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The dopants selection affects IC characteristics. Boron and phosphorus are the basic dopants
of most ICs. Arsenic and antimony, which are highly soluble in silicon and diffuse slowly,
are used before epitaxial processing or as a second diffusion. Gold and silver diffuse rapidly.
They act as recombination centres and thus reduce carrier life time.
Boron is almost an exclusive choice as an acceptor impurity in silicon since other p-type
impurities have limitations as follows :
Gallium has relatively large diffusion coefficient in Si02, and the usual oxide window-
opening technique for locating diffusion would be inoperative, Indium is of little interest
because of its high acceptor level of 0.16 eV, compared with 0.01 eV for boron, which
indicates that not all such acceptors would be ionized at room temperature to produce a hole.
Aluminium reacts strongly with any oxygen that is present in the silicon lattice.
The choice of a particular n-type dopant is not so limited as for p-type materials. The n-type
impurities, such as phosphorus, antimony and arsenic, can be used at different stages of IC
processing. The diffusion constant of phosphorus is much greater than for Sb and As, being
comparable to that for boron, which leads to economies resulting from shorter diffusion
times.
Dopants in VLSI Technology
The common dopants in VLSI circuit fabrication are boron, phosphorus. and arsenic.
Phosphorus is useful not only as an emitter and base dopant, but also far gettering fast-
diffusing metallic contaminants, such as Cu and An, which cause junction leakage current
problems. Thus, phosphorus is indispensable in VLSI technology. However, n-p-n transistors
made with arsenic-diffused emitters have better low-current gain characteristics and better
control of narrow base widths than those made with phosphorus-diffused emitters. Therefore,
in V LSI, the use of phosphorus as an active dopant in small, shallow junctions and low-
temperature processing will be limited to its use as the base dopant of p-n-p device and as a
gettering agent. Arsenic is the most frequently used dopant for the source and drain regions in
n-channel MOSFETs.
Diffusion Systems
Impurities are diffused from their compound sources as mentioned above. The method
impurity delivery to wafer is determined by the nature of impurity source; Two-step diffusion
is widely technique. Using this technique, the impurity concentration and profiles can be
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carefully controlled. The type of impurity distribution (erfc or Gaussian) is determined by the
choice of operating conditions.
The two-step diffusion consists of a deposition step and a drive-in step. In the former step a
constant source diffusion is carried out for a short time, usually at a relatively low
temperatures, say, 1000°C. In the latter step, the impurity supply is shutoff and the existing
dopant is allowed to diffuse into the body of the semiconductor, which is now held at a
different temperature, say 1200°C, in an oxidizing atmosphere. The oxide layer which forms
on tire surface of the wafer during this step prevents further impurities from entering, or those
already deposited, from diffusing out. The final impurity profile is a function of diffusion
condition, such as temperature, time, and diffusion coefficients, for each step.
• Diffusion Furnace
For the various types of diffusion (and also oxidation) processes a resistance-heated tube
furnace is usually used. A tube furnace has a long (about 2 to 3 meters) hollow opening into
which a quartz tube about 100,150 mm in diameter is placed as shown in the figure below.
Diffusion Furnace
The temperature of the furnace is kept about1000°C. The temperature within the quartz
furnace tube can be controlled very accurately such that a temperature within 1/2°C of the
set-point temperature can be maintained uniformly over a “hot zone” about 1 m in length.
This is achieved by three individually controlled adjacent resistance elements. The silicon
wafers to be processed are stacked up vertically into slots in a quartz carrier or “boat” and
inserted into the furnace lube.
Diffusion Of p-Type Impurity
Boron is an almost exclusive choice as an acceptor impurity in silicon. It has a moderate
diffusion coefficient, typically of order I0-16 m2/sec at 1150°C which is convenient for
precisely controlled diffusion. It has a solid solubility limit of around 5 x 1026 atoms/m3, so
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that surface concentration can be widely varied, but most reproducible results are obtained
when the concentration is approximately 1024/m3, which is typical for transistor base
diffusions.
• Boron Diffusion using B2H6 (Diborane) Source
This is a gaseous source for boron. This can be directly introduced into the diffusion furnace.
A number of other gases are metered into the furnace. The principal gas flow in the furnace
will be nitrogen (N2) which acts as a relatively inert gas and is used as a carrier gas to be a
dilutent for the other more reactive gases. The N2, carrier gas will generally make up some 90
to 99 percent of the total gas flow. A small amount of oxygen and very small amount of a
source of boron will make up the rest of the gas flow. This is shown in the figure below. The
following reactions will be occurring simultaneously at the surface of the silicon wafers:
Si + 02 = SiO2 (silica glass)
2B2H6 + 302 = B2O3 (boron glass) + 6H2
This process is the chemical vapour deposition (CVD) of a glassy layer on (lie silicon surface
which is a mixture of silica glass (Si02) and boron glass (B203) is called borosilica glass
(BSG). The BSG glassy layer, shown in the figure below, is a viscous liquid at the diffusion
temperatures and the boron atoms can move around relatively easily.
Diffusion Of Dopants
Furthermore, the boron concentration in the BSG is such that the silicon surface will be
saturated with boron at the solid solubility limit throughout the time of the diffusion process
as long as BSG remains present. This is constant source (erfc) diffusion. It is often called
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VLSI DESIGN
deposition diffusion. This diffusion step is referred as pre-deposition step in which the dopant
atoms deposit into the surface regions (say 0.3 micro meters depth) of the silicon wafers. The
BSG is preferable because it protects the silicon atoms from pitting or evaporating and acts as
a “getter” for undesirable impurities in the silicon. It is etched off before next diffusion as
discussed below.
The pre-deposition step, is followed by a second diffusion process in which the external
dopant source (BSG) is removed such that no additional dopants cuter the silicon. During this
diffusion process the dopants that are already in the silicon move further in and are thus
redistributed. The junction depth increases, and at the same time the surface concentration
decreases. This type of diffusion is called drive-in, or redistribution, or limited-source
(Gaussian diffusion).
• Boron Diffusion using BBr3i (Boron Tribromide) Source
This is a liquid source of boron. In this case a controlled flow of carrier gas (N2,) is bubbled
through boron tribromide, as shown in the figure below, which with oxygen again produces
boron trioxide (BSG) at the surface of the wafers as per following reaction :
4BBr3 + 302 = B203 + 2Br2
Diffusion of n-Type Impurity
For phosphorus diffusion such compounds as PH3 (phosphine) and POCl3 (phosphorus
oxychloride) can be used. In the case of a diffusion using PoCI3, the reactions occurring at
the silicon wafer surfaces will be:
Si + 02 = SiO2 (silica glass)
4POCl + 302 = 2P205 + 6Cl2
This will result in the production of a glassy layer on the silicon wafers (hat is a mixture of
phosphorus glass and silica glass called phosphorosilica glass (PSG), which is a viscous
liquid at the diffusion temperatures. The mobility of the phosphorus atoms in this glassy layer
and the phosphorus concentration is such that the phosphorus concentration at the silicon
surface will be maintained at the solid solubility limit throughout the time of the diffusion
process (similar processes occur with other dopants, such as the case of arsenic, in winch
arsenosilica glass is formed on the silicon surface.
The rest of the process for phosphorus diffusion is similar to boron diffusion, that is, after
deposition step, drive-in diffusion is carried out.
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VLSI DESIGN
P205 is a solid source for phosphorus impurity and can be used in place of POCl3. However
POCl3 offers certain advantages overP205 such as easier source handling, simple furnace
requirements, similar glassware for low and high surface concentrations and better control of
impurity density from wafer to wafer and from run to run.
Ion Implantation
Ion Implantation is an alternative to a deposition diffusion and is used to produce a shallow
surface region of dopant atoms deposited into a silicon wafer. This technology has made
significant roads into diffusion technology in several areas. In this process a beam of impurity
ions is accelerated to kinetic energies in the range of several tens of kV and is directed to the
surface of the silicon. As the impurity atoms enter the crystal, they give up their energy to the
lattice in collisions and finally come to rest at some average penetration depth, called the
projected range expressed in micro meters. Depending on the impurity and its implantation
energy, the range in a given semiconductor may vary from a few hundred angstroms to about
1micro meter. Typical distribution of impurity along the projected range is approximately
Gaussian. By performing several implantations at different energies, it is possible to
synthesize a desired impurity distribution, for example a uniformly doped region.
Ion Implantation System
A typical ion-implantation system is shown in the figure below.
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VLSI DESIGN
A gas containing the desired impurity is ionized within the ion source. The ions are generated
and repelled from their source in a diverging beam that is focussed before if passes through a
mass separator that directs only the ions of the desired species through a narrow aperture. A
second lens focuses this resolved beam which then passes through an accelerator that brings
the ions to their required energy before they strike the target and become implanted in the
exposed areas of the silicon wafers. The accelerating voltages may be from 20 kV to as much
as 250 kV. In some ion implanters, the mass separation occurs after the ions are accelerated
to high energy. Because the ion beam is small, means are provided for scanning it uniformly
across the wafers. For this purpose the focussed ion beam is scanned electrostatically over the
surface of the wafer in the target chamber.
Repetitive scanning in a raster pattern provides exceptionally uniform doping of the wafer
surface. The target chamber commonly includes automatic wafer handling facilities to speed
up the process of implanting many wafers per hour.
Properties of Ion Implantation
The depth of penetration of any particular type of ion will increase with increasing
accelerating voltage. The penetration depth will generally be in the range of 0.1 to 1.0 micro
meters.
Annealing after Implantation
After the ions have been implanted they are lodged principally in interstitial positions in the
silicon crystal structure, and the surface region into which the implantation has taken place
20

VLSI DESIGN
will be heavily damaged by the impact of the high-energy ions. The disarray of silicon atoms
in the surface region is often to the extent that this region is no longer crystalline in structure,
but rather amorphous. To restore this surface region back to a well-ordered crystalline
state and to allow the implanted ions to go into substitutional sites in the crystal
structure, the wafer must be subjected to an annealing process. The annealing process
usually involves the heating of the wafers to some elevated temperature often in the
range of 1000°C for a suitable length of time such as 30 minutes.
Laser beam and electron-beam annealing are also employed. In such annealing techniques
only the surface region of the wafer is heated and re-crystallized. An ion implantation process
is often followed by a conventional-type drive-in diffusion, in which case the annealing
process will occur as part of the drive-in diffusion.
Ion implantation is a substantially more expensive process than conventional deposition
diffusion, both in terms of the cost of the equipment and the throughput, it does, however,
offer following advantages.
Advantages of Ion Implantation
• Ion implantation provides much more precise control over the density of dopants
deposited into the wafer, and hence the sheet resistance. This is possible because both
the accelerating voltage and the ion beam current are electrically controlled outside of
the apparatus in which the implants occur. Also since the beam current can be
measured accurately during implantation, a precise quantity of impurity can be
introduced. Tins control over doping level, along with the uniformity of the implant
over the wafer surface, make ion implantation attractive for the IC fabrication, since
this causes significant improvement in the quality of an IC.
• Due to precise control over doping concentration, it is possible to have very low
values of dosage so that very large values of sheet resistance can be obtained. These
high sheet resistance values are useful for obtaining large-value resistors for ICs. Very
low-dosage, low-energy implantations are also used for the adjustment of the
threshold voltage of MOSFET’s and other applications.
• An obvious advantage of implantation is that it can be done at relatively low
temperatures, this means that doped layers can be implanted without disturbing
previously diffused regions. This means a lesser tendency for lateral spreading.
High-Current High-Energy Implantation Machines
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VLSI DESIGN
The ion-implantation apparatus, discussed above, has limits to energy range. The minimum
implantation energy is usually set by the extraction voltage, that is, the voltage causing the
ions to move out of the ion source into the mass separator. This voltage (which is typically 20
KeV) cannot be reduced too far without drastically reducing beam current. The maximum
implantation energy is set by the design of the high voltage equipment. The only way to
circumvent this is to implant multiply-charged ions.
High beam currents are obtained by using multiple extraction electrodes and higher voltages.
To get a final beam of suitable energy a combination of acceleration and deceleration modes
of operation is used.
The electrostatic scanning is not suitable for high-beam currents, as it disrupts space charge
neutrality and leads to beam “blow-up”. Therefore a mechanical scanning system is usually
used. In this case, the wafer is scanned past a stationary beam. This method has the added
advantage of keeping the same beam angle across the whole wafer, whereas an electrostatic
system can vary by ±2° for 100 mm wafers. However, mechanical scanning puts new
requirements on the wafer holder.
High-energy implantation, at MeV energies, makes possible several new processing
techniques required for VLSI.
High-energy implantation machines however introduce high-voltage breakdown problem. At
about 400 KeV of energy electrical breakdown of the air around the high voltage equipment
occurs. Hence, above 400 KeV, conventional equipment is used. Also, high energy implants
frequently require water stages heated up to 600 degree Celsius, so that self annealing during
implantation minimizes damage in the surface layer. Mechanical scanning is used because of
the difficulty of electrostatically scanning a high-energy beam.
Problems in VLSI Processing
Now a day’s large diameter wafers are feasible. Large size wafers are necessary for VLSI.
This makes the task of uniformly implanting a wafer increasingly difficult. This in turn has
effect on sheet resistance. Ion implantation is basically clean process because contaminant
ions are separated from the beam before they hit the target. There are still several sources of
contamination possible near the end of the beam line, which can result in contaminant dose
up to 10 percent of the intended ion dose, for example, metal atoms knocked from chamber
walls, water holder, masking aperature and so on.
Annealing, as discussed earlier, is required to repair lattice damage and put dopant
atoms on substitutional site where they will be electrically active. The success of
22

VLSI DESIGN
annealing is often measured in terms of the fraction of the dopant that is electrically active, as
found experimentally using a Hall Effect technique. For VLSI, the challenge in annealing is
not simply to repair damage and activate dopant, but to do so while minimizing diffusion so
that shallow implants remain shallow. This has motivated much work in rapid thermal
annealing (RTA), where annealing times are on the order of seconds. RTA uses
tungsten-halogen lamps or graphite resistive strips to heat the wafer from one or both
sides as against conventional furnace annealing where times or on the order of minutes.
Modern device structures, such as the lightly-doped drains (LDD) for MOSFET, require
precise control of dopant distribution vertically and lateral on a very fine scale. For VLSI
CMOS structure, we need to form shallow n and layers with implantation energies within the
reach of standard machines. As stated earlier, the ion velocity, perpendicular to the surface,
determines the projected range of an implanted ion distribution. If the water is tilted at a large
angle to the ion beam then the effective ion energy is greatly reduced tilted ion beams, thus,
make it possible to achieve extremely shallow dopant distributions using comparatively high
implantation energies. We can circumvent the problem of implanting a shallow layer in
silicon completely if instead we implant entirely into a surface layer and then diffuse the
dopant into the substrate. This is most often done when the surface film is to be used as a
conductor making contact to the substrate. Diffusion results in steep dopant profiles without
damage to the silicon lattice. Dopant diffusion in silicides and polysilicon is generally much
faster than in single-crystal silicon, so the implanted atoms soon become uniformly
distributed in the film.
Importance of Ion Implantation for VLSI Technology
Ion implantation is a very popular process for VLSI because it provides more precise control
of dopants (as compared to diffusion). With the reduction of device sizes to the submicron
range, the electrical activation of ion-implanted species relies on a rapid thermal annealing
technique, resulting in as little movement of impurity atoms as possible. Thus, diffusion
process has become less important than methods for introducing impurity atoms into silicon
for forming very shallow junctions, an important feature of VLSI circuits. Ion, implantation
permits introduction of the dopant in silicon that is controllable, reproducible and free from
undesirable side effects. Over
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VLSI DESIGN
Oxidation
The function of a layer of silicon dioxide (SiO2) on a chip is multipurpose. SiO2 plays an
important role in IC technology because no other semiconductor material has a native oxide
which is able to achieve all the properties of SiO2. The role of SiO2 in IC fabrication is as
below
• It acts as a diffusion mask permitting selective diffusions into silicon wafer through
the window etched into oxide.
• It is used for surface passivation which is nothing but creating protective SiO2 layer
on the wafer surface. It protects the junction from moisture and other atmospheric
contaminants.
• It serves as an insulator on the water surface. Its high relative dielectric constant,
which enables metal line to pass over the active silicon regions.
• SiO2 acts as the active gate electrode in MOS device structure.
• It is used to isolate one device from another.
• It provides electrical isolation of multilevel metallization used in VLSI.
It is fortunate that silicon has an easily formed protective oxide, for otherwise we should have
to depend upon deposited insulators for surface protection. Since SiO2 produces a stable
layer, this has held back germanium IC technology.
Growth and Properties of Oxide Layers on Silicon
Silicon dioxide (silica) layer is formed on the surface of a silicon wafer by thermal oxidation
at high temperatures in a stream of oxygen.
Si+02 = SiO2 (solid)
The oxidation furnace used for this reaction is similar to the diffusion furnace. The thickness
of the oxide layer depends on the temperature of the furnace, the length of time that the
wafers are in it, and the flow rate of oxygen. The rate of oxidation can be significantly
increased by adding water vapour to the oxygen supply to the oxidizing furnace.
Si + 2H2O = SiO2 + 2H2
The time and temperature required to produce a particular layer thickness arc obtained from
empirically determined design curves, of the type shown in the figures given below
corresponding to dry- oxygen atmosphere and also corresponding to steam atmosphere.
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VLSI DESIGN
Growth and Properties of Oxide Layers on Silicon
In the past, steam was obtained by boiling ultra-high-purity water and passing it into the high-
temperature furnace containing the silicon wafers; however, present day technologies
generally use hydrogen and oxygen which are ignited in the furnace tube to form the ultra
high-purify water vapour.
The process of silicon oxidation takes place many times during the fabrication of an IC. Once
silicon has been oxidized the further growth of oxide is controlled by the thickness of the
initial or existing oxide layer.
Kinetics of oxidation
A well established model for thermal oxide growth has been proposed by Deal and Grove
Concept and Formulation (just for extra information-Not in syllabus)
If one assumes that the oxidation process is dominated by the inward movement of the
oxidant species, the transported species must go through the following stages:
(1) It is transported from the bulk of the oxidizing gas to the outer surface of oxide, where it
is adsorbed.
(2) It is transported across the oxide film towards silicon.
25

VLSI DESIGN
(3) It reacts at the interface with silicon and form a new layer of SiO2.
Each of these steps can be described as independent flux equation. The adsorption of oxidants
is written as
(1)
where is the gas-phase transport coefficient, is the equilibrium concentration of the
oxidants in the surrounding gas atmosphere, and Co is the concentration of oxidants at the
oxide surface at any given time.
It was found experimentally that wide changes in gas flow rates in the oxidation furnaces,
changes in the spacing between wafers on the carrier in the furnace, and a change in wafer
orientation (standing up or lying down) cause only little difference in oxidation rates. These
results imply that is very large, or that only a small difference between and Co is
required to provide the necessary oxidant flux.
is also the solubility limit in the oxide, which is assumed to be related to the partial
pressure p of the oxidant in the gas atmosphere by Henry's law
(2)
At natural ambient pressure of 1 atm and at a temperature of 1000 C, the solubility limits are
5.2 x10 cm for O2, and 3.0 x10 cm for H2O.
The flux F2 represents the diffusion of the oxidants through the oxide layer to the Si-SiO2
interface, which can be expressed as
(3)
where is the oxidant diffusivity in the oxide, Cs is the oxidant concentration at the oxide-
silicon interface, and xo represents the oxide thickness. In this expression it is assumed that
the process is in steady state (no changing rapidly with time), and that there is no loss of
oxidants when they diffuse through the oxide. Under these conditions, F2 must be constant
through the oxide and hence the derivative can be replaced simply by a constant gradient.The
third part of the oxidation process is the flux of oxidants consumed by the oxidation reaction
at the oxide-silicon interface given by
(4)
with ks as the surface rate constant. ks really represents a number of processes occurring at the
Si/SiO2 interface. These may include oxidant (O2 2O), Si-Si bond breaking, and/or Si-O
26

VLSI DESIGN
bond formation. The rate at which this reaction takes place should be proportional to the
oxidant concentration at the interface Cs.
Figure 2.16: One-dimensional model for the oxidation of silicon.
Deal and Grove assumed that in the steady state condition these three fluxes are equal, which
allows to express them as
(5)
The rate of oxide growth is proportional to the flux of oxidant molecules,
(6)
where N is the number of oxidant molecules incorporated per unit volume.
The differential equation can be simplified as
(7)
with the physically based parameters
(8)
(9)
Growth Rate of Silicon Oxide Layer
The initial growth of the oxide is limited by the rate at which the chemical reaction takes
place. After the first 100 to 300 A of oxide has been produced, the growth rate of the oxide
27

VLSI DESIGN
layer will be limited principally by the rate of diffusion of the oxidant (02 or H20) through the
oxide layer, as shown in the figures given below.
The rate of diffusion of O2 or H2O through the oxide layer will be inversely proportional to
the thickness of the layer, so that we will have that dx/dt = C/x
where x is the oxide thickness and C is a constant of proportionality. Rearranging this
equation gives xdx = Cdt
Integrating this equation both sides yields, x2
/2 = Ct
Solving for the oxide thickness x gives, x = √2Ct
We see that after an initial reaction-rate limited linear growth phase the oxide growth will
become diffusion-rate limited with the oxide thickness increasing as the square root of the
growth time. This is also shown in the figure below.
The rate of oxide growth using H2O as the oxidant will be about four times faster than the
rate obtained with O2. This is due to the fact that the H2O molecule is about one-half the size
of the O2 molecule, so that the rate of diffusion of H2O through the SiO2 layer will be much
greater than the O2 diffusion rate.
Oxide Charges
The interlace between silicon and silicon dioxide contains a transition region. Various
charges are associated with the oxidised silicon, some of which are related to the transition
region. A charge at the interface can induce a charge of the opposite polarity in the
underlying silicon, thereby affecting the ideal characteristics of the MOS device. This results
in both yield and reliability problems. The figure below shows general types of charges.
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VLSI DESIGN
• Interface-trapped charges
These charges at Si-SiO2 are thought to result from several sources including structural
defects related to the oxidation process, metallic impurities, or bond breaking processes. The
density of these charges is usually expressed in terms of unit area and energy in the silicon
band gap.
• Fixed oxide charge
This charge (usually positive) is located in the oxide within approximately 30 A of the Si –
SiO2 interface. Fixed oxide charge cannot be charged or discharged. From a processing point
of view, fixed oxide charge is determined by both temperature and ambient conditions.
• Mobile ionic charge
This is attributed to alkali ions such as sodium, potassium, and lithium in the oxides as well
as to negative ions and heavy metals. The alkali ions are mobile even at room temperature
when electric fields are present.
• Oxide trapped charge
This charge may be positive or negative, due to holes or electrons trapped in the bulk of the
oxide. This charge, associated with defects in the Si02, may result from ionizing radiation,
avalanche injection.
Effect of Impurities on the Oxidation Rate
The following impurities affect the oxidation rate
1. Water
2. Sodium
3. Group III and V elements
4. Halogen
In addition damage to the silicon also affects oxidation rate. As wet oxidation occurs at a
substantially greater rate than dry oxygen, any unintentional moisture accelerates the dry
29

VLSI DESIGN
oxidation. High concentrations of sodium influence the oxidation rate by changing the bond
structure in the oxide, thereby enhancing the diffusion and concentration of the oxygen
molecules in the oxide.
During thermal oxidation process, an interface is formed, which separates the silicon from
silicon dioxide. As oxidation proceeds, this interface advances into the silicon. A doping
impurity, which is initially present in the silicon, will redistribute at the interface until its
chemical potential is the same on each side of the interface. This redistribution may result in
an abrupt change in impurity concentration across the interface. The ratio of the equilibrium
concentration of the impurity, that is, dopant in silicon to that in SiO2 at the interface is called
the equilibrium segregation coefficient. The redistribution of the dopants at the interface
influences the oxidation behaviour. If the dopant segregates into the oxide and remains there
(such as Boron, in an oxidizing ambient), the bond structure in the silica weakens. This
weakened structure permits an increased incorporation and diffusivity of the oxidizing
species through the oxide thus enhancing the oxidation rate. Impurities that segregate into the
oxide but then diffuse rapidly through it (such as aluminium, gallium, and indium) have no
effect on the oxidation kinetics. Phosphorus impurity shows opposite effect to that of boron,
that is, impurity segregation occurs in silicon rather than Si02. The same is true for As and Sb
dopants.
Halogen (such as chlorine) impurities are intentionally introduced into the oxidation ambient
to improve both the oxide and the underlying silicon properties. Oxide improvement occurs
because there is a reduction in sodium ion contamination, increase in oxide breakdown
strength, and a reduction in interface trap density. Traps arc energy levels in the forbidden
energy gap which are associated with defects in the silicon.
Growth and Properties of Thin Oxides
MOS VLSI technology requires silicon dioxide thickness in the 50 to 500 A range in a
repeatable manner. This section is devoted to the growth and properties of such thin oxide.
This oxide must exhibit good electrical properties and provide long-term reliability. As an
example, the dielectric material for MOS devices can be thin thermal oxide. This dielectric is
an active component of the storage capacitor in dynamic RAMs, and its thickness determines
the amount of charge that can be stored.
The growth of thin oxide must be slow enough to obtain uniformity and reproducibility.
Various growth techniques for thin oxide are dry oxidation, dry oxidation with HCl,
sequential oxidations using different temperatures and ambients, wet oxidation, reduced
pressure techniques, and high pressure/low temperature oxidation. High pressure oxidation is
30

VLSI DESIGN
discussed later. The oxidation rate will, of course, be lower at lower temperatures and at
reduced pressures. Ultra-thin oxide (<50 A) have been produced using hot nitric acid, boiling
water, and air at room temperatures. Some recent developments in thin oxide growth
technique are
(i) Rapid thermal oxidation performed in a controlled oxygen ambient with heating provided
by tungsten-halogen lamps and
(ii) Ultraviolet pulsed laser excitation in an oxygen environment.
The properties of thin oxide depend upon the growth technique employed. For example,
oxide density increases as the oxidation temperature is reduced. Additionally, HCl ambients
have typically been used to passivate ionic sodium, improve the breakdown voltage, and
getter impurities and defects in the silicon. This passivation effect begins to occur only in the
higher temperature range.
For thin oxides, there is an increase in leakage for a given voltage. In thin oxides the
dielectric breakdown may be field-dependent (breakdown in a ramping field) or time-
dependent (breakdown at a constant field). This breakdown is a failure mode for MOS ICs.
Thinner oxides are more prone to failure.
High Pressure Oxidation
There is a benefit of increase in the oxidation rate if the thermal oxidation is carried out at
pressures that are much above atmospheric pressure. The rate of diffusion of the oxidant
molecules through an oxide layer is proportional to the ambient pressure. For example, at a
pressure of 10 atm the diffusion rate will be increased by a factor of 10 and the corresponding
oxidation time can be reduced by nearly the same factor. Alternatively, the oxidation can be
done for the same length of time, but the temperature required will be substantially lower.
Thus, one principal benefit of high-pressure oxidation processing is lower-temperature
processing. The lower processing temperature reduces the formation of crystalline defects
and produces less effect on previous diffusions and other processes. The shorter oxidation
time is also advantageous in increasing the system throughput. The major limitation of this
process is the high initial cost of the system.
Applications
Oxide Masking
The oxide layer is used to mask an underlying silicon surface against a diffusion (or ion
implantation) process. The oxide layer is patterned by the photolithographic process to
produce regions where there are opening or “windows” where the oxide has been removal to
expose the underlying silicon. Then these exposed silicon regions are subjected to the
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VLSI DESIGN
diffusion (or implantation) of dopants, whereas the unexposed silicon regions will be
protected. The pattern of dopant that will be deposited into the silicon will thus be a
replication of the pattern of opening in the oxide layer. The replication is a key factor in the
production of tiny electronic components.
The thickness of oxide needed for diffusion masking is a function of the type of diffusant and
the diffusion time and temperature conditions. In particular, an oxide thickness of some 5000
A will he vufftcieni to mask against almost all diffusions. This oxide thickness will also be
sufficient to block almost alt but the highest-energy ion implantation.
Oxide Passivation
The other function of Si02 in IC fabrication is the surface passivation. This is nothing but
creating protective Si02 layer on the wafer surface. The figure below shows a cross-sectional
view of a p-n junction produced by diffusion through an oxide window. There are lateral
diffusion effects, that is, the diffusion not only proceeds in the downward direction, but also
sideways as well, since diffusion is an isotropic process. The distance from the edge of the
oxide window to the junction in the lateral direction underneath die oxide is indicated as yj.
Lithography
Lithography is the process of transferring geometric shapes on a mask to the surface of a
silicon wafer. When a sample of crystalline silicon is covered with silicon dioxide, the oxide-
layer acts as a barrier to the diffusion of impurities, so that impurities separated from the
surface of the silicon by a layer of oxide do not diffuse into the silicon during high-
temperature processing.
The selective removal of the oxide in the desired area is performed with lithography. Thus,
the areas over which diffusions are effective are defined by the oxide layer with windows cut
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VLSI DESIGN
in it, through which diffusion can take place. The windows are produced by the lithographic
process. This process is the means by which microscopically small electronic circuits and
devices can be produced on silicon wafers resulting in as many as 10000 transistors on a 1
cm x 1 cm chip.
In IC fabrication a number of masks are employed. Except for the first mask, every mask
must be aligned to the pattern produced by the previous mask. This is done using mask
aligner. The mask aligner may be contact type or proximity type or projection type.
Accordingly we have three types of printing. They are
◾Contact printing
◾Proximity printing
◾Projection printing
Photolithography
In this process the exposing radiation, such as ultraviolet (UV) light in case of
photolithography, is transmitted through the clear parts of the mask. The circuit pattern of
opaque chromium blocks some of die radiation. This type of chromium/glass mask is used
with UV light.
Photolithographic Process Steps
1. Photoresist Application (Spinning)
A drop of light-sensitive liquid called photoresist is applied to the centre of the oxidized
silicon wafer that is held down by a vacuum chuck. The wafer is then accelerated rapidly to a
rotational velocity in the range 3000 to 7000 RPM for some 30 to 60 seconds. This action
spreads the solution in a thin, nearly uniform coat and spins off the excess liquid. The
thickness of the coat so obtained is in the range 5000 to 10000 A, as shown in the figure
below. The thickness of the photoresist layer will be approximately inversely proportional to
the square root of the rotational velocity.
Sometimes prior to the application of the photoresist the silicon wafers are given a “bake-out”
at a temperature Of at least 100°C to drive off moisture from the wafer surfaces so as to
obtain better adhesion of the photoresist. Typical photoresist used is Kodak Thin Film Resist
(KTFR).
2. Prebake
The silicon wafers coated with photoresist are now put into an oven at about 80°C for about
30 to 60 minutes to drive off solvents in the photoresist and to harden it into a semisolid film.
3. Alignment and Exposure
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VLSI DESIGN
The coated wafer, as above, is now placed in an apparatus called a mask aligner in very close
proximity (about 25 to 125 micro meters) to a photomask. The relative positions of the wafer
and the photomasks are adjusted such that the photomask is correctly lined up with reference
marks or a pre-existing pattern on the wafer.
The photomask is a glass plate, typically about 125 mm square and about 2 mm thick. The
photomask has a photographic emulsion or thin film metal (generally chromium) pattern on
one side. The pattern has clear and opaque areas. The alignment of the photomask to the
wafer is often required to be accurate to within less than 1 micro meter, and in some cases to
within 0.5 micro meters. After proper alignment has been achieved, the wafer is brought into
direct contact with the photomask. Photomask making will be described separately.
A highly collimated ultraviolet (UV) light is then turned on and the areas of the silicon wafer
that are not covered by the opaque areas of the photomask are exposed to ultraviolet
radiation, as shown in the figure. The exposure time is generally in the range 3 to 10 seconds
and is carefully controlled such that the total UV radiation dosage in watt-seconds or joules is
of the required amount.
4. Development
Two types of photoresist exist- negative photoresist and positive photoresist. In the present
description negative photoresist is used in which the areas of the photoresist that are exposed
the ultraviolet radiation become polymerized. The polymerization process increases the
length of the organic chain molecules that make up the photoresist. This makes the resist
tougher and makes it essentially insoluble in the developer solution. The resisting photoresist
pattern after the development process will therefore be a replication of the photomask pattern,
with the clear areas on the photomask corresponding to the areas where the photoresist
remains on the wafers, as shown in the figure below.
An opposite type of process occurs with positive photoresist. Exposure to UV radiation
results in depolymerization of the photoresist. This makes these exposed areas of the
photoresist readily soluble in the developer solution, whereas the unexposed areas are
essentially insoluble. The developer solution will thus remove the exposed or depolymerized
regions of the photoresist, whereas the unexposed areas will remain on the wafer. Thus again
there is a replication of the photomask pattern, but this time the clear areas of the photomask
produce the areas on the wafer from which the photoresist has been removed.
5. Postbake
After development and rinsing the wafers are usually given a postbake in an oven at a
temperature of about 150°C for about 30 to 60 minutes to toughen further the remaining resist
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VLSI DESIGN
on the wafer. This is to make it adhere better to the wafer and to make it more resistant to the
hydrofluoric acid [HF] solution used for etching of the silicon dioxide.
6. Oxide Etching
The remaining resist is hardened and acts as a convenient mask through which the oxide layer
can be etched away to expose areas of semiconductor underneath. These exposed areas are
ready for impurity diffusion.
For etching of oxide, the wafers are immersed in or sprayed with a hydrofluoric [HF] acid
solution. This solution is usually a diluted solution of typically 10: 1, H2O : HF, or more often
a 10 : 1 NH4F [ammonium fluoride]: HF solution. The HF solutions will etch the SiO2 but
will not attack the underlying silicon, nor will it attack the photoresist layer to any
appreciable extent. The wafers are exposed to the etching solution ion enough to remove the
SiO2 completely in the areas of the wafer that are not covered by the photoresist as shown in
the figure.
The duration of oxide etching should be carefully controlled so that all of the oxide present
only in the photoresist window is removed. If etching time is excessively prolonged, it will
result in more undercutting underneath the photoresist and widening of the oxide opening
beyond what is desired.
The above oxide etching process is termed wet etching process since the chemical reagents
used are in liquid form. A newer process for oxide etching is a dry etching process called
plasma etching. Another dry etching process is ion milling.
7. Photoresist Stripping
Following oxide etching, the remaining resist is finally removed or stripped off with a
mixture of sulphuric acid and hydrogen peroxide and with the help of abrasion process.
Finally a step of washing and drying completes the required window in the oxide layer. The
figure below shows the silicon wafer ready for next diffusion.
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VLSI DESIGN
Photolithographic Process Steps
Negative photoresists, as above, are more difficult to remove. Positive photoresists can
usually be easily removed in organic solvents such as acetone.
The photolithography may employ contact, proximity, or projection printing. For IC
production the line width limit of photolithography lies near 0.4 micro meters, although 0.2
micro meters features may be printed under carefully controlled conditions. At present, the
photolithography occupies the primary position among various lithographic techniques.
Photoresists
One of the major factors in providing increasingly complex devices has been improvement in
photolithographic art. A large part of this improvement has been due to high quality
photoresist, materials as improved techniques of coating, baking, exposing and developing
photoresists.
The principal constituents of a photoresist solution are a polymer, a sensitizer and a suitable
solvent system Polymers have properties of excellent film forming and coating. Polymers
generally used are polyvinyl cinnamate, partially cyclized isoprene family and other types are
phenol formaldehyde.
When photoresist is exposed to light, sensitizer absorbs energy and initiates chemical changes
in the resist. The sensitizers are chromophoric organic molecules. They greatly enhance cross
linking of the photoresist. Cross linking of polymer or long chain formation of considerable
number of monomers makes high molecular weight molecules on exposure to light radiation,
termed as photo-polymerization. Typical sensitizers are carbonyl compounds, Benzoin,
Benzoyl peroxide, Benzoyl disulphide, nitrogen compounds and halogen compounds.
The solvents used to keep the polymers in solution are mixture of organic liquids. They
include aliphetic esters such as butyl acetate and cellosolve acetate, aromatic hydrocarbons
like xylene and Ethylbenzene, chlorinated hydrocarbons like chlorobenzene and methylene
chloride and ketones such as cyclohexanone. The same solvents are used as thinners and
developers.
Characteristics of Good Photoresist
To achieve faithful registration of the mask geometry over the substrate surface, the resist
should satisfy following conditions.
• Uniform film formation
• Good adhesion to the substrate
• Resolution
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VLSI DESIGN
• Resistance to wet and dry etch processes
Types of Photoresist
Polymers film is either photosensitive or capable or reacting with the pholysis product of
additional compound so that the solubility increases or decreases greatly by exposure to UV
(ultra-violet) radiation. According to the changes that take place, photoresists are termed
negative or positive. Materials which are rendered less soluble in a developer solution by
illumination^ yield a negative pattern of the mask and are called negative photoresists.
Conversely, positive photoresists become more soluble when subjected to light and therefore
yield a positive image of the mask.
Negative Photoresist
Kodak negative photoresist contain polyvinyl cinnametes. KPR is being used in printing
circuit boards. KTFR is widely used in fabrication of ICs. It provides good adhesion to
silicon dioxide and metal surfaces. It gives well etch results to different etchant solutions. For
finer resolution, thinner coating of KTFR is used. To achieve controlled and uniform
thickness, the viscosity of resist is suitably lowered using thinners.
Another negative photoresist is Kodak Microneg 747 which provides high scan speeds at
high aperature giving high throughput and resolution.
Positive Photoresist
Positive Photoresists have solved the problem of resolution and substrate protection. Photo
resists can be used at a coating thickness of 1 micro meter that eliminates holes and
minimises defects from dust.
Positive photoresist is inherently of low solubility (polymerized) material. The base polymer
is active by itself. A sensitizer, when absorbs light, makes the base resist soluble in an alkali
developer. Positive photoresists are Novolac resins. Typical solvents are cellosolve acetate,
butyl acetate, xylene and toluene.
Resist requirements for VLSI
For fine line geometries in VLSI circuits, the resist requirements become more stringent. The
resist properties should meet the required demand of high resolution. Here the resist should
exhibit
• High sensitivity for partial exposure tool chosen
• Dry developing, dry compatibility
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VLSI DESIGN
• Vertical profile control
Photomask Fabrication
Photolithography is used to produce windows in the oxide layer of the silicon wafer, through
which diffusion can take place. For this purpose photomask is required. In this section we
shall discuss various techniques of mask fabrication. The pattern appearing on the mask is
required to be transferred to the wafer. For this purpose various exposure techniques are
employed. We will also discuss these techniques.
Mask Making
IC fabrication is done by the batch processing, where many copies of the same circuit are
fabricated on a single wafer and many wafers are fabricated at the same time. The number of
wafers processed at one time is called the lot size and many vary between 20 to 200 wafers.
Since each IC chip is square and the wafer is circular, the number of chips per wafer is the
number of complete squares of a given size that can fit inside a circle.
The pattern for the mask is designed from the circuit layout. Many years ago, bread boarding
of the circuit was typical. In this, the circuit was actually built and tested with discrete
components before its integration. At present, however, when LSI and VLSI circuits contain
from a thousand to several hundred thousand components, and switching speeds are of such
high order where propagation delay time between devices is significant, bread boarding is
obviously not practical. Present-day mask layout is done with the help of computer.
The photographic mask determines the location of all windows in the oxide layer, and hence
areas over which a particular diffusion step is effective. Each complete mask consists of a
photographic plate on which each window is represented by an opaque are, the remainder
being transparent. Each complete mask will not only include all the windows for the
production of one stage of a particular IC, but in addition, all similar areas for all such
circuits on the entire silicon as shown in the figure below.
It will be obvious that a different mask is required for each stage in the production of an array
of IC’s on a wafer. There is also a vital requirement for precise registration between one
mask and the other in series, to ensure that there is no overlap between components, and that
each section of a particular transistor is formed in precisely the correct location.
To make a mask for one of the production stages, a master is first prepared which is an exact
replica of that portion of the final mask associated with one individual integrated circuit, but
which is 250x [say] enlargement of the final size of IC. The figure below shows a possible
master for the production of a mask to define a particular layer of diffusion for a hypothetical
circuit. Art work at enlarge size avoids large tolerance errors. Large size also permits the art
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VLSI DESIGN
work to be dealt easily by human operator. In the design of the art work, the locations of all
components that is, resistor, capacitor, diode, transistor and so on, are determined on the
surface of the chip. Therefore, six or more layout drawings are required. Each drawing shows
the position of Windows that are required for a particular step of the fabrication. For complex
circuit the layout is generated by the use of computer-aided graphics.
Photomask Fabrication
The master, typically of order 1 m x 1 m, is prepared from cut and strip plastic material which
consists of two plastic films, one photographically opaque called Rubilith and the other
transparent [mylar], which are laminated together. The outline of the pattern required is cut in
the red coating of Rubilith (which is opaque) using a machine controlled cutter on an
illuminated drafting table. The opaque film is then peeled off to reveal transparent areas, each
representing a window region in die final mask.
The next step is to photograph the master using back illumination, to produce a 25 x reduced
sub-master plate. This plate is used in a step and repeat camera which serves the dual purpose
of reducing the pattern by a further 10 x to finished size and is also capable of being stepped
mechanically to produce an array of identical patterns on the final master mask, each member
of the many corresponding to one complete IC. Instead of the photographic plate being
transported mechanically in discrete steps, better accuracy may be achieved by using
continuous plate movement; discrete exposures then being made by an electronically
synchronized flash lamp which effectively freezes the motion.
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VLSI DESIGN
The entire sequence just described can be done with plates containing a photosensitive
emulsion; typically the emulsion is considered too vulnerable to abrasion and tears. For this
reason, masks are often made of harder materials such as chrome or iron oxide.
For very complex circuits automated mask generation equipment is used. In this, a computer
controlled light flashes to build up the pattern on a photographic film by a series of line or
block exposures, the resulting film is then reduced and handled in a step and repeat system to
create the production mask. Alternatively, the master mask can be generated by an electron
beam exposure system, again controlled by computer.
Various Printing Techniques
Photolithography comprises the formation of images with visible or U V radiation in a
photoresist using contact proximity, or projection printing. Here we will discuss about these
printing techniques.
1. Contact Printing
In this printing technique, the photomask is pressed against the resist coated wafer with a
pressure typically in the range of 0.05 atm to 0.3 atm and exposure by light of wavelength
near 400 micro meters. A resolution of less than 1 micro meter linewidth is possible, but it
may vary across the wafer because of spatial non-uniformity of the contact. To provide better
contact over the whole wafer, a thin (0.2 mm) flexible mask has been used.
2. Proximity Printing
In proximity or shadow printing, there exists a gap between mask and wafer in the range of
20 to 50 micro meters. This has the advantage of longer mask life because there is no contact
between the mask and the wafer. In the proximity printing, the mask and wafer are both
placed in an equipment called a projection aligner. Looking through a microscope, an
operator brings the mask into close proximity [say 10 to 20 micro meters] to the wafer and
properly aligns the wafer and mask using alignment mark on the mask and the wafer. UV
light is then projected through the mask on to the entire resist coated wafer at one time. This
mask that is used is a full wafer x 1 mask. The resolution of this process is a function of the
wavelength of the light source and the distance between the mask and the wafer. Typically,
the resolution of proximity printing is 2 to 4 micro meter and is therefore not suitable for a
process requiring less than a 2 um minimum line width.
3. Projection Printing
In this case the image is actually projected with the help of a system of lenses, onto the wafer.
The mask can be used a large number of times, substantially reducing the mask cost per
wafer. Theoretically a mask can be used an unlimited-number of times, but actual usage is
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VLSI DESIGN
limited to about 100,000 times because the mask must be cleaned due to dust accumulation,
and it is scratched at each cleaning. This is costliest of the conventional systems, however
mask life is good, and resolution obtained is higher than proximity printing together with
large separation between mask and wafer.
Automated Mask Generation
As discussed above, layouts of electronic circuit are drawn on large mylar sheets. They can
also be drawn on a CRT screen by which layouts are stored digitally in a magnetic tape (or
disk). In this case we need to prepare many layouts since each layout represents a pattern on
each mask to be used during fabrication. Since the layouts are to be stored digitally, it is
required to convert the layouts drawn on mylar sheets into digital data. This is performed by a
digitizer with the aid of a computer. Then different portions of each layout are displayed on a
CRT one by one and inspected for further mistakes. After all the corrections have been made,
a reticle, which is a small photographic plate of the layout image, is prepared from each
layout stored on the magnetic tape.
Depending upon the type of equipment used, the mask to be fabricated contains one IC chip
pattern which is repeated as many times as there are on the wafer. Alternatively, the mask
consists of only magnified chip pattern as shown in the figure below.
Automated Mask generation
The two most common approaches to automated mask making or generation are
• Using optical projection and
• Using electron beam
A pattern generator (PG) tape is used as the Input to both approaches. The PG tape, contains
the digitized data necessary to control the light source or electron beam that is used to write a
pattern on a photosensitive glass plate. An Ax10 pattern for a single chip (called a x10
reticle) is first produced. This reticle is then photo enlarged by a factor of 15, yielding x 150
41

VLSI DESIGN
blowback, which is used for visual checking. A x 1 mask of the type shown in the figure is
then produced from the x 10 reticle by optical reduction and projection onto a second
photosensitive plate. The same pattern is stepped and repeated on this plate as many as there
are chips on the wafer. This step and repat operation is performed by photo repeater. The
glass plate is then developed yielding a x 1 mask which is called a master mask and looks like
a tile floor where each rectangular tile has the same layout image of the chp. During the step
and repeat process the position and angle of the reticle are precisely aligned with the help of
two fiducial marks incorporated in the PG files of all layouts in the same relative position
with respect to the entire chip. The master mask plate is then placed in close proximity to the
wafer and optically projected on to a resist-coated wafer during the lithographic process.
The figure below shows the second approach. This employs electron-beam mask generation
equipment winch generates the mask plate in one step. The layout data are converted into a
hit map of 1’s and 0′s on a raster image. The electron beam sweeps the row in a repeating S
pattern, blanking or unblanking the beam according to the input bit value, 0 or 1. In the
figure, the x10 reticle is optically reduced and stepped directly onto the wafer. This is
referred to as direct-step on wafer (DSW) lithography.
Automated Mask Generation Process
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VLSI DESIGN
The main advantage of electron-beam pattern generator is speed in the case of complex chips.
A large, dense chip can require 20 hours or more of optical pattern generator time, but only
two hours or less of electron-beam pattern generator time.
Electron-Beam Lithography
Electron-beam lithography provides better resolution then photolithography. This is
possible because of small wavelength of the 10-50 KeV electrons. The resolution of electron-
beam lithography system is not limited by diffraction, but by electron scattering in the resist
and by the various aberrations of the electron optics. The electron-beam exposure system
(EBES) machine has proved to be the best photomask pattern generator. However, the pattern
writing is in serial form. Therefore, the throughput is much less than for optical systems. In
the earlier years of development, electron-beam lithography was employed in the production
of low-volume integrated circuits.
Resists
There is a formation of bonds or cross-links between polymer chains when negative resist is
exposed to electron beam. However, bond breaking occurs in positive resist when it is
exposed. The electron-beam induced cross-links between molecules of negative resist make
the polymer less soluble in the developer solution. Resist sensitivity increases with increasing
molecular weight. In positive resist the bond breaking process predominates. Thus exposure
leads to lower molecular weight and greater solubility.
The polymer molecules in the unexposed resist will have a distribution of length or molecular
weight and thus a distribution of sensitivities to radiation.
The narrower the distribution, the higher will be the contrast. High molecular weight and
narrow distribution are advantageous.
The resist resolution is limited by swelling of the resist in the developer and electron
scattering. Swelling is of more concern for the negative resist and this occurs in all types of
lithography, that is, optical, electron, or X-ray. Swelling leads to poor adhesion of resist to the
substrate. This problem becomes less severe as resist thickness is reduced.
There is also a fundamental process limitation on resolution. When electrons are incident on a
resist or other material, they inter the material and lose energy by scattering, thus producing
secondary electrons and X-rays. This limits the resolution to an extent that depends on resist
thickness, beam energy, and substrate composition.
For thinner resist layers the resolution is better. Minimum thickness, however, is set by the
need to keep defect density low and by resistance to etching as used while device processing.
For photomasks where the surface is fiat and only a thin layer of chrome must be etched with
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VLSI DESIGN
a liquid etchant, resist thickness in the range of 0.2 to 0.4 micro meters are used. In case of
more severe dry gas plasma etching process employed, thickness of 0.5 micro meters to 2
micro meters are required. One way to overcome this problem is to use a multilayer resist
structure in which the thick bottom layer consists of the process-resistant polymer. A three-
layer resist structure may be used in which the uppermost layer is used to pattern a thin
intermediate layer, such as SiO2 which serves as a mask for etching the thick polymer below.
For electron lithography a conducting layer can be substituted for the SiO2 layer to prevent
charge build-up that can lead to beam placement errors.
Multilayer resist structure also alleviates the problem of proximity effect encountered during
electron-beam exposure. In this, an exposed pattern element adjacent to another element
receives exposure not only from the incident electron beam but also from scattered electrons
from the adjacent elements. A two- layer resist structure is also used. In such structure, both
the thin upper and the thick lower layer are positive electron resist, but they are developed in
different solvents. The thick layer can be overdeveloped to provide the undercut profile that
is ideal for lift-off process.
Electron Optics
The first widespread use of electron-beam pattern generators has been in photomask making
as discussed in previous section. The EBES machine, as stated earlier, has proved to be the
best photomask pattern generator. Scanning electron-beam pattern generators are similar to
scanning electron microscopes, from which they are derived. A basic probe-forming electron
optical system may consist of two or more magnetic lenses and provisions for scanning the
image and blanking the beam on the wafer image plane. Typical image spot sizes are in the
range from 0.1 to 2 micro meters. This is for from the diffraction limits. Hence diffraction
can be ignored. However, abberations of the final lens and of the deflection system will
increase the size of the spot and can change its shape as well.
Electron Projection Printing
Electron projection system provides high resolution over a large field with high throughput.
Rather than a small beam writing the pattern in serial fashion, a large beam provides parallel
exposure of large area pattern. In a 1:1 projection system parallel electric and magnetic fields
image electrons onto the wafer. The mask is of quartz and is patterned with chrome. It is
covered with CsI on the side facing the wafer. Photoelectrons are generated on the
mask/cathode by backside UV illumination.
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VLSI DESIGN
The advantages of the projection system are stable mask, good resolution, fast step-repeat
exposure with low sensitivity electron resists, large field, and fast alignment. The limitations
of the system include proximity effects of electrons and shorter life of cathode.
Electron Proximity Printing
This is a step-repeat system in which a silicon membrane stencil mask containing one chip
pattern is shadow printed onto the wafer. The mask cannot accommodate re-entrant
geometries. Registration is accomplished by reference to alignment mask on each chip. An
advantage of electron proximity printing is its ability to measure and compensate for mask
distortions. Proximity effects must be treated by changing the size of pattern elements. The
main limitation of the system is the need for two masks for each pattern.
X-Ray Lithography
The photolithography has its resolution limited by diffraction effects. To improve the
resolution, therefore, the diffraction effects are reduced by reducing the wavelength.
However, if the wavelength is reduced further, all optical materials become opaque because
of the fundamental absorption, but transmission increases again in the X-ray region. This led
to the requirement of X-rays for lithography purpose.
In X-ray lithography an X-ray source illuminates a mask, which casts shadows on to a resist-
covered wafer. The mask and resist material for X-ray lithography are mainly determined by
the absorption spectra of these materials in the X-ray region.
X-Ray Resist
An electron resist can also be referred to as an X-ray resist, since an X-ray resist is exposed
largely by the photoelectrons produced during X-ray absorption. The energies of these
photoelectrons are much smaller than the 10 keV to 50 keV energies used in electron
lithography, making proximity effects negligible in the case of X-ray and promising higher
ultimate resolution.
Most of the polymer resists containing only H, C, and 0, absorb very small X-ray flux. This
small absorption has the advantage of providing uniform exposure throughout the resist
thickness and the disadvantage of reduced sensitivity. .
As in optical and election lithography, the negative resists are limited in resolution by
swelling during development. Thus minimum features of only 0.75 micro meters can be
resolved in a commercial resist.
Proximity Printing
Since the wavelength of X-ray is small, diffraction effects can be ignored and simple
geometrical considerations can be used in relating the image to the pattern on the mask. The
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VLSI DESIGN
opaque parts of the mask cast shadows on to the wafer below. The edge of the shadow is not
absolutely sharp because of the finite diameter of the focal spot of the electrons on the anode
[X-ray source] at a finite distance from the mask. The blurring of shadow can be evaded by
the following equation.
∂ = Sg/D
Where ∂ = blur
g = gap between mask and the wafer
D = Distance of source from the mask
X-Ray Lithography
The various factors contributing to total registration error in X-ray lithography are machine
imprecision and mask stacking errors due to placement errors of pattern generator] and mask
distortion. Wafer process related contributions also have a role in the total registration error.
X-Ray Sources
In earlier years of development X-ray sources was often an electron beam evaporator with its
chamber modified to accept a mask and wafer. The target metal could be changed easily to
modify the X-ray spectrum. X-ray generation by electron bombardment is a very inefficient
process. Most of the input power is converted into heat in the target. The X-ray flux is
generally limited by the heat dissipation in the target. Much high X-ray fluxes are available
from generators which have high speed targets. Another type of source, which provides still
greater amount of flux, is the plasma discharge source in which the plasma is heated to a
temperature high enough to produce X-radiation. The plasma chamber has problems such as
reliability and contaminations.
X-Ray Masks
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VLSI DESIGN
The mask for X-ray lithography consists of an absorber on a transmissive membrane
substrate. The absorber is usually gold which is a heavy metal. Also it can be easily
patterned. The transmissive membrane substrate is a polymer such as polymide and
polyethylene terephthalate.
Chemical Vapor Deposition (CVD)
Chemical Vapor Deposition (CVD) is the deposition of a solid material onto a heated
substrate through decomposition or chemical reaction of compounds contained in the gas
passing over the substrate. Many materials such as, silicon nitri- anjude, silicon dioxide, non-
crystalline silicon, and single crystal silicon, can be deposited through CVD method.
In CVD process, a reaction chamber is introduced in which the materials to be deposited are
passed through. These materials should be in the gaseous or vapor phase and react on or near
the surface of the substrates, which are at some elevated temperature. This produces a
chemical reaction and forms atoms or molecules that are to be deposited on entire substrate
surface.
Chemical Vapor Deposition is used for deposition of poly silicon, silicon dioxide, and
silicon nitride.
The most common deposition methods are
• Atmospheric-pressure chemical vapor deposition (APCVD)
• Low-pressure chemical vapor deposition (LPCVD), and
• Plasma-enhanced chemical vapor deposition (PECVD) or plasma deposition
In earlier years, dielectric and poly-silicon films have been deposited at atmospheric pressure
with the use of different types of reactors. But the use of such Atmospheric-Pressure
Reactors have caused problems like low wafer throughput, and also require excessive wafer
handling during loading and unloading, and provide non-uniformity in thickness. As time
passed by, they have been replaced by low-pressure, hot-wall reactors. Plasma assisted
depositions in hot-wall reactors or with parallel-plate geometries are also available for
application that require low sample temperatures,(100 to 350°C). The major advantages of
low-pressure CVD processes are
• Uniform step coverage
• Precise control of composition and structure
• Low temperature processing
• Fast deposition rates
• High throughput
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VLSI DESIGN
• Low processing costs
The figure below shows the four reactors commonly used for deposition.
Cvd Reactors
Diagram [a] shows an LPCVD reactor that is used to deposit polysilicon, silicon dioxide, and
silicon nitride. The reactor consists of a quartz tube heated by a three-zone furnace. Te gas is
introduced through one end of the furnace and pumped out f the other. The pressures inside
the reaction chambers vary from 30 to 250 Pa, with a temperature range between 300 and 900
degree Celsius. Wafers are kept in a quartz holder and are kept to stand in the vertical
position, and perpendicular to the gas flow. In special cases, special insert are used so as to
bring a drastic change in the dynamics of the gas flow. Such a reactor can easily hold 150
millimeters diameter wafers. Each run processes 50 to 200 wafers with thickness uniformities
of the deposited films within ±5%.
Advantages – LPCVD Reactor
• Excellent uniformity,
• Large load size
• Ability to accommodate large diameter wafers
Disadvantages – LPCVD Reactor
• Low deposition rate
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VLSI DESIGN
• Frequent use of toxic corrosive or flammable gases
An APCVD reactor is shown in diagram [b]. This reactor is used to deposit silicon dioxide.
The samples reach the reactor through a conveyor belt. Due to the high speed flow of
nitrogen, gas curtains are formed which cover the reactant gases flowing through the centre
of the reactor. The samples are heated by convection. The advantages and disadvantages of
APCVD reactors are as follows.
Advantages – APCVD Reactor
• High throughput
• Good uniformity
• Ability to handle large diameter wafers
Disadvantages – APCVD Reactor
• Fast gas flows are required, and
• Reactors must be cleaned frequently
Diagram [c] shows a Plasma-Enhanced CVD (PECVD) or Plasma Deposition Reactor
which is a radial-flow, parallel-plate type. The reaction chamber is a cylinder, usually glass
or aluminium, with aluminium, plates on the top and bottom. Samples lie on the grounded
bottom electrode. An RF voltage is supplied to the top electrode so as to create a glow
discharge between the two plates. This causes the gases to flow radially through the
discharge. These gases begin at the outer edge and take the direction towards the centre. But,
if needed the pattern of the flow can also be reversed. Resistance heaters or high-intensity
lamps heat the bottom, grounded electrode to a temperature between 100 and 400°C. Due to
its low temperature deposition, this reactor finds its application in the plasma-enhanced
deposition of silicon dioxide and silicon nitride.
Disadvantages – Plasma Deposition Reactor
• Capacity is limited, especially for large diameter wafers
• Wafers must be loaded and unloaded individually
• Wafers may be contaminated by loose adhering deposits falling on them
Diagram [d] shows a PECVD or plasma deposition reactor of Hot-Wall Type. This reactor
will help in solving most of the problems that occurred in radial-flow reactor. The reaction
takes place in a quartz tube heated by a furnace. The samples should be held vertically, and
that too parallel to the gas flow. The samples should be supported with the help of materials
like long graphite or aluminium slabs, kept in the electrode assembly. A discharge is
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VLSI DESIGN
produced in the space between the electrodes. This discharge is produced by the alternating
slabs that are connected to the power supply.
Advantages – Hot-Wall Type
• High capacity
• Low deposition temperature
Disadvantages – Hot-Wall Type
• Particles can be formed while the electrode assembly is being inserted
• Wafers must be individually handled during loading and unloading
Epitaxy
Epitaxy is referred to as an arrangement of atoms in a crystal form upon a crystal substrate, so
that the resulting added layer structure is an exact extension of the substrate crystal structure.
In other words, deposited atoms arrange themselves along existing planes of the crystalline
substrate material. This will cause the deposited atoms to bond to the parent atoms to form an
unbroken chain of the crystal structure. The structure of the grown epitaxial layer is thus a
continuation of that single-crystal substrate. A special method in CVD, called Epitaxy or
Epitaxial Layer Deposition or Vapor-Phase Epitaxy (VPE), has only a single-crystal form as
the deposited layer
• Silicon epitaxial layer on a single-crystal silicon substrate (homoepitaxy or commonly
referred to as epitaxy).
• Silicon epitaxial layer deposition on a sapphire (Heteroepitaxy).
Epitaxy and Crystal Growing
There is no difference between epitaxy and crystal growing technique. But where, in epitaxy
a thin film of single crystal silicon is grown from a vapor phase upon a existing single crystal
of the same material, in crystal growing, a single crystal is grown from the liquid phase, in
contrast to the growth technique in epitaxy. Furthermore, epitaxial process involves no
portion of the system at a temperature anywhere near the melting point of the material.
Epitaxial deposition was the initial form in which CVD was used in IC fabrication, and it
continues to play a very important role
Uses of Epitaxy
Epitaxy was first developed so as to improve the performance of discrete bipolar transistors.
The breakdown voltage of the collector was determined by fabricating the devices in bulk
wafers using the wafer’s resistivity to determine the breakdown voltage of the collector.
However, high breakdown voltages need high-resistivity material. This requirement, coupled
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VLSI DESIGN
with the thickness of the wafer, results in excessive collector resistance that limits high-
frequency response and increases power dissipation. Epitaxial growth of a high resistivity
layer on a low-resistivity substrate solves this problem.
Epitaxy is also used to improve the performance of dynamic random-access memory devices
and CMOS ICs.
Epitaxial wafers have two basic advantages over bulk wafers:
• Epitaxial layers make it possible to control the doping profile in a device structure that
available with diffusion or ion implantation.
• The physical properties of lire epi-layer differ from those of bulk material. For
example, epi -layers are generally oxygen and carbon free, a situation not obtained
with the crystal grown silicon.
The most common example of epitaxy is the deposition of silicon epitaxial layer on a single-
crystal silicon substrate. In this case the substrate and layer materials are the same, and this is
called homoepitaxy. Here the epi-layer becomes a crystallographic continuation of the
substrate.
The CVD of single-crystal silicon is usually performed in a reader consisting of a quartz
reaction chamber into which a susceptor is placed. The susceptor provides physical support
for the substrate wafers and provides a more uniform thermal environment. Deposition occurs
at a high temperature at which several chemical reactions take place when process gases flow
into the chamber.
Epitaxial Growth of Silicon
There are a number of different chemical reactions that can be used for the deposition of
epitaxial layers. Four silicon sources have been used for growing epitaxial silicon. These are
silicon tetrachloride [SiCl4], dichlorosilane [SiH2Cl2], trichlorosilane [SiHCl3] and silane
[SiH4].
Silicon tetrachloride has been the most studied and has seen the widest industrial use. The
overall reaction can be classed as a hydrogen reduction of a gas.
SiCl4 [gas] + 2H2 [gas] = Si [solid] + 4HCl [gas]
For understanding the above reaction, we should determine for the Si – CI – H system the
equilibrium constant for each possible reaction and the partial pressure of each gaseous
species at the temperature of interest. Equilibrium calculations reveal fourteen species to be
in equilibrium with solid silicon. In practice many of the species can be ignored because their
partial pressures are less than 10-6
atm.
Doping and Autodoping
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The considerations applied to epitaxial growth process are also applicable to doping. Typical
hydrides of the impurity atoms are used as the source of dopant. Typical reaction for arsenic
dopant is as below
• 2AsH3(gas) = 2As[solid] + 3H2 [gas] = 2As (solid) = 2As+
[solid] + 2e
The hydride AsH3 does not decompose spontaneously as it is relatively stable because of the
large volume of hydrogen present in the reaction. Interactions also take place between the
doping process and the growth process. In addition to intentional dopants incorporated into
the layer, unintentional dopants are introduced from the substrate. This effect is termed
autodoping. Autodoping limits the minimum layer thickness that can be grown with
controlled doping as well as the minimum doping level.
Epitaxial Reactors
The epitaxial layer deposition takes place in a chamber called an epitaxial reactor. There are
three basic types of reactors.
• Horizontal Reactor
• Vertical Reactor and
• Cylindrical Reactor
The three reactors have been explained in the figure below.
Epitaxial Reactors
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VLSI DESIGN
Horizontal reactors offer lowest cost construction, however, controlling the deposition
process over the entire susceptor length is a problem. Vertical reactors are capable of very
uniform deposition but suffer from mechanical complexity. Cylindrical reactors are also
capable of uniform deposition due to employment of radiant heating, but arc not suited for
extended operation at temperature above 1200°C.
Epitaxial Growth Process
A typical epitaxial growth process includes several steps as follows.
• A hydrogen carrier gas is used to purge the reactor of air.
• The reactor is then heated to a temperature.
• After thermal equilibrium is established in the chamber, anhydrous HCl gas is fed into
the reactor. The HCl gas reacts with the silicon at the surface of wafers in reaction
that is reverse of that given for [SiCl4+H2].This reverse reaction results in vapor-
phase-etching of the silicon surface and usually occurs at a temperature between 1150
and 1200°C for 3 min.
• The temperature is then reduced to the growth temperature with time allowed for
stabilizing the temperature and flushing the HCI gas. For [SiCI2 +H2] reaction, the
graphite boat is heated to a temperature in the range 1150 – 1250 degree Celsius. The
vapor of SiCl4 and hydrogen as a carrier gas arc introduced into the lube for producing
epitaxial layer.
• Once growth is complete, the dopant and silicon flows are eliminated and the
temperature reduced, usually by shutting of the power.
• As the reactor cools toward ambient temperature, the hydrogen flow is replaced by a
nitrogen flow so that the reactor may be opened safely.
Depending on wafer diameter and reactor type, capacities range from 10 to 15 wafer per
batch. Process cycle times are about 1 hour. The vapor-phase etching (VPE) described above
is necessary to remove a small amount of Si and other contaminants from the wafer surfaces
to ensure that a clear freshly etched silicon surface will be available for epitaxial layer
deposition. When the concentration of SiCI4, is high, etching can still occur even when
hydrogen chloride is not present due to a competing interaction.
SiC4 + Si = 2SiCl2
Thus, the growth rate of epitaxial silicon, which will be negative if etching occurs. It is
critically dependent on the concentration of silicon chloride as well as the temperature. In
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VLSI DESIGN
typical environmental conditions for growth, at a rate of around 1 micro meter per min,
produces layers which are well within the region for single-crystal epitaxy
When reduction of SiC4 lakes place, the reaction gives rise to free silicon atoms. Atoms from
the gas phase skid about on the surface of the growing epitaxial film until they find correct
position in the lattice before becoming fastened into the growing structure.
For producing doped p-type or n-type epitaxial layers, a number of gases can be metered into
the reactor tube, including some very small amounts of doping gases, such as B2H6
[diborane] for boron doping and PH3 [phosphine] for phosphorus doping of the epitaxial
layer. During the epitaxial layer deposition the dopant gas molecules react and become
decomposed and the dopant atoms thus produced become incorporated into the epitaxial
layer. Doping of the epitaxial layer is also achieved by adding controlled amounts of-the
appropriate impurity in liquid form, for example, phosphorus trichloride or arsenic
trichloride, to the silicon chloride.
The main advantages and disadvantages of SiCl4 as a source of Si epitaxy are as follows:
Advantages
• SiCl4 is non-toxic, inexpensive and easy to purify.
• The reaction making silicon from SiCl4 takes place only at surface and not on the
boat or reaction chamber walls.
Disadvantages
• The growth process is accompanied by the diffusion phenomenon which causes an
exchange of impurities between silicon wafer and growing Film. This prevents the
fabrication of an ideal step junction.
• SiCl4 process requires higher temperature than silane process and also has slower
growth rate.
Problems in Growing Impurity Doped Epitaxial Layers
Epitaxial layer deposition takes place at temperatures in the range 950 to 1250°C. Due to this,
diffusion of impurities may occur across the epitaxial layer or substrate interface due to the
deposition and high temperature processing steps. This will cause a blurring of the impurity
profile in the region of this interface. But the main problem will be the deposition of a very
thin and very lightly doped epitaxial layer on a very heavily doped substrate. The
outdiffusion of impurities from the heavily doped substrate into the lightly doped epitaxial
layer will blot out the sharp n/n+
transition that would otherwise be present at the layer-
substrate interface. The influx of donor atoms from the substrate will reduce the effective
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VLSI DESIGN
thickness of the lightly doped epitaxial layer by 1 or 2 micro meter. To minimize this
problem of outdiffusion from heavily doped n+
substrate, slow donor diffusants such as
antimony and arsenic are often used for the doping of substrate in preference to phosphorus.
Molecular Beam Epitaxy (MBE)
Molecular beam epitaxy differs from vapor-phase epitaxy (VPE) in that it employs
evaporation t [instead of deposition] method. Thus it is a non-CVD epitaxial process.
Although the method has been known since the early 1960s, it has recently been considered a
suitable technology for silicon device fabrication. In the MBE process the silicon along with
dopants is evaporated. The evaporated species are transported at a relatively high velocity in
a vacuum to the substrate.
The relatively low vapor pressure of silicon and the dopants ensures condensation on a low-
temperature substrate. Usually, silicon MBE is performed under ultra-high vacuum [UHV]
conditions of 10-8
to l0-16
Torr.
The two major reasons why MBE was not used were in earlier years were that the quality was
not commensurate with device needs and that no industrial equipment existed. Equipments
are now available, but the process has low throughput and is expensive. MBE, however, does
have a number of inherent advantages over CVD techniques:
• It is a low temperature process. Thus outdiffusion and autodoping is minimized.
• It allows precise control of doping and permits complicated doping profiles in he
generated, This is useful for discrete microwave devices.
• A linear voltage -capacitance relationship is desired for varactor diodes used in FM
modulators. For this linear doping profile is required, which is easily obtained with
MBE.
Metallization Process
Metallization is the final step in the wafer processing sequence. Metallization is the process
by which the components of IC’s are interconnected by aluminium conductor. This process
produces a thin-film metal layer that will serve as the required conductor pattern for the
interconnection of the various components on the chip. Another use of metallization is to
produce metalized areas called bonding pads around the periphery of the chip to produce
metalized areas for the bonding of wire leads from the package to the chip. The bonding
wires are typically 25 micro meters diameter gold wires, and the bonding pads are usually
made to be around 100×100 micro meters square to accommodate fully the flattened ends of
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VLSI DESIGN
the bonding wires and to allow for some registration errors in the placement of the wires on
the pads.
Aluminium
Aluminium (At) is the most commonly used material for the metallization of most IC’s,
discrete diodes, and transistors. The film thickness is as about 1 micro meters and conductor
widths of about 2 to 25 micro meters are commonly used. The use of aluminium offers the
following advantages:
• It has as relatively good conductivity.
• It is easy to deposit thin films of Al by vacuum evaporation.
• It has good adherence to the silicon dioxide surface.
• Aluminium forms good mechanical bonds with silicon by sintering at about 500°C or
by alloying at the eutectic temperature of 577°C.
• Aluminium forms low-resistance, non-rectifying (that is, ohmic) contacts with p-type
silicon and with heavily doped n-type silicon.
• It can be applied and patterned with a single deposition and etching process.
Aluminium has certain limitations:
1. During packaging operation if temperature goes too high, say 600°C, or if there is
overheating due to current surge, Al can fuse and can penetrate through the oxide to
the silicon and may cause short circuit in the connection. By providing, adequate
process control and testing, such failures can be minimized.
2. The silicon chip is usually mounted in the package by a gold perform or die backing
that alloys with the silicon. Gold lead wires have been bonded to the aluminium film
bonding pads on the chip, since package lead are usually gold plated. At elevated
temperatures, a reaction between the metal of such systems causes formation of
intermetallic compounds, known as the purple plague. Purple plague is one of six
phases that can occur when gold and aluminium inter-diffuse. Because of dissimilar
rate of diffusion of gold and aluminium, voids normally occur in the form of the
purple plague. These voids may result in weakened bonds, resistive bonds or
catastrophic failure. The problem is generally solved by using aluminium lead wires,
or another metal system, in circuits that will be subjected so elevated temperatures.
One method is to deposit gold over an under layer of chromium. The chromium acts
as a diffusion barrier to the gold and also adheres well to both oxide and gold. Gold
has poor adhesion to oxide because it does not oxide itself. However, the chromium-
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VLSI DESIGN
gold process is comparatively expensive, and it has an uncontrollable reaction with
silicon during alloying.
3. Aluminium suffers from electromigration which can cause considerable material
transport in metals. It occurs because of the enhanced and directional mobility of
atoms caused by the direct influence of the electric field and the collision of electrons
with atoms, which leads to momentum transfer. In thin-film conductors that carry
sufficient current density during device operations, the mode of material transport can
occur at much lower temperature (compared to bulk metals) because of the presence
of grain boundaries, dislocations and point defects that aid the material transport.
Eecctromigration-induced failure is the most important mode of failure in Al lines.
In general the desired properties of the metallization for IC can be listed as follows.
• Low resistivity.
• Easy to form.
• Easy to etch for pattern generation.
• Should be stable in oxidizing ambient , oxidizable.
• Mechanical stability; good adherence, low stress.
• Surface smoothness.
• Stability throughout processing including high temperature sinter, dry or wet
oxidation, gettering, phosphorous glass (or any other material) passivation,
metallization.
• No reaction with final metal, aluminium.
• Should not contaminate device, wafers, or working apparatus.
• Good device characteristics and life times.
• For window contacts-low contact resistance, minimum junction penetration, low
electromigration.
Metallization Application in VLSI
For VLSI, metallization applications can be divided into three groups:
1. Gates for MOSFET
2. Contacts, and
3. Interconnects.
Interconnection metallization interconnects thousands of MOSFETs or bipolar devices using
fine-line metal patterns. It is also same as gate metallization for MOSFET. All metallization
directly in contact with semiconductor is called contact metallization. Polysilicon film is
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VLSI DESIGN
employed in the form of metallization used for gate and interconnection of MOS devices.
Aluminium is used as the contact metal, on devices and as the second-level inter-connection
to the outside world. Several new schemes for metallization have been suggested to produce
ohmic contacts to a semiconductor. In several cases a multiple-layer structure involving a
diffusion barrier has been recommended. Platinum silicide (PtSi) has been used as a Schottky
barrier contact and also simply as an ohmic contact for deep junction.
Titanium/platinum/gold or titanium/palladium/gold beam lead technology has been
successful in providing high-reliability connection to the outside world. The applicability of
any metallization scheme in VLSI depends on several requirements. However, the important
requirements are the stability of the metallization throughout the IC fabrication process and
its reliability during the actual use of the devices.
Ohmic contacts
When a metal is deposited on the semiconductor a good ohmic contact should be formed.
This is possible, if the deposition metal does not perturb device characteristics. Also die
contact should be stable both electrically and mechanically.
Other important application of metallization is the top-level metal that provides a connection
to the outside world. To reduce interconnection resistance and save area on a chip, multilevel
metallization, as discussed in this section is also used. Metallization is also used to produce
rectifying (Schottky barrier) contacts, guard rings, and diffusion barriers between reacting
metallic films.
We have already stated the desired properties of metallization for ICs. None of the metals
satisfies all the desired characteristics. Even Al, which has most of the desired properties
suffers from a low melting point-limitation and electromigration as discussed above.
Poly-silicon has been used for gate metallization, for MOS devices. Recently, poly-
silicon/refractory metal silicide bi-layers have replaced poly-silicon so that lower resistance
an be achieved at the gale and interconnection level. By preserving the use of polysilicon as
the “metal” in contact with the gate oxide, well known device characteristics and processes
have been unaltered. The silicides of molybdenum (MoSi2), tantalum (TaSi2) and tungsten
(WSi2) have been used in the production of microprocessors and random-access memories.
TiSi2 and CoSi2 have been suggested to replace MoSi2, TaSi2, and WSi2. Aluminium and
refractory metals tungsten and Mo are also being considered for the gate metal.
For contacts, Al has been the preferred metal for VLSI. However, for VLSI applications,
several special factors such as shallower junctions, step coverage, electromigration (at higher
current densities), and contact resistance can no longer be ignored. Therefore, several
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VLSI DESIGN
possible solutions to the contact problems in VLSI have been considered. These include use
of
• Dilute Si-Ai alloy.
• Polysilicon layers between source, drain, or gate and top-level Al.
• Selectively deposited tungsten, that is, deposited by CVD methods so that metal is
deposited only on silicon and not on oxide.
• A diffusion barrier layer between silicon and Al, using a silicide, nitride, carbide, or
their combination.
Use of self-aligned silicide, such as, PtSi, guarantees extremely good metallurgical contact
between silicon and silicide. Silicides are also recommended in processes where shallow
junctions and contacts are formed at the same time. The most important requirement of an
effective metallization scheme in VLSI is that metal must adhere to the silicon in the
windows and to the oxide that defines die window. In this respect, metals such as, Al, Ti, Ta,
etc., that form oxides with a heat of formation higher than that of Si02 are the best. This is
why titanium is the most commonly used adhesion promoter.
Although silicides are used for contact metallization, diffusion barrier is required to protect
from interaction with Al which is used as the top metal. Aluminium interacts with most
silicides in the temperature range of 200-500 degree Celsius. Hence transition metal nitrides,
carbides, and borides are used as a diffusion barrier between silicide (or Si) and Al due to
their high chemical stability.
Metallization Processes
Metallisation process can be classified info two types:
1. CVD and
2. Physical Vapour Deposition
CVD offers three important advantages. They are
• Excellent step coverage
• Large throughput
• Low-temperature processing
• The basic physical vapour deposition methods are
• Evaporation
• Sputtering
Both these methods have three identical steps.
• Converting the condensed phase (generally a solid) into a gaseous or vapour phase.
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VLSI DESIGN
• Transporting the gaseous phase from the source to the substrate, and
• Condensing the gaseous source on the substrate.
In both methods the substrate is away from the source.
In cases where a compound, such as silicide, nitride, or carbide, is deposited one of the
components is as gas and the deposition process is termed reactive evaporation or sputtering.
Deposition Methods
In the evaporation method, which is the simplest, a film is deposited by the condensation of
the vapour on the substrate. The substrate is maintained at a lower temperature than that of
the vapour. All metals vaporize when heated to sufficiently high temperatures. Several
methods of heating are employed to attain these temperatures. For AI deposition, resistive,
inductive (RF), electron bombardment [electron-gun] or laser heating can be employed. For
refractory metals, electron-gun is very common. Resistive heating provides low throughput.
Electron-gun cause radiation damage, but by heat treatment it can be annealed out. This
method is advantageous because the evaporations take place at pressure considerably lower
than sputtering pressure. This makes the gas entrapment in the negligible. RF heating of the
evaporating source could prove to be the best compromise in providing large throughput,
clean environment, and minimal levels of radiation damage.
In sputtering deposition method, the target material is bombarded by energetic ions to release
some atoms. These atoms are then condensed on the substrate to form a film. Sputtering,
unlike evaporation is very well controlled and is generally applicable to all materials metals,
alloys, semiconductors and insulators. RF-dc and dc-magnetron sputtering can be used for
metal deposition. Alloy-film deposition by sputtering from an alloy target is possible because
the composition of the film is locked to the composition of the target. This is true even when
there is considerable difference between the sputtering rates of the alloy components. Alloys
can also be deposited with excellent control of composition by use of individual component
targets. In certain cases, the compounds can be deposited by sputtering the metal in a reactive
environment. Thus gases such as methane, ammonia, or nitrogen, and diborane can be used in
the sputtering chamber to deposit carbide, nitride, and boride, respectively. This technique is
called reactive sputtering. Sputtering is carried out at relatively high pressures (0.1 to 1 pascal
or Pa). Because gas ions are the bombarding species, the films usually end up including small
amount of gas. The trapped gases cause stress changes. Sputtering is a physical process in
which the deposited film is also exposed to ion bombardment. Such ion bombardment causes
sputtering damage, which leads to unwanted charges and internal electric fields that affect
device proxies. However such damages can be annealed out at relatively low temperatures
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VLSI DESIGN
(<500°C), unless the damage is so severe as to cause an irreversible breakdown of the gate
dielectric.
Deposition Apparatus
The metallization is usually done in vacuum chambers. A mechanical pump can reduce the
pressure to about 10 to 0.1 Pa. Such pressure may be sufficient for LPCVD. An oil-diffusion
pump can bring the pressure down to 10-5
Pa and with the help of a liquid nitrogen trap as low
as 10-7
Pa. A turbomolecular pump, can bring the pressure down to 10-8
-10-9
Pa. Such pumps
are oil-free and are useful HI molecular-beam epitaxy where oil contamination must be
avoided. Besides the pumping system, pressure gauges and controls, residual gas analyzers,
temperature sensors, ability to clean the surface of the wafers by backsputtering,
contamination control, and gas manifolds, and the use of automation should be evaluated.
As typical high-vacuum evaporation apparatus is shown in the figure below.
The apparatus consists of a hell jar, a stainless-steel cylindrical vessel closed at the top and
sealed at the base by a gasket. Beginning at atmospheric pressure the jar is evacuated by a
roughing pump, such as a mechanical rotary-van pump reducing pressure to about 20 Pa or a
combination mechanical pump and liquid-nitrogen-cooled molecular pump (reducing
pressure lo about 0.5 Pa). At the appropriate pressure, the jar is opened to a high-vacuum
pumping system that continues to reduce the pressure. The high-vacuum, pumping system
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VLSI DESIGN
may consist of a liquid nitrogen-cooled trap and an oil-diffusion pump, a trap and a
turbomolecular pump, or a trap and a closed-cycle helium refrigerator cryopump. The
cryopump acts as a trap and must be regenerated periodically, the turbomolecular and
diffusion pumps act as transfer pumps, expelling their gas t a forepump. The high vacuum
pumping system brings the jar to a low pressure that is tolerable for the deposition process.
All components in the chamber are chemically cleaned and dried. Freedom from sodium
contamination is vital when coating MOS devices.
The sputtering system operates with about 1 Pa of argon pressure during film deposition. For
sputtering, a throttle valve should be placed between the trap and the high-vacuum pumping
system. The argon gas pressure can to be maintained by reducing the effective pumping
speed of the high-vacuum pump, while the full pumping speed of the trap for water vapour is
utilized. Water vapour and oxygen are detrimental to film quality at background pressures of
about 10-2
Pa.
The use of thickness monitors is common in evaporation and sputtering deposition. This is
necessary for controlling the thickness of the film, because thinner film can cause excess
current density and excessive thickness can lead to difficulties in etching.
Metallization Patterning
Once the thin-film metallization has been done the film must be patterned to produce the
required interconnection and bonding pad configuration. This is done by a photolithographic
process of the same type that is used for producing patterns in Si02 layers. Aluminium can be
etched by a number of acid and base solutions including HCl, H3PO4, KOH, and NaOH. The
most commonly used aluminium etchant is phosphoric acid with the addition of small
amounts of HN03 (nitric acid) and acetic acid, to result a moderate etch rate of about 1 micro
meter per minute at 50°C. Plasma etching can also be used with aluminium.
Lift-off Process
The lift-off process is an alternative metallization patterning technique. In this process a
positive photoresist is spun on the wafer and patterned using the standard photolithographic
process. Then the metallization thin film is deposited on top of the remaining photoresist. The
wafers are then immersed in suitable solvent such as acetone and at the same time subjected
to ultrasonic agitation. This causes swelling and dissolution of the photoresist. As the
photoresist comes off it lifts off the metallization on top of it, for the lift-off process to work,
the metallization film thickness must generally be somewhat less than the photoresist
thickness. This process can, however produce a very fine line-width metallization pattern,
even with metallization thickness that are greater than the line width.
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VLSI DESIGN
Pattering for VLSI Applications
VLSI applications require anisotropic etching techniques for metallization patterning because
of the requirements of tight control on metallization dimensions. Therefore dry-etching
techniques are most suitable. Reactive-ion etching (RIE) is anisotropic. Hence it is preferred.
For RIE, reactive gases such as, Cl2 and CCI3F are used, hence the name reactive ion etching.
Packaging
Packaging involves bonding the circuit chips to a header and encapsulating the whole
unit.
A package has 4 basic functions
 To protect sensitive semiconductor device from externl environment that could
degrade circuit performance.
 To provide adequate mechanical protection
 To provide convenient means for interconnectiong many individually packaged
circuits
 Act as a path for heat resulting from power dissipation in IC.
Type of pakage is based on environmental capacity
Comparative interconnecting cost
Comparative package cost
Component density per unit volume.
Comparative system size.
Package types
Three basic types of linear IC packages
 Flat pack
 Metal can or transistor pack
 Dual in line package
Flat pack
 Occupies smallest space.
 Hermetically sealed
 Once fixed in position it cannot be removed from circuit for servicing.
 Typical flat pack is enclosed in rectangular ceramic case with terminal leads
extending through sides and ends.these leads accommodate power
supplies,inputs,ouputs and several special connections required to complete circuit.
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VLSI DESIGN
 To attach package on to PCB welding or resistance soldering is required which might
increase the cost.
Metal can or transistor pack
IC chip is encapsulated in meatl or plastic case .IC chip is bonded to base of can and then
enclosed with metal cap.Leads connected to IC chip are brought from base of packages.Inert
gas is forced into cap prior to sealing.This forces out moisture or corrosive material and chip
surface is protected from contamination.The package is hermetically sealed.
Dual in line packages
IC chip is mounted in a plastic or ceramic case. It was designed to obtain improved solder
ability to PCB. Another advantage is ease with which it is fabricated, resulting in low cost.
Package materials
 Plastic
 Metal
 Ceramic
Plastic
The least expensive package material sucha s epoxy resin.
Provides good mechanical protection.It is not hermetically sealed.
Lack of seal makes it unsuitable for its use in moisture or in corrosive environment.
Lowest thermal dissipation capacity.
Highest thermal resistance.
Metal
Increases hermetical sealing.Isolation of chip allows its use in ambient that would corrode
and melt a plastic chip.
Ceramic
Presents high integrity to extreme surrounding.it can be hermetically sealed.High thermal
dissipation capability of all materials,allowing its us at high temperatures.
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VLSI DESIGN
MODULE 2
Isolation of components (refer written notes)
Once all components are fabricated on a single crystal wafer, they must be electrically
isolated from each other. The problem is not encountered indiscrete circuits, because
physically all components are isolated. There are two methods of isolation in Integrated
circuits. They are
◾P-N junction isolation and
◾Dielectric isolation
PN JUNCTION ISOLATIONThe method of isolation is most compatible with the IC
processing, that is, one extra processing step, other than required to fabricate IC, is required
in isolation. Basically the method involves producing islands of n- type material surrounded
by p-type material. Components are then fabricated in different n-type islands. The p-type
material surrounding the islands is given the most negative p potential with respect to all
parts of the wafer, thus each island and hence component is electrically isolated from the
others by back-to-back diodes. The process step for p-n junction isolation are explained
below:
1. One begins with the p-type substrate on which n-epitaxial layer is grown. If the component
to be fabricated is transistor, then buried layer have to be formed before growing epi-layer.
Figure [a] shows epi-layer growth over substrate without buried layer. The epi-layer is then
covered with SiO2 layer.
2. A p-type diffusion is now performed from the surface of the wafer. Since this is to be
performed in selected areas, an isolation mask is prepared prior to this diffusion. A long
drive-in time is required for p-type diffusion so that the acceptor concentration is greater than
the epi-layer donor concentration throughout the region of epi-layer. Thus the portion of
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VLSI DESIGN
wafer at the location of isolation diffusion is changed to p-type from the surface of wafer to
the substrate. This is shown in the figure [b]. In other words, the substrate is extended toward
the surface and acts as an isolation wall. This isolation wall causes the formation of p-n
junction everywhere around the n-type islands except at the surface. If the substrate is
connected to a voltage which is more negative than any of the n-region voltages, the diodes
shown will be reversed biased and negligible current will flow. Thus isolation is achieved
since any reverse biased p-n junction is associated with a depletion capacitance; this will have
parasitic effect associated with junction, particularly, at high frequencies.
The main disadvantage of p-n junction isolations is as below:
 The time required for such isolation technique is considerably longer due to diffusion
time taken, which is longer than any of other diffusions.
 Lateral diffusion is significant due to longer time taken by isolation diffusion, hence
considerable clearance must be used for isolation regions.
 Isolation diffusion takes an area of the wafer surface which is significant portion of
the chip area. From component density consideration, this area is wasted.
 P-N junction isolation method introduces significant parasitic capacitance which
degrades circuit performance. The parasitic capacitance is introduced by isolation
sidewall and bottom epitaxial substrate junction.
Dielectric Isolation
Dielectric isolation, is the process of electrically isolating various components in the IC chip
from the substrate and from each other by an insulating layer. It’s main use is to eliminate
undesirable parasitic junction capacitance or leakage currents associated with certain
applications.
The various methods of dielectric isolation are:
V-Groove Isolation
V-groove isolation is formed with an n-type substrate, on which an n+ diffusion is performed.
As a next step an SiO2 layer is formed, which is then patterned to form a grid of intersecting
lines opening in the oxide. V-groove isolation process is shown in the figure below.
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VLSI DESIGN
The wafer formed is then exposed to an orientation dependent etching (ODE) process, where
the patterned layer is used as the etching mask; which results in the formation of V-shaped
grooves as shown in the picture (b). In this the <111> plane sidewalls are at an angle of 54.74
degree with respect to the <100> top surface of the silicon wafer.
As a result the starting material is <111> oriented crystal, which is normally used for p-n
junction isolation. But for dielectric isolation the starting material is <100> oriental
silicon.The etchant used in the above step etches away the exposed silicon anisotropically,
this means that the etch rate is much faster along the <111> planes than along the <100>
crystal planes. This kind of preferential etching is the key reason behind the formation of V-
groove. The depth D of the isolation groove can be determined in the initial oxide cut width
W as D = W/√2
Next step is covering the sidewalls of the V-groove with an oxide layer, therefore the wafer is
subjected to a thermal oxidation process. After completing the oxide layer, a very thick layer
of polycrystalline silicon is deposited as shown in picture (c).
The most critical step in the V-groove isolation process is explained in figure (d). Keeping
polycrystalline surface side of the wafer down, silicon wafers are mounted on the lapping
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VLSI DESIGN
plate. In the next step, n-type silicon substrate is then carefully lapped down to the level at
which the vertices of the V-grooves become exposed.So now we get an array of n-type single
crystal silicon regions that are isolated from the polycrystalline silicon substrate.
Polycrystalline silicon now serves to provide the mechanical support for the IC.This material
is ideal for the function because of its good thermal expansion coefficient, it can withstand
high processing temperatures, and is a good match to single crystal silicon.
The n-type silicon has now moved down to vertices of the V-grooves because of the lapping
operation. If the lapping is recessive, then proper isolation will not be achieved.But if
excessive lapping is done, it may lead to thinner n-type regions. Wafer diameter is approx
100mm and the V-groove depth is about 10 micro meters, thus precise lapping is necessary.
The n+ diffused layer serves as a buried layer to reduce the collector series resistance of the
n-p-n transistors The rest of the processing sequence for the dialectically isolated ICs follows
along the same line as for the conventional junction isolated IC.
The dielectric isolation is useful for such applications as high-voltage and radiation-resistant
ICs. This isolation technique is much more expensive than junction isolation technique
because it requires extra processing steps.
Advantage of dielectric isolation:
Excess free electrons and holes created in the silicon as a result of high energy ionisation by
photo radiation causes a large increase in the leakage current of the pn junctions in the IC;
which obviously is undesirable and can cause damage.The dielectric isolation in the IC is
resistant and protects the IC from such large transients.
Below listed are some reasons for the reduced parasitic capacitance:
◾Permittivity of SiO2 is one reason, which is 1/3rd of Silicon and hence capacitance is
reduced.
◾Oxide is thicker than the depletion region of the substrate junction and capacitance is
inversely proportional to the thickness of oxide.
◾No need of applying negetive potential to the substrate.
Silicon-on-lnsulator Technology
It’s another process for creating dielectrically isolated devices. In this process, a thin layer of
single-crystal silicon can be produced on top of a thermal SiO2 layer on a silicon wafer.
Strips of oxide are produced by patterning the oxide layer using photolithography. As a next
step, a thin layer of silicon is then deposited on the wafer.It will be polycrystalline in the
regions where the deposited silicon layer overlays the oxide and it will be single crystal in the
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VLSI DESIGN
regions where there is direct contact with silicon substrate. In the next step we will
directionally recrystalise the silicon layer, which inturn recrystallises the substrate to act as
the nucleation centre.As the heated zone is scanned across the wafer the crystal growth,
propagates from these nucleation regions to the regions of the silicon film on top of the oxide
islands or strips.Thus we form a complete single crystal layer of silicon.
Epitaxial Lateral Overgrowth (ELO)
The Epitaxial Lateral Overgrowth (ELO) is related to Silicon on Insulator process.Like in
SOI process, the starting material is thermally oxidised silicon wafer in which the oxide layer
is patterned to islands or stripes using photolithographic techniques.Next step is a repeated
sequence of carefully controlled CVD silicon deposition, followed vapour phase etching
cycles to produce single crystal silicon film on the silicon substrate.
A preferential removal of polycrystalline silicon (deposited on top of SiO2) happens during
the vapour phase etching process.In the next steps,as successive cycles of the CVD
deposition and vapour-phase etching process continues,the single-crystal silicon that is
formed in the oxide windows starts to extend over the adjoining oxide regions,and at the
same time any polycrystalline silicon that is deposited on top of the oxide is removed by the
vapour-phase etching process.As a result a complete single crystal layer of silicon is formed.
Monolithic Planar Diode Configurations(refer written notes+ class notes)
We have seen that in the fabrication of an IC the geometry and the doping of the various
layers must be chosen to optimize uncharacteristic of the transistor which is the most
important device. It is not economically feasible to provide extra processing steps to fabricate
diodes. Therefore diodes are generally transistor adopted for this operation. There are basic
five configurations of transistor for diode operation as shown in the figure below.
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VLSI DESIGN
A base-collector diode is shown in figure [a]. The emitter is floating and can be omitted. This
diode has a high breakdown voltage of around 50 V. However it has a relatively long
switching time of about 100 nano seconds due to the collector access resistance Rcc, which is
nothing but the resistance between the collector terminal and the effective active region to
which it is connected. (This resistance is reduced by buried layer diffusion).
The switching time can be improved to about 70 nano seconds by shorting the emitter and
base to remove charge stored at that junction, while retaining the high breakdown voltage, as
shown in figure [b].
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VLSI DESIGN
Figure [c] shows the base-emitter junction diode with collector open. The turn-off time, due
mainly to charge stored in the base collector junction is about 80 nano seconds and it has a
low breakdown voltage (associated with the high doped emitter of around 5V.
In above case, the switching time can be reduced to as low as 20 nano seconds, by shorting
base and collector, to remove minority stored charge as shown in figure [d]. The low
breakdown voltage is not affected in this diode.
Figure [e] shows the diode connection where both emitter-base and base-collector junctions
are in parallel. It is obtained by shorting emitter and collector. This diode is not much used
due to high junction capacitance which causes low switching speed of around 150 nano
seconds, together with a poor breakdown voltage of about 5V associated with the base-
emitter junction.
From above discussion we conclude that diodes shown in figure [b] and [d] are most useful,
the former for higher voltage applications, and the latter where switching speed is of
paramount importance. Supply voltage encountered and digital ICs rarely exceed 5 or 6 V,
hence the limitation of low breakdown voltage of diodes shown in figure [d] is not a serious
disadvantage. Further it has the lowest series resistance and no parasitic p-n-p action to the
substrate (which occurs between the substrate and the p-type base, if the collector-base region
of the n-p-n were to become forward biased). Also it has generally the lowest forward voltage
drop for a given forward current, lowest storage time and lowest reverse-bias capacitance.
These all favourable factors make the diode of figure [d] an ideal choice for digital IC’s.
Avalanche Diode
The avalanche breakdown characteristic in a reverse biased diode can be used for voltage
reference or the dc level-shift purposes in IC circuits. The base-emitter breakdown voltage
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VLSI DESIGN
which falls within the 6 to 9 V range is the most commonly used avalanche diode since its
breakdown voltage incompatible with the voltage levels available in analog circuits.
The breakdown voltage of base-emitter junction of above diode exhibits a positive
temperature coefficient, typically in the range of +2 mV/°C to +5 /°C. By connecting a
forward-biased diode in series with avalanche diode, it is possible to partially compensate the
thermal drift of avalanche diode because the thermal drift of forward voltage of the series
connected diode is negative. The composite connection is shown in the figure below which
has breakdown voltage of (VD + BVEB) with significantly reduced temperature coefficient.
Here VD is forward drop of series diode and BVEB is the breakdown voltage (BE junction)
of avalanche diode. As the figure shows, the composite connection consists of two transistors
back-to-back in diode connection. Since both transistors have their collector and base regions
in common, they can be designed as a single transistor with two separate emitters.
Schottky Diode and Transistor
When a metal is placed in close contact with an n-type semiconductor, a voltage barrier is
created, which is known as Schottky Barrier. ln such contact, there are many free electrons in
the metal, whereas the semiconductor contains relatively low. With a positive voltage applied
to the metal, the barrier is overcome and the diode begins conducting. A negative bias
enlarges the barrier, thus the diode blocks conduction. Such diode differs from an ordinary p-
n junction as follows:
The barrier is only half as large as that of a junction diode, at low current, a Schottky diode
has a forward voltage drop of only about 0.3 V to 0.5 V.
Only majority carriers are involved in the conduction mechanism, which make the Schottky
diode a very high speed device with a recovery time less than 1 nano seconds.
The Schottky effect only takes place in relatively high resistivity semiconductor material.
When the semiconductor is heavily doped, a tunnelling effect occurs which provides a direct
ohmic contact.The figure below shows the cross-section view of a typical Schottky diode. It
is formed between the epitaxial layer and the Al deposited for interconnections. The cathode
connection to the epitaxial layer is through a conventional n+ collector contact diffusion, to
ensure a good ohmic contact, but at the anode connection the n+ diffusion is omitted due to
direct ohmic contact provided by Schottky junction. The Schottky barrier is formed between
aluminium and the n-type epitaxial silicon. The advantage of Schottky diode is that it can be
made with existing IC processes. No additional manufacturing steps are required. This is
important from yield point of view.
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VLSI DESIGN
One important application of Schottky diode is Schottky diode clamped transistor is shown in
the figure below. The figure [a] shows circuit symbol and [b] shows the cross-sectional view
of Schottky transistor. The Schottky transistor is used in TTL logic circuits. The Schottky
transistor provides very fast speed operation. This is possible because the Schottky clamp
prevents the transistor from going into saturation. If an attempt is made to saturate this
transistor by increasing the base current, the collector voltage drops, diode D conducts, and
the base-to-collector voltage is limited to about less than 0.5. V. Since the collector junction
is forward-biased by less than the cut-in voltage (0.5 V), the transistor does not enter
saturation.
Schottky Transistor
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VLSI DESIGN
Note that in the figure [b], the aluminium metallization for base lead is allowed to make
contact also with the n-type collector region, but without an intervening n+ layer. This results
in formation of metal semiconductor diode between base and collector. Since the Schottky
junction is formed during the metallization process, the Schottky transistor requires the same
number of process steps as does an n-p-n transistor.
For practical Schottky diodes, the dominant reverse current component is the edge leakage
current which is caused by the sharp edge around the periphery of the metal plate. To
eliminate this effect metal semiconductor diodes are fabricated with a diffused guard ring as
shown in the figure [b]. The guard ring is deep p-type diffusion and the doping profile is
tailored to give the p-n junction a higher breakdown voltage than the metal semiconductor
contact, thus preventing premature breakdown and surface leakage.
FET structures(refer written notes)
Monolithic Junction FET’s
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VLSI DESIGN
The figure shows some IC JFET structures. The n-channel JFET structure of first figure [a] is
compatible with the n-p-n transistor fabrication sequence. Another view of this n-channel
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VLSI DESIGN
JFET is shown in second figure [a], where we note that the top p+ gate region extends beyond
the n-type epitaxial layer region to make contact with the p-type substrate bottom gate. The n-
type channel is thus completely encircled by the gate structure and the application of a
suitably large negative voltage to the gate can pinch the channel off and reduce the drain-to-
source current to essentially zero. If the p+ top gate did not extend out to overlap the p-type
substrate, the n-type channel would not be completely encircled by the gate structure and it
would not be possible to cut off the drain-to-source current. The major drawback or the JFET
structure of second figure [a] is that the gate is connected to the p-type substrate, which is at a
ground potential. This restricts the use of this structure to only the common-gate
configuration
Second figure [b] shows another n-channel JFET. Its fabrication is similar to the one just
considered, the principal difference being in the top surface geometry. In this JFET the p+ top
gate is in the form of an annual ring that completely encloses the drain region of the JFET.
The only current path from source to drain will be underneath the p+ top gate. Therefore the
application of a suitably large negative voltage to the top gate can pinch off the channel and
reduce the drain-to-source current to essentially zero.
First figure [b] shows a p-channel JFET. The n+ gate region of this device extends out
beyond the source/drain/channel region to overlap the n-type epitaxial layer so that the gate
completely encircles the channel. The same processing sequence can be used for this JFET as
for the n-p-n transistor. But, if this is done, the gate-to-channel breakdown voltage
(corresponding to BVtRo) will be down in the range 6 to 8V and the full pinch-off of the
channel may not be possible. As a result, a specially tailored low-concentration boron
diffusion will be required to produce a higher gate –channel breakdown voltage and lower
channel doping; so that the channel can be pinched off at a voltage that is conveniently less
than the breakdown voltage. This, however, requires some extra processing steps making the
device more expensive.
A p-channel JFET employing boron- lon-implanted channel is shown in first figure [c]. Since
the ion implantation dosage can be very precisely controlled, the JFET parameters, such as
Vp and IDss can be closely set to the values desired This JFET uses the same processing steps
as the n-p-n transistor, with the addition of a photolithography, boron ion implantation and
annealing step.
MOSFET Technology and Various MOS Process(refer written notes+ppt)
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VLSI DESIGN
Most of the LSI/VLSI digital memory and microprocessor circuits is based on the MOS
Technology. More transistor and circuit functions can be achieved on a single chip with MOS
technology, which is the considerable advantage of the same over bipolar circuits. Below
given are the reasons for this advantage of MOS technology:
• Less chip area is demanded by an Individual MOS transistor, which results in more
functions in less area.
• Critical defects per unit chip area are low for a MOS transistor because it involves
fewer steps in the fabrication of a MOS transistor.
• Dynamic circuit techniques are practical in MOS technology, but not in bipolar
technology. A dynamic circuit technique involves use of fewer transistors to realise a
circuit function.
So you are already clear that because of above said reasons, its considerably cheap to use
MOS technology over Bipolar one.
Three types of MOS process are PMOS, NMOS and Complimentary MOS. Let’s take a look
at brief descriptions below.
p-Channel MOS or PMOS Technology
This MOS process operates at a very low data rate say 200Kbps to 1Mbps. PMOS is also
considered as the first MOS process which required special supply voltages as -9 volts, -12
volts and so on.
n-Channel MOS or NMOS Technology
We can say this is a second generation MOS process, after PMOS, which has considerable
improvement in data rates; say up to 2Mbps and resulted in the construction of LSI circuits of
a single standard +5volt supply.NMOS increases circuits speed in sharp, because of reduction
in the internal dimensions of devices; which is contrary to (and an advantage over) bipolar
circuits whose speed increases gradually.The difference in performance between both circuits
have steadily become smaller for both LSI and VLSI because of steady improvements in
pattern definition capability.
Have you ever heard of Self aligned silicon gate NMOS ? It’s a commonly used and popular
version of MOS technology. Now a days, a technique named as local oxidation is used for
this process to improve circuit density and performance. HMOS, SMOS and XMOS are the
commonly used names by manufacturers for this. Older versions of the process like Metal
Gate NMOS and PMOS are not used now a days for latest designs. A second layer of poly-
silicon may be added to the process for important memory applications.
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VLSI DESIGN
Complementary MOS Technology
So you might have already got an idea from the name “Complimentary MOS” ? Its a
combination of both n-channel and p-channel devices in one chip. Compared to both other
process, CMOS is complex in fabrication and requires larger chip area. Biggest advantage of
a CMOS circuit is reduced power consumption (less than NMOS); it is designed for zero
power consumption in steady state condition for both logic states. As you may already know,
CMOS circuits are widely used in digital equipments like watches, computers etc.
CMOS offers comparatively higher circuit density and high speed performance (used in
VLSI);and this is the primary reason why CMOS is still preferred despite it’s complex
manufacturing process. Memories and microprocessors made of CMOS usually employ
silicon gate process.
There are variations of MOS technology which offer either better performance or density
advantages over the standard process. Some of those are named as VMOS (V-groove MOS),
DSA (Diffusion Self Aligned), SOS (Silicon on Saphire), D-MOS (Double diffused MOS)
etc.
Simple MOSFET Structures
MOS Technology comprises of 3 process basically, p-channel MOS, n-channel MOS and
CMOS process. The basic purpose of all these process is to enhance MOSFET performance
one over the other, like lower power consumption, high power capability, relaibility
improvements, response speed etc.
PMOS Structure
The PMOS is the first device made in metal gate p-channel technology. PMOS infact is an
older version of the MOS process which is not used nowadays. A cross sectional view of the
PMOS structure is shown below.
NMOS Fabrication Process(refer written notes or Pucknell text)
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VLSI DESIGN
 By the process of Chemical Vapour Deposition (CVD), a thin layer of Si3N4 is
deposited on the entire wafer surface. With the first photolithographic step, the areas
where the transistors are to be fabricated are clearly defined. Through chemical
etching, Si3N4 is removed outside the transistor areas. In order to suppress the
unwanted conduction between transistor sites, an impurity such as Boron is implanted
in the exposed regions. Next, SiO2 layer of about 1 micro meters thickness is grown
in these inactive, or field regions by exposing the wafer to oxygen in an electric
furnace. This is known as selective or local oxidation process. The Si3N4 is
impervious to oxygen and thus inhibits growth of the thick oxide in the transistor
regions.
 Next, the Si3N4 is removed by an etchant that does not attack SiO2. A layer of oxide
about 0.1 micro meters thick is grown in the transistor areas. Then a layer of poly-
Silicon is grown over the entire wafer by CVD process. The second photolithographic
step shows the desired patterns for gate electrodes. The unwanted poly-Silicon is
removed by chemical or plasma etching. In order to introduce a source and drain in
particular regions for the MOS device, an n-type dopant, such as phosphorus or
arsenic, is introduced. This is done by either Diffusion or Ion Implantation method.
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VLSI DESIGN
The thick field oxide and the polysilicon gate are barriers to the dopant, but in this
process, the poly-Si becomes heavily n-type.
 Again, through CVD process, an insulating layer, SiO2, is deposited. As shown in the
figure above, the third photolithographic step shows the areas in which contacts to the
transistors are to be made. Chemical or plasma etching selectively exposes bare
silicon or poly-Si in the contact areas.
 Al is used for the interconnection. As shown in the figure above, the fourth masking
step shows the Al as desired for the circuit connections.
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VLSI DESIGN
MODULE 3
CMOS TECHNOLOGY
CMOS circuits require that both NMOS and PMOS enhancement devices to be fabricated
on same chip The main advantage of CMOS over NMOS and BIPOLAR technology is the
much smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a CMOS circuit has
almost zero static power dissipation. Power is only dissipated in case the circuit actually
switches. This allows to integrate many more CMOS gates on an IC than in NMOS or bipolar
technology, resulting in high packing density.
Advantages of CMOS logic
• No static power dissipation
• High o/p voltage swing(O/P SWING BETWEEN VDD and GROUND POTENTIAL)
• High Noise margin
• High Packing density
Disadvantage
• Possibility of latch up due to parasitic bipolar transistors because of existence of
PMOS and NMOS circuits in same substrate
CMOS structure
CMOS circuits require that both NMOS and PMOS enhancement devices to be fabricated
on same chip. CMOS structure may be
 nwell structure-nwell is implanted in psubstarte.nmos is fabdricated in in p-substrate
and pwelll is implanted in which nMOS is fabricated.
 pwell structure-pwell is implanted in n substrate.Pmos is fabricated in n-substrate and
n-welll is implanted in which PMOS is fabricated.
 Twin well structure – two separate wells (nwell and pwell) are implanted in lightly
doped silicon
A basic CMOS structure using n well process is shown below.
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VLSI DESIGN
This basic CMOS structure is built on a p-type substrate. The pMOS transistor requires an n-
type body region, so an n-well is diffused into the substrate in its vicinity. the nMOS
transistor has heavily doped n-type source and drain regions and a polysilicon gate over a thin
layer of silicon dioxide (SiO2, also called gate oxide). n+ and p+ diffusion regions indicate
heavily doped n-type and p-type silicon. The pMOS transistor is a similar structure with p-
type source and drain regions. The polysilicon gates of the two transistors are tied together
somewhere off the page and form the input A. The source of the nMOS transistor is
connected to a metal ground line and the source of the pMOS transistor is connected to a
metal VDD line. The drains of the two transistors are connected with metal to form the output
Y. A thick layer of SiO2 called field oxide prevents metal from shorting to other layers
except where contacts are explicitly etched.
A junction between metal and a lightly doped semiconductor forms a Schottky diode that
only carries current in one direction. When the semiconductor is doped more heavily, it forms
a good ohmic contact with metal that provides low resistance for bidirectional current flow.
The substrate must be tied to a low potential to avoid forward-biasing the p-n junction
between the p-type substrate and the n+ nMOS source or drain. Likewise, the n-well must be
tied to a high potential. This is done by adding heavily doped substrate and well contacts, or
taps, to connect GND and VDD to the substrate and n-well, respectively.
OPERATION OF A BASIC CMOS STRUCTURE
When the input is low NMOS transistor is off ,PMOS device will be ON and the o/p voltage
will be pulled up to high state near the positive power supply voltage VDD .When input is
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VLSI DESIGN
high NMOS turns on and PMOS turns OFF and output voltage will now drop to low state
near ground potential.In either of these conditions one of the transistor is off and current
through the CMOS pair is negligible. Hence power consumption is low,only significant
power consumption is during transition.Another advantage is large output voltage swing
,with high state o/p voltage close to VDD and low state close to ground potential.
FABRICATION -n-well CMOS structure
A basic CMOS structure - inverter could be defined by a hypothetical set of six masks: n-
well, polysilicon,n+ diffusion, p+ diffusion, contacts, and metal.
Step 1: Si Substrate
The n-well CMOS process starts with a moderately doped (with impurity concentration
around 2
×1021
impurities/m3
) p-type silicon substrate.
The wafer is first oxidized in a high-temperature (typically 900–1200 °C) furnace that causes
Si and O2 to react and become SiO2 on the wafer surface. Oxide must be patterned to define
the n-well.
An organic photoresist that softens where
exposed to light is spun onto the wafer.
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VLSI DESIGN
The first lithographic mask defines the n well region is brought in close proximity to the
wafer.
The photoresist is exposed through the n-well mask that allows light to pass through only
where the well should be.
The softened photoresist is removed to expose the oxide
The oxide is etched with hydrofluoric acid (HF) where it is not protected by the photoresist .
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VLSI DESIGN
Strip off remaining photoresist. photoresist is stripped away using a mixture of acids called
piranha etch
The well is formed where the substrate is not covered with oxide. Two ways to add dopants
are diffusion and ion implantation. In the diffusion process, the wafer is placed in a furnace
with a gas containing the dopants. When heated, dopant atoms diffuse into the substrate. With
ion implantation, dopant ions are accelerated through an electric field and blasted into the
substrate. In either method, the oxide layer prevents dopant atoms from entering the substrate
where no well
is intended.
Finally, the remaining oxide is stripped with HF to leave the bare wafer with wells in the
appropriate places.
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VLSI DESIGN
The transistor gates are formed next. These consist of polycrystalline silicon, generally called
polysilicon, over a thin layer of oxide. The thin oxide is grown in a furnace. Then the wafer is
placed in a reactor with silane gas (SiH4) and heated again to grow the polysilicon layer
through a process called chemical vapor deposition. The polysilicon is heavily doped to form
a reasonably good conductor
The wafer is patterned with photoresist and the polysilicon mask leaving the polysilicon gates
on top of the thin gate oxide.
The n+ regions are introduced for the transistor active area and the well contact.
a)A protective layer of oxide is formed .
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VLSI DESIGN
b)Oxide layer is patterned with the n-diffusion mask to expose the areas where the dopants
are needed
Masking
c)Etching oxide over n+regions
The n+ regions for source and drain of nMOS transistor and substrate tap are typically
formed with ion implantation, still are often called n-diffusion.The polysilicon gate over the
nMOS transistor blocks the diffusion so the source and drain are separated by a channel
under the gate. This is called a self-aligned process because the source and drain of the
transistor are automatically formed adjacent to the gate without the need to precisely align the
masks.
d)
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VLSI DESIGN
e)Finally, the protective oxide is stripped
The field oxide is grown to insulate the wafer from metal and patterned with the contact
mask to leave contact cuts where metal should attach to diffusion or polysilicon.
Finally, aluminum is sputtered over the entire wafer, filling the contact cuts as well.
Sputtering involves blasting aluminum into a vapor that evenly coats the wafer. The metal is
patterned with the metal mask and plasma etched to remove metal everywhere except where
wires should remain This completes the nMos fabrication process.
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VLSI DESIGN
Latch up in CMOS (refer written notes or QP answer key)
Fig .Latch up in CMOS inverter
Equivalent latch up ckt is given as
Latch-up is defined as the generation of a low-impedance path in CMOS chips between the
power supply rail and the ground rail due to interaction of parasitic pnp and npn bipolar
transistors. These BJTs form a silicon-controlled rectifier (SCR) with positive feedback and
virtually short circuit the power rail to-ground, thus causing excessive current flows and even
permanent device damage.
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VLSI DESIGN
In the equivalent circuit, Q1 is a vertical pnp transistor whose base is formed by the n-
well with its base-to-collector current gain (β1) as high as several hundreds. Q2 is a lateral
double-emitter npn transistor with its base formed by the p-type substrate. The base-to-
collector current gain (β2) of this lateral transistor may range from a few tenths to tens. Rweil
represents the parasitic resistance in the n-well structure with its value ranging from 1 kohm
to 20 kohm. The substrate resistance Rsub strongly depends on the substrate structure,
whether it is a simple p- or p- epitaxial layer grown on top of the p+ substrate which acts as a
ground plane. In the former case Rsub can be as high as several
hundred ohms, whereas in the latter case the resistance can be as low as a few ohms.
To examine the latch-up event, first assume that the parasitic resistances Rwell and
Rsub are sufficiently large so that they can be neglected (open circuit). Unless the SCR is
triggered by an external disturbance, the collector currents of both transistors consist of the
reverse leakage currents of the collector-base junctions and therefore, their current gains are
very low. If the collector current of one of the transistors is temporarily increased by an
external disturbance, however, the resulting feedback loop causes this current perturbation to
be multiplied by (β2 ). This event is called the triggering of the SCR. Once triggered, each
transistor drives the other transistor with positive feedback,eventually creating and sustaining
a low-impedance path between the power and the ground rails, resulting in latch-up.
It can be seen that if the condition
β1.β2>1
is satisfied, both transistors will continue to conduct a high (saturation) current, even after
the triggering perturbation is no longer available.
Causes of latch up
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VLSI DESIGN
 Sudden transients in power or ground buses due to simultaneous switching of many
drivers may turn on a BJT in SCR.
 Large currents in the parasitic SCR in CMOS chips can occur when the input or
output signal swings either far beyond the VDD level or far below the Vss (ground)
level, thus injecting a triggering current.
 Leakage currents in well junctions can cause large enough lateral currents.
Prevention of latch up
Latch up is prevented by decoupling the transistors to prevent formation of SCR
arrangement.The latch-up susceptibility is inversely proportional to the product of the
substrate doping level and the square of the spacing.
 Use p+ guard rings connected to ground around nMOS transistors and n+ guard rings
connected to VDD around pMOS transistors to reduce Rwell and Rsub and to capture
injected minority carriers before they reach the base of the parasitic BJTs.
 Place substrate and well contacts as close as possible to the source connections of
MOS transistors to reduce the values of Rwell and Rsub
 Reduce the gains of BJTs
CMOS LOGIC CIRCUITS
In CMOS logic circuits, both N-type and P-type transistors are used to realize logic
functions.
GENERAL STRUCTURE OF COMPLEMENTARY CMOS LOGIC GATE
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VLSI DESIGN
CMOS inverter
Gate schematic Logic symbol
Truth table
I/P(A) NMOS PMOS Y
1 ON OFF 0
0 OFF ON 1
CMOS inverter structure, consists of an enhancement-type nMOS transistor and an
enhancement-type pMOS transistor, operating in complementary mode . This configuration is
called Complementary MOS (CMOS). The circuit topology is complementary push-pull in
the sense that for high input, the nMOS transistor drives (pulls down) the output node while
the pMOS transistor acts as the load, and for low input the pMOS transistor drives (pulls up)
the output node while the nMOS transistor acts as the load.
• When a low voltage (0 V) is applied at the input, pMOS is conducting (switch closed)
while Nmos behaves like an open circuit.Therefore, the supply voltage (5 V) appears
at the output.
• Conversely, when a high voltage (5 V) is applied at the input, the nMOS is
conducting (switch closed) while pMOS behaves like an open circuit.Hence, the
ouput voltage is low (0 V).
The CMOS inverter has two important advantages over the other inverter configurations.
 The steady-state power dissipation of the CMOS inverter circuit is virtually
negligible, except for small power dissipation due to leakage currents.Either one of
the two transistors is ON in steady state,hence there is no continuous current path
from VDD to Vss power rail.
 The voltage transfer characteristic (VTC) exhibits a full output voltage swing
between 0 V and VDD.ie high voltage swing and hence high noise margin
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VLSI DESIGN
VOLTAGE TRANSFER CHARACTERISTICS / DC CHARACTERISTICS
Summary of CMOS INVERTER OPERATION
Region Nmos Pmos
A LINEAR CUT OFF
B LINEAR SATURATED
C SATURATED SATURATED
D SATURATED LINEAR
E CUT OFF LINEAR
Considering static conditions first In region A,NMOS is turned ON,PMOS is turned
OFF,output node is directly connected to VDD.No curren flows through inverter.In region E
Vin =~ logic 1,n MOS IS ON PMOS is OFF.o/P node is pulled down to logic 0.No current
flows.
In region B,input voltage has increased to a threshold that just exceeds threshold voltage of
nmos,NMOS is conduction with large value of drain to source voltage ,hence operates in
saturation and pmos is conducting wth small value of VDS ,hence it operates in linear
region.A small current now flows through inverter.Reverse is the case in region D.PMOS is
in saturation and nmos in linear region.
In region C ,both transistors are in saturation.Maximum current flows through the circuit.
Threshold voltage of inverter is that value of i/p voltage at which Vin =Vout.In the ideal case
ie Vtn=|Vtp| and transcinductance ratioβ n=βp .Vth=VDD/2.
(SEE DERIVATION OF THRESHOLD VOLTAGE IN TEXT -PUCKNELL)
NAND Gate
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VLSI DESIGN
GATE SCHEMATIC-NAND2
LOGIC SYMBOL-NAND2
TRUTH TABLE
Figure shows a 2-input CMOS NAND gate. It consists of two series nMOS transistors
between output node Y and GND and two parallel pMOS transistors between Y and VDD. If
either input A or B is 0, at least one of the nMOS transistors will be OFF, breaking the path
from Y to GND. But at least one of the pMOS transistors will be ON, creating a path from Y
to VDD. Hence, the output Y will be 1. If both inputs are 1, both of the nMos transistors will
be ON and both of the pMOS transistors will be OFF. Hence, the output will be 0. Thus, the
dual or complementary circuit structure allows that, for any given input combination, the
output is connected either to VDD or to ground via a low-resistance path. A DC current path
between the VDD and ground is not established for any of the input combinations. This
results in the fully complementary operation mode
k-input NAND gates are constructed using k series nMOS transistors and k parallel
pMOS transistors
NOR gate
GATE SCHEMATIC- NOR2
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VLSI DESIGN
LOGIC SYMBOL
TRUTH TABLE
A B PULL DOWN
NET
PULL UP NET Y
0 0 OFF ON 1
0 1 ON OFF 0
1 0 ON OFF 0
1 1 ON OFF 0
The circuit consists of a parallel-connected n-net(pull down network) and a series-connected
complementary pnet(pull up network). The nMOS transistors are in parallel to pull the output
low when either input is high. The pMOS transistors are in series to pull the output high when
oth inputs are low. If either input A or B or is logic 1, at least one or both of the nMOS
transistors will be ON, creating a path from Y to GND.Hence, the output Y will be 0. If both
inputs are 0, both of the nMOS transistors will be ON and o/p will be logic 0.If both inputs
are 0, both of the pMOS transistors will be ON and both of the nMOS transistors will be
OFF. Hence, creating a path from output Y to VDD.Hencethe output will be 1. Thus, the dual
or complementary circuit structure allows that, for any given input combination, the output is
connected either to VDD or to ground via a low-resistance path. A DC current path between
the VDD and ground is not established for any of the input combinations. This results in the
fully complementary operation mode .k-input NOR gates are constructed using k parallel
nMOS transistors and k series pMOS transistors
CMOS Full Adder (refer class notes for expression )
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VLSI DESIGN
The sum _out and carry-out signals of the full adder are defined as the following two
combinational Boolean functions of the three input variables, A, B, and C.
Using inverting property of full adder:inverting all inputs to a full adder leads to
inverted outputs,sum can be expressed in terms of carry,hence reducing the no:of
transistors to realize a full adder.
Using inverting property of full adder Carryout’=A’B’+B’C’+A’C’
Therfore Sum _out=ABC+(A+B+C)Carry_out’
Hence we realize
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VLSI DESIGN
A gate-level realization of these two functions is shown in Figure below. Instead of
realizing the two functions independently, we use the carry-out signal to generate the
sum output. This implementation will ultimately reduce the circuit complexity and,
hence, save chip area.
The transistor-level design of the CMOS full-adder circuit is shown in Figure below..
For translating the gate-level design into a transistor-level circuit description, we
note that both the sum..out and the carryout functions are represented by nested AND-
OR-NOR structures in Figure below. Each such combined structure (complex logic
gate) can be realized in CMOS as follows: the AND terms are implemented by series-
connected nMOS transistors, and the OR terms are implemented by parallel-
connected nMOS transistors. The input variables are applied to the gates of the nMOS
(and the complementary pMOS) transistors. Thus, the nMOS net may consist of
nested series-parallel ,connections of nMOS transistors between the output node and
the ground. Once the nMOS part of a complex CMOS logic gate is realized, the
corresponding pMOS net, which is connected between the output node and the power
supply, is obtained as the dual network of the nMOS net. the dual (pMOS) network is
actually equivalent to the nMOS network for both the sum_out and the carry-out
functions, which leads to a fully symmetric circuit topology.The circuit contains a
total of 14 nMOS and 14 pMOS transistors, together with the two CMOS inverters
which are used to generate the outputs.
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VLSI DESIGN
TRANSMISSION GATE
The CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in
parallel. The gate voltages applied to these two transistors are also set to be complementary
signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B
which is controlled by signal C.
TRANSMISION GATE SYMBOLS
If the control signal C is logic-high, i.e., equal to VDD, then both transistors are turned
on and provide a low-resistance current path between the nodes A and B. If, on the other
hand, the control signal C is low, then both transistors will be off, and the path between
the nodes A and B will be an open circuit. This condition is also called the high-impedance
state.
The strength of a signal is measured by how closely it approximates an ideal voltage
source. An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it
passes a strong 0. However, the nMOS transistor is imperfect at passing a 1. The high
voltage level is somewhat less than VDD(VDD-Vtn because of threshold drop). We say it
passes a degraded or weak 1. A pMOS transistor again has the opposite behavior, passing
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VLSI DESIGN
strong 1s but degraded 0s(|Vtp| because of threshold drop). When an nMOS or pMOS is used
alone as an imperfect switch, we sometimes call it a pass transistor. By combining an nMOS
and a pMOS transistor in we obtain a switchin figure below , that turns on when a 1 is applied
to g in which 0s and 1s are both passed in an acceptable fashion. We term this a transmission
gate or pass gate
Fig a)transmission gate structure. Fig b:Equivalent ckt depending on gate i/p.Fig C.passing 0
AND 1 when TG is on.
Equiavlent resisistance of transmission gate plotted as a function of i/p voltage
Req = Reqn||Reqp
Req=Equivalent resistance of nMOS
Reqn=Equivalent resistance of pMOS
Reqp=Equivalent resistance of transmission gate
Resistance offered by transmission gate is almost a constant irrespective of i/p voltage.
Application
Used in logic circuits like mux
Used in logic circuits like latches
Transmission gate realization of boolean expressions
Transmission gates consists of NMOS and PMOS pass transistors in parallel with nmos and
pmos controllled by control signals of opposite polarity.
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VLSI DESIGN
1) 2 I/p XOR ->F=A’B +AB’
How to draw the circuit
• We need to realize two expressions to realize xor.(AB’ and A’B)
• So there should be two transmission gates in circuit.
• Take one of the two variables A or B as control input of each transmission
gate.
• For eg .If A is taken as CONTOL I/P ther should be provision for passing B’
when A=1 and B when A=0.
• One TG should turn on when A=1 and other should turn ON when A=0.
• Gate control input for one transmission gate should be such that A is tied to
gate of nmos AND A’ is tied to gate of PMOS.When A=1 this TG will turn
ON.and the i/p to be connected to this TG is B’ .(hence WHEN A=1,B’ is
passed as this TG turns on)
• Gate control input for second transmission gate should be such that A’ is tied
to gate of nmos AND A is tied to gate of PMOS.hence when A=0 this TG
will turn ON.and the i/p to be connected to this TG is B . Hence when A=0,B
is passed as TG turns on)
• Both these transmission gates o/ps are tied together,hence either B or B’ is
passd depending on A=0 or A=1 respectively
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VLSI DESIGN
Circuit consists of a transmission gate and an inverter.
When B=0,TG turns on ,A is passed to o/p.when B=1,TG turns OFF. A i/p is bypassed
through the other path and available as i/p to inverter.Source of PMOS is connected to 1
(B=1) and source of nmos is connected to ground(B=0).Hence inverter will be functional
and it inverts whatever is applied as input to the ciruit.
Hence when B=1, A’ (A is inverted by inverter section, TG is off) is passed to o/p.
When B=0. A is passed to o/p as TG is on.(inverter is not fuctioning at this moment)
hence implemented a’b+ ab’
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VLSI DESIGN
Four expressions are to be realized.So four paths from I/P to O/P.Each I/p should be passed to
o/p depending on values of both S1 ad S0.So two transmission gates one with triggering i/p
s1 and other with triggering i/p S0 are connected in seies for passing each input to Y .O/P is
either of four i/ps . Hence each case should be connected in parallel.
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VLSI DESIGN
To avoid the floating o/p for the i/p
combination S2S1 ,we will add one more
expression 0.S2S1(no change to original
expression). Hence when S2=S1=1,0 is passed to o/p.
F=AB+ AB’C+ A’C’
=A(B+B’C)+A’C’
B.VDD +B’C =B.1+B’C =B+B’C is implemented by upper two paths.Then it is given as i/p
to another TG which turns on WHEN A=1. THEN A(B+B’C) is obtained.its o/p is tied with
bottom path that implements A’C’.hence A(B+B’C)+A’C’ is implemented.
CMOS IMPLEMENTATION
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VLSI DESIGN
XOR
Complementary pass transistor logic(CPL)or Differential pass transistor logic
(Refer class notes)
The main idea behind CPL is to use a purely nMOS pass-transistor network for the logic
operations, instead of a CMOS TG network. All inputs are applied in complementary form,
i.e., every input signal and its inverse must be provided; the circuit also produces
complementary outputs, to be used by subsequent CPL stages. Thus, the CPL circuit
essentially consists of complementary inputs, an nMOS pass transistor logic network to
generate complementary outputs, and CMOS output inverters to restore the output
signals.
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VLSI DESIGN
Basic block diagram for CPL circuits with two i/p variables is shown above.
Advantages
 The complexity of full-CMOS pass-gate logic circuits can be reduced dramatically .
 The elimination of pMOS transistors from the pass-gate network significantly reduces
the parasitic capacitances associated with each node in the circuit, thus, the operation
speed is typically higher compared to a full-CMOS counterpart.
Disadvantage
 But the improvement in transient characteristics comes at a price of increased process
complexity.In CPL circuits, the threshold voltages of the nMOS transistors in the
pass-gate network must be reduced to about 0 V through threshold-adjustment
implants, in order to eliminate the threshold-voltage drop( If Vtn=0,when i/p is
1,O/P=Vdd-Vtn=Vdd )
Design of CPL NAND2 and NOR2
NAND2-KMAP NOR2-KMAP
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VLSI DESIGN
Fig a-CPL NAND2 Fig b –CPL NOR2.
CPL XOR
Shifter (refer QP HINTS+ class notes)
N bit shifter should be able to shift up to n-1 places in right shft or left shift direction
The 4 bit shifter must have
 i/p from a 4 line parallel data bus
 4 o/p lines for the shifted data
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VLSI DESIGN
 Means of transferring i/p data to o/p lines with any shift from 0 to 3 bits-Pass
transistors or Transmission gates
 Data flows horizontally & control sgls flow vertically
 Any i/p line connected to any or all o/p lines
4x4 crossbar switch arrangement for shifter
Demerits
 if all s/ws closed, all i/p’s connected to all o/p’s
 16 control sgls needed
Barrel shifter
Couple gates in groups of 4 & 4 separate groups for sh0,1,2,3 bits
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VLSI DESIGN
Stick diagram,4x4 barell shifter
Shift / o/p Out0 Out1 Out2 Out3
Sh0 In0 In1 In2 In3
Sh1 In3 In0 In1 In2
Sh2 In2 In3 In0 In1
Sh3 In1 In2 In3 In0
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VLSI DESIGN
Stick Diagrams (refer written notes + pucknell text)
Stick Diagrams used to convey layer information through the use of a color code.
Components in CMOS technology and its colour code
Via Connection between metal
layers
Demarcation
line
-----------------
(BROWN)
Pwell edge
VDD or VSS
contact
Substrate/well contact
111

VLSI DESIGN
Layers in stick diagram
Metal
Two types of metal are used to represent the supply rails metal1 (blue ) or metal2 (purple )
Polysilicon
Polysilicon ( red) is used to represent the gate.
n-type diffusion
n-type diffusion ( green) is used to represent the source and drain n-transistors.
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VLSI DESIGN
p-type diffusion
p-type diffusion (yellow ) is used to represent the source and drain p-transistors.
Contacts
Contacts ( black) are used to represent electrical connections.(eg diffusion to metal,or
polysilicon to metal)
Via
Cuts called vias are used to make contact between two metal layers
CMOS Joining Rules
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VLSI DESIGN
 Wherever polysilicon (red) cross diffusion (green) an n-transistors is formed and p-
transistor is formed wherever polysilicon (red) cross diffusion (yellow)
 Diffusions of the opposite types cannot cross and contact
 Metal can cross polysilicon or diffusion without any significant effect
 P and N diffusion wires must not directly join each other nor may they cross pwell or
nwell boundary ie diffusion should not cross demarcation line in stick diagram
 Metal1 (blue) can contact metal2 (purple), but via is needed
 Simple contacts can be used to connect diffusion or polysilicon to metal
 Only metal and polysilicon can cross demarcation line
Eg:-CMOS INVERTER(using pwell process)
 n & p transistors are separated by demarcation line
 Place crosses on VDD & VSS rails one each for every p & n transistors.
 Diffusion paths must not cross Demarcation line
 n-diffusion & p-diffusion wires must not join
 Only Metal & polysilicon can cross demarcation line
Steps to draw CMOS inverter stick diagram
 Draw VDD and VSS power supply rails.(two horizontal lines) Can be drawn using
metal1 or metal 2.Here metal 1 is used (blue).
 Draw n diffusion(green) and p diffusion(yellow) below and above the demarcation
line.Diffusion is crossed by polysilicon (gate)to form NMOS and PMOS
respectively.sourse of NMOS is connected to VSS ,source of pmos is connected to
VDD.Diffusion connected with metal so contact is required.
 Gate of nmos and pmos is joined and connected to input.(polysilicon can be used for
signal wires eg i/p,o/p etc).so no contact is required to connect gate to input.
 Drains of transistors are connected using metal and output is taken.either polysilicon
or metal can be used for output line.If metal is used simply extend metal connection
b/w two drains.If polysilicon is used make a contact where polysilicon contacts metal.
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VLSI DESIGN
 Demarcation line is shown which shows pwell edge.It seperates n substrate in which
pmos is fabricated and nmos in pwell.
 Draw substrate contact(VDD CONTACT) and well contact(VSS CONTACT).
BLUE METAL 1
YELLOW P+DIFFUSION
GREEN N+DIFFUSION
-- - - -- --- --- -- DEMARCATION LINE
VDD OR VSS CONTACT
CONTACT
2I/P CMOS NOR GATE
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VLSI DESIGN
2 I/P CMOS NAND
Implement
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VLSI DESIGN
Procedure followed to draw stick diagram in alternate method
 Draw VDD and VSS power rails(SHOULD ME MARKED AS VDD AND VSS)
 Draw demarcation line marking pwell edge(BROWN)
 Draw p diffusion horizontal straight line( YELLOW)
 Draw n diffusion horizontal straight line(GREEN)
 Draw polysilicon gates (RED) vertical straight line crossing n and p diffusion as
many times as no :of input variables.for example for n variable expression n nmos
and n pmos transistors are formed.
 Source and drain of nmos and pmos are connected by metal lines (BLUE) to obtain
parallel and series combination of transiostors so formed as per transistor
schematic.Whenever metal is connected to diffuision contact is made.
Examples shown
Y=ABC
Y=A+BC
Y=AB+CD
3input NAND
117

VLSI DESIGN
NMOS DESIGN STYLE
NMOS logic circuits have nmos pulldown network implementing logic function.and nmos
depletion mode transistor in pullup network.depletion mode transistor is shown in diagram as
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VLSI DESIGN
a transistor with gate shorted to source of
Gate connected to source of nmos pull up transistor by burried contact.To show a depletion
mode transistor yellow implant is shown which indicates channel is implanted.(depletion
mode transistor has channel implanted at time of fabrication)
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VLSI DESIGN
Nmos INVERTER
NMOS NAND
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VLSI DESIGN
MODULE 4
CMOS SEQUENTIAL CIRCUITS(refer KANG +CLASS NOTE)
Sequential circuits or regenerative are circuits in which the output is determined by
the current inputs as well as the previously applied input variables. Figure shows a sequential
circuit consisting of a combinational circuit and a memory block in the feedback loop. In
most cases, the regenerative behaviour of sequential circuits is due to either a direct or
indirect feedback connection between the output and the input.
The critical components of sequential systems are the basic regenerative circuits,
which can be classified into three main groups: bistable circuits, monostable circuits, and
astable circuits.Bistable circuits have, as their name implies, two stable states or operation
modes,each of which can be attained under certain input and output conditions. Among these
three main groups of regenerative circuit types, the bistable circuits are by far the most
widely used 'and the most important class. All basic latch and flip-flop circuits, registers, and
memory elements used in digital systems fall into this category.
Principle of bistable circuits
CIRCUIT SCHEMATIC TRANSISTOR LEVEL IMPLEMENTATION
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VLSI DESIGN
Voltage transfer chara of bistatble elemnet
A bistable circuit — a circuit having two stable states that represent 0 and 1. Another
common name for a bistable circuit is flip-flop. The cross-coupling of two inverters results in
a bistable circuit, that is, a circuit with two stable states, each corresponding to a logic state.
The circuit serves as a memory, storing either a 1 or a 0.
SR FLIPFLOP
NOR BASED SR FLIP FLOP
The circuit consists of two CMOS NOR2 gates. One of the input terminals of
eachNOR gate is used to cross-couple to the output of the other NOR gate,(hence, the circuit
can perform a simple memory function of holding its state.,)while the second input enables
triggering of the circuit. S and R external triggering inputs are for allowing a change of state
from one stable operating mode to the other.
Gate level schematic and block diagram
Truth table
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VLSI DESIGN
Circuit operation
The SR flipflop has two complementary outputs, Q and Q. By definition, the flipflop is
said to be in its set state when Q is equal to logic " 1 " and Q is equal to logic "0."
Conversely, the latch is in its reset state when the output Q is equal to logic "0" and Q is
equal to "1."
The operation of the CMOS SR flip circuit shown in Fig. can be examined in more
detail by considering the operating modes of the four nMOS transistors, MI, M2, M3, and
M4. If the set input (S) is equal to logic high(VOH) and the reset input (R) is equal to logic
low(VOL), both of the parallel-connected transistors Ml and M2 will be on. Consequently, the
voltage on node Q will assume a logic-low level of VOL = 0. At the same time, both M3 and
M4 are turned off, which results in a logic-high voltage (VOH) at node Q. If the reset input (R)
is equal to VOH and the set input (S) is equal to VOL, the situation will be reversed (Ml and
M2 turned off Qis at logic high and M3 and M4 turned on-Q at logic low). When both of the
input voltages are equal to logic low ,VOL o there are two possibilities. Depending on the
previous state of the SR latch, either M2 or M3 will be on, while both of the trigger
transistors MI and M4 are off. This will generate a logic-low level of VOL = O at one of the
output nodes, while the complementary output node is at VOH.
Hence to summarize
 If both input signals ( S and R)are equal to logic "0," the SR flipflop will operate
exactly like the simple cross-coupled bistable element, it will preserve (hold) either
one of its two stable operating points (states) as determined by the previous inputs.
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VLSI DESIGN
 If the set input (S) is equal to logic "1" and the reset input is equal to logic "0," then
the output node Q will be forced to logic " 1 " while the output node Q is forced to
logic "0." This means that the SR flipflop will be set, regardless of its previous state.
 If S is equal to "0" and R is equal to " ," then the output node Q will be forced to "0"
while Q is forced to "1." Thus, with this input combination, the flipflop is reset,
regardless of its previously held state.
 If both of the inputs S and R are equal to logic 1" ,both output nodes will be forced to
logic "0," which conflicts with the complementarity of Q and Q. Therefore, this input
combination is not permitted during normal operation and is considered to be a not
allowed condition.
The static operation modes and voltage levels of the NOR-based CMOS SR flipflop circuit
are summarized in the following table.
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VLSI DESIGN
NAND2 SR Latch or flipflop
The gate-level schematic and the corresponding block diagram representation of the NAND-
based SR flipflop circuit are shown in Fig.. The small circles at the S and R input terminals
indicate that the circuit responds to active low input signals. NAND-based SR flipflop circuit
reveals that in order to hold (preserve) a state, both of the external trigger inputs must be
equal to logic " 1." The operating point or the state of the circuit can be changed only by
pulling the set input to logic zero or by pulling the reset input to zero. We can observe that if
S is equal to "0" and R is equal to " 1," the output Q attains a logic " 1 " value and the
complementary output Q becomes logic "0." Thus, in order to setthe NAND SR flipflop, a
logic "0" must be applied to the set (S) input. Similarly, in order to reset the latch, a logic "0"
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VLSI DESIGN
must be applied to the reset (R) input. The conclusion is that the NAND-based SR flipflop
responds to active low input signals, as opposed to the NOR-based SR latch, which
responds to active high inputs. Note that if both input signals are equal to logic "0," both
output nodes assume a logic-high level, which is not allowed because it violates the
complementarity of the two outputs.
Clocked SR Latch
To facilitate synchronous operation, the circuit response can be controlled simply by adding a
gating clock signal to the circuit, so that the outputs will respond to the input levels only
during the active period of a clock pulse.
The gate-level schematic of a clocked NOR-based SR latch is shown in Fig. It can be seen
that if the clock (CK) is equal to logic "0," the input signals have no influence upon the
circuit response. The outputs of the two AND gates will remain at logic "0," which forces the
SR latch to hold its current state regardless of the S and R input signals. When the clock input
goes to logic " 1," the logic levels applied to the S and R inputs are permitted to reach the SR
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VLSI DESIGN
latch, and possibly change its state. Note that as in the nonclocked SR latch, the input
combination S = R = "1" is not allowed in the clocked SR latch. With both inputs S and R at
logic " 1," the occurrence of a clock pulse causes both outputs to go momentarily to zero.
When the clock pulse is removed, i.e., when it becomes "0," the state of the latch is
indeterminate. It can eventually settle into either state, depending on slight delay differences
between the output signals. The circuit is strictly level-sensitive during active clock
phases, i.e., any changes occurring. in the S and R input voltages when the CK level is
equal to " 1 " will be reflected onto the circuit outputs. Consequently, even a narrow spike
or glitch occurring during an active clock phase can set or reset the latch, if the loop delay is
shorter than the pulse width.
Figure shows a CMOS implementation of the clocked NOR-based SR latch circuit, using two
simple AOI gates. Notice that the AOI-based implementation of the circuit results in a very
small transistor count.
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VLSI DESIGN
The NAND-based SR latch can also be implemented with gating clock input, as shown in
Fig. It must be noted, however, that both input signals S and R as well as the clock signal CK
are active low in this case. This means that changes in the input signal levels will be ignored
when the clock is equal to logic " 1," and that inputs will influence the outputs only when the
clock is active, i.e., CK = "0."
For the circuit implementation of this clocked NAND-based SR latch, we can use a simple
OAI structure, which is essentially analogous to the AOI-based realization of the clocked
NOR SR latch circuit.
NAND BASED SR LATCH WITH ACTIVE HIGH INPUTS
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VLSI DESIGN
A different implementation of the clocked NAND-based SR latch is shown in Fig. . Here,
both input signals and the CK signal are active high, i.e., the latch output Q will be set when
CK = " 1," S = " 1," and R = "O." Similarly, the latch will be reset when CK = "1," = "O,"
and R = "1." The latch preserves its state as long as the clock signal is inactive, i.e., when CK
= "O". The drawback of this implementation is that the transistor count is higher than
the active low version.
Clocked JK Latch
The JK latch is commonly called a JK flip-flop. SR latch circuits suffer from the common
problem of having a not-allowed input combination, i.e., their state becomes indeterminate
when both inputs S and R are activated at the same time. This problem can be overcome by
adding two feedback lines from the outputs to the inputs, as shown in Fig.. The resulting
circuit is called a JK latch.
Figure shows an all-NAND implementation of the JK latch with active high inputs, and the
corresponding block diagram representation.
The J and K inputs in this circuit correspond to the set and reset inputs of the basic SR latch.
When the clock is active, the latch can be set with the input combination (J = '1," K = "0"),
and it can be reset with the input combination (J = "0," K = "1"). If both inputs are equal to
logic "0," the latch preserves its current state. If, on the other hand, both inputs are equal to "
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VLSI DESIGN
1 " during the active clock phase, the latch simply switches its state due to feedback. In other
words, the JK latch does not have a not-allowed input combination. As in the other clocked
latch circuits, the JK latch will hold its current state when the clock is inactive (CK = "0").
The operation of the clocked JK latch is summarize-d in the truth Table.
NOR BASED IMPLEMENTATION OF JK LATCH
Figure shows an alternative, NOR-based implementation of the clocked JK latch, and CMOS
realization of this circuit. Note that the AOI-based circuit structure results in a relatively low
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VLSI DESIGN
transistor count, and consequently, a more compact circuit compared to the all-NAND
realization
While there is no not-allowed input combination for the JK latch, there is still a potential
problem. If both inputs are equal to logic " 1 " during the active phase of the clock pulse, the
output of the circuit will oscillate (toggle) continuously until either the clock becomes
inactive (goes to zero), or one of the input signals goes to zero. To prevent this undesirable
timing problem, the clock pulse width must be made smaller than the input-to-output
propagation delay .
Master-Slave Flip-Flop
Mater slave flipflop consists of two latch stages in a cascaded configuration. Key operation
principle is that the two cascaded stages are activated with opposite clock phases. This
configuration is called the master-slave flip-flop
The input latch in Fig. , called the "master," is activated when the clock pulse is high. During
this phase, the inputs J and K allow data to be entered into the flip-flop, and the first-stage
outputs are set according to the primary inputs. When the clock pulse goes to zero, the master
latch becomes inactive and the second-stage latch, called the "slave," becomes active. The
output levels of the flip-flop circuit are determined during this second phase, based on the
master-stage outputs set in the previous phase.
Since the master and the slave stages are effectively decoupled from each other with the
opposite clocking scheme, the circuit is never transparent, i.e., a change occurring in the
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VLSI DESIGN
primary inputs is never reflected directly to the outputs. This very important property clearly
separates the master-slave flip-flop from the latch circuits
Because the master and the slave stages are decoupled from each other, the circuit allows for
toggling when J = K = "1," but it eliminates the possibility of uncontrolled oscillations since
only one stage is active at any given time.
A NOR-based alternative realization for the master-slave flip-flop circuit is shown in Fig.
The master-slave flip-flop circuit examined here has the potential problem of "one's
catching." When the clock pulse is high, a narrow spike or glitch in one of the inputs, for
instance a glitch in the J line (or K line), may set (or reset) the master latch and thus cause an
unwanted state transition, which will then be propagated into the slave stage during the
following phase. This problem can be eliminated to a large extent by building an edge-
triggered master-slave flip-flop.
D LATCH
The gate-level representation of the D-latch is simply obtained by modifying the clocked
NOR-based SR latch circuit. Here, the circuit has a single input D, which is directly
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VLSI DESIGN
connected to the S input of the latch. The input variable D is also inverted and connected to
the R input of the latch. It can be seen from the gate-level schematic that the output Q
assumes the value of the input D when the clock is active, i.e., for CK = "1." When the clock
signal goes to zero, the output will simply preserve its state. Thus, the CK input acts as an
enable signal which allows data to be accepted into the D-latch.
 The D-latch finds many applications in digital circuit design, primarily for temporary
storage of data or as a delay element.
Consider the circuit diagram given in Fig., which shows a basic two-inverter loop and two
CMOS transmission gate (TG) switches.
The TG at the input is activated by the CK signal, whereas the TG in the inverter loop is
activated by the inverse of the CK signal, CK. Thus, the input signal is accepted (latched)
into the circuit when the clock is high, and this information is preserved as the state of the
inverter loop when the clock is low.
The operation of the CMOS D-latch circuit can be better visualized by replacing the CMOS
transmission gates with simple switches, as shown in Fig.
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VLSI DESIGN
A timing diagram shows the time intervals during which the input and the output signals
should be valid (unshaded).
The valid D input must be stable for a short time before (setup time, tsetup) and after (hold
time, thold) the negative clock transition, during which the input switch opens and the loop
switch closes. Once the inverter loop is completed by closing the loop switch, the output will
preserve its valid level. In the D-latch design, the requirements for setup time and hold time
should be met carefully. Any violation of such specifications can cause metastability
problems.
Figure shows a different version of the CMOS D-latch.
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VLSI DESIGN
The circuit contains two tristate inverters, driven by the clock signal and its inverse. The
basic operation principle of the circuit is the same as that shown in first figure. The first tri-
state inverter acts as the input switch, accepting the input signal when the clock is high. At
this time, the second tristate inverter is at its high-impedance state, and the output Q is
following the input signal. When the clock goes low, the input buffer becomes inactive, and
the second tristate inverter completes the two-inverter loop, which preserves its state until the
next clock pulse.
MASTER SLAVE NEGATIVE EDGE TRIGGERED D FLIP FLOP
Consider the two-stage master-slave flip-flop circuit shown in Fig.,which is constructed by
simply cascading two, D-latch circuits. The first stage (master) isidriven by the clock signal,
while the second stage (slave) is driven by the inverted clock signal. Thus, the master stage is
positive level-sensitive, while the slave stage is negative level-sensitive.
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VLSI DESIGN
When the clock is, high, the master stage follows the D input while the slave stage holds the
previous value. When the clock changes from logic "1" to logic "," the master latch ceases to
sample the input and stores the D value at the time of the clock transition. At the same time,
the slave latch becomes transparent, passing the stored master value Qm to the output of the
slave stage, Q.. The input cannot affect the output because the master stage is disconnected
from the D input. When the clock changes again from logic 0" to 1," the slave latch locks in
the master latch output and the master stage starts sampling the input again. Thus, this circuit
is a negative edge-triggered D flip-flop by virtue of the fact that it samples the input at the
falling edge of the clock pulse.
CMOS LOGIC SYSTEMS (refer CLASS notes +UYEMURA text )
 Psueodo nMOS
 Dynamic CMOS
 CMOS domino
 Clocked CMOS
 n-p CMOS
 Zipper CMOS
Pseudo nMOS
PseudonMOS NAND3 structure
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VLSI DESIGN
PseudonMOS logic structure consists of nMOS pull down n/w and a PMOS pullup transistor
with its gate grounded.Depletion load pull upt transistor of standard nMOS logic ckts
replaced with a pMOS transistor with its gate connected to ground so that it is always ON
forms a pseudo nMOS logic structure.This a ratioed circuit since Gain ratio of n-driver
transistors to p-transistor load (beta driver /beta load ), is important to ensure adequate noise
margin.
Disadvantages of pseudo-nMOS gate compared to a complementary CMOS gate
 Nonzero static power dissipation, since the always-on pmos load device conducts a
steady-state current when the output voltage is lower than VDD. Also,
 Value of VOL and the noise margins are now determined by the ratio of the pmos load
transconductance(βp) to the pull-down or driver transconductance(βn)
Advantage
 The clear advantage of pseudo-NMOS is the reduced number of transistors
(N+1 )versus 2N for complementary CMOS).
[Reason for low value of VOL ,and reduced noise margin
(Noise margin,NML=VIL-VOL,VOL=0 for FULL CMOS but for pseudo nMOs .WHEN Vout
is low -VOL, ie Vin =VDD,nmos pulldown n/w is ON providing a path from output node to
ground,where as PMOS pull up is always ON connecting VDD to o/p node.Hence VOL will
not be zero.(this is not the case with CMOS since if pulldown n/w is ON pull will be
off ).hence noise margin also will be low compared to complementary CMOS.
Inorder to have a low value for VOL ratioing is necessary.
The value of VOL is obtained by equating the currents through the driver(NMOS) and load
(PMOS)devices for Vin = VDD. At this operation point, it is reasonable to assume that the
NMOS device resides in linear mode (since the output should ideally be close to 0V), while
the PMOS load is saturated.
Drain current in saturation IdP= βp (VGSP-VTP) VDSAT-V2
DSAT
2
Drain current in linear region IdN= βn(VGSN-VTN)Vout-V2
out
2
Vout=VOL
VG=VDD
VGSP=0 - VDD= - VDD
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VLSI DESIGN
VGSN= VDD
IdN = - IdP
βn(VDD-VTN)VOL-V2
OL= - βp (-VDD-VTP) VDSAT-V2
DSAT
2 2
VTN= |VTP|, NEGLECTING HIGHER POWERS
VOL= - βp (-VDD-VTP) VDSAT
βn(VDD-VTN)
= βp VDSAT
βn
VOL = µp Cox(W/L)P VDSAT
µn Cox(W/L)n
Hence to get low value of VOL PMOS device should be sized much smaller than that
of NMOS device.]
Dynamic CMOS
Actual logic is implemented in faster nMOS logic and a p -transistor is used for non-
time critical precharging of output line so that output capacitance is charged to VDD. The
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VLSI DESIGN
circuit operation is based on first precharging the output node capacitance and subsequently,
evaluating the output level according to the applied inputs.
Precharge
When CLK = 0, the output node Out is precharged to VDD by the PMOS transistor
Mp.During that time, the evaluate NMOS transistor Me is off, so that the pull-down path is
disabled.
Evaluation
For CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me is turned
on. The output is conditionally discharged based on the input values and the pull-down
topology. If the inputs are such that the PDN(Pull Down Network) conducts, then a low
resistance path exists between Out and GND and the output is discharged to GND. If the
PDN is turned off, the precharged value remains stored on the output capacitance CL
Advantage
 Dynamic CMOS circuit technique allows us to significantly reduce the number of
transistors used to implement any logic function.
Limitations
 Charge sharing may be a problem unless the inputs are constrained not to change
during the period of clock
 Single phase dynamic logic structures cannot be cascaded since owing to circuit
delays incorrect inputs to next stage may be present when evaluation begins and
wrong output results.
One remedy is to employ a four phase clock in which actual signals are
derived clocks Φ12 Φ23 Φ34 Φ41 as shown in fig b. The basic circuit in fig a is
modified by the inclusion of a transmission gate as in fig c the function of which is to
samle the output during evaluate period and to hold the output state while the next
stage logic evaluates. For this strategy to work next stage must operate with
overlapping but later clock signals. Since there are four different derived clock signals
there are four different clocking configurations. Inorder to avoid erroneous evaluation
gate must be connected in allowable next sequences set out in table below
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VLSI DESIGN
Clocked CMOS(C2
MOS )LOGIC
The logic is implemented in both n- and p transistors in form of a pull up p block and
a complementary n block pull down structure .However logic in this case is evaluated only
during on period of clock.A clocked inverter(tristate inverter) forms part of this family.
Limitation
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VLSI DESIGN
 Owing to extra transistors in series slow rise times and fall times can be expected.
CMOS Domino logic
An extension to dynamic CMOs LOGIC ,a dynamic CMOS logi stage followed by a
static inverter constitute CMOS domino logic.This static inverting buffer allows for
cascading of logic structures using only a single phase clock without erroneous outputs.
Features
 Such logic structures can have smaller area than conventional CMOS logic
 Requires less no:of transistors to implement logic function compared to conventional
CMOS
 Parasitic capacitances are smaller so that higher operating speeds are possible.
 Operation is free of glitches since each gate can make only one 1 to 0 transition
 Only non inverting structures are possible because of presence of inverting buffer
Limitations
 Charge distribution is a problem in domino CMOS
Eg AB+GH+(E+F)(C+D)
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VLSI DESIGN
n-p CMOS(NORA)LOGIC
This is a variation of basic dynamic logic arrangement in which actual logic blocks are
alternatively n and p in a cascaded structure.The pre charge and evaluate transistors are fed
from clock and alternately and functions of top and bottom transistors are alternateϕ ϕ
between precharge and evaluate. The precharge-and-evaluate timing of nMOS logic stages is
accomplished by the clock signal , whereas the pMOS logic stages are controlled by theϕ
inverted clock signal, . The operation of the NORA CMOS circuit is as follows: When theϕ
clock signal is low, the output nodes of nMOS logic blocks are precharged to VDD through
the pMOS precharge transistors, whereas the output nodes of pMOS logic blocks are pre-
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VLSI DESIGN
discharged to 0 V through the nMOS discharge transistors, driven by .When the clockϕ
signal makes a low-to-high transition (note that the inverted clock signal makes a high-to-low
transition simultaneously), all cascaded nMOS and pMOS logic stages evaluate one after
the other.
ADVANTAGE of NORA CMOS logic
 Static CMOS inverter is not required at the output of every dynamic logic stage.
Instead, direct coupling of logic blocks is feasible by alternating nMOS and pMOS
logic blocks. NORA logic is also compatible with domino CMOS logic.
 The second important advantage of NORA CMOS logic is that it allows pipelined
system architecture.
Limitation
 Suffer from charge sharing and leakage.
Zipper CMOS
Zipper CMOS is identical with NORA(np CMOS)with the exception of the clock signals.
The Zipper CMOS clock scheme requires the generation of slightly different clock signals for
the precharge (discharge) transistors and for the pull-down (pull-up) transistors. In particular,
the clock signals which drive the pMOS precharge and nMOS discharge transistors allow
these transistors to remain in weak conduction or near cut-off during the evaluation phase,
thus compensating for the charge leakage and charge-sharing problems.
Scaling(refer pucknell text)
The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to
as scaling. It is expected that the operational characteristics of the MOS transistor will change
with the reduction of its dimensions. Also, some physical limitations eventually restrict the
extent of scaling that is practically achievable. There are two basic types of size-reduction
strategies: full scaling (also called constant-field scaling) and constantvoltage scaling. Scaling
of MOS transistors is concerned with systematic reduction of overall dimensions of the
devices as allowed by the available technology, while preserving the geometric ratios found
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VLSI DESIGN
in the larger devices. The proportional scaling of all devices in a circuit would certainly result
in a reduction of the total silicon area occupied by the circuit, thereby increasing the overall
functional density of the chip. To describe device scaling, we introduce a constant scaling
factor S > 1. All horizontal and vertical dimensions of the large-size transistor are then
divided by this scaling factor to obtain the scaled device. The extent of scaling that is
achievable is obviously determined by the fabrication technology and more specifically, by
the minimum feature size.
Scaling models and scaling factors
 Constannt field (E) scaling (full scaling)- This scaling option attempts to preserve
the magnitude of internal electric fields in the MOSFET, while the dimensions are
scaled down by a scaling factor . To achieve this goal, all potentials must be scaled
down proportionally, by the same scaling factor.
 Constannt Voltage (V) scaling- In constant-voltage scaling, all dimensions of
MOSFET are reduced by a scaling factor. The power supply voltage and the terminal
voltages, on the other hand, remain unchanged.
 Combined voltage and field scaling.
L =Length of channel
W =Width of chananel
D =Thickness of channel
X =junction depth
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VLSI DESIGN
To accomodtae these three models thwo scaling factors are used.1/α AND 1/β. 1/β is chosen
a scaling factor for supply voltage VDD and gate oxide thickness D. 1/α- for all other linear
dimensions.For the constant field moldel β=α and for constant voltage moldel β=1 is applied.
Effects of scaling-Scaling factors for device scaling
(OBTAIN EXPRESSION (DERIVE) FOR EACH DEVICE PARAMETER –GIVEN
IN TEXT –PUCKNELL-just summary is shown here.U have to derive each)
To summarize, constant field scaling reduces both the drain current and the drain-to-source
voltage by a factor of α; hence, the power dissipation of the transistor will be reduced by the
factor α2
.This significant reduction of the power dissipation is one of the most attractive
features of full scaling. constant-voltage scaling may be preferred over full (constant-field)
scaling in many practical cases because of the external voltage-level constraints. It must
be recognized, however, that constant-voltage scaling increases the drain current density and
the power density .This large increase in current and power densities may eventually cause
serious reliability problems for the scaled transistor, such as electromigration, hot-carrier
degradation, oxide breakdown, and electrical over-stress.
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VLSI DESIGN
Small geometry effects-Short-Channel Effects
A MOS transistor is called a short-channel device if its channel length is on the same order of
magnitude as the depletion region thicknesses of the source and drainjunctions. Alternatively,
a MOSFET can be defined as a short-channel device if the effective channel length Leffis
approximately equal to the source and drain junction depth xj.
Velocity satutation
The lateral electric field EY along the channel increases, as the effective channel length is
decreased. While the electron drift velocity Vd in the channel is proportional to the electric
field for lower field values, this drift velocity tends to saturate at high channel electric fields.
Carrier velocity saturation actually reduces the saturation-mode current.
Mobility degaradation
In short-channel MOS transistors, the carrier velocity in the channel is also a function of the
normal (vertical) electric-field component Ex. Since the vertical field influences the
scattering of carriers (collisions suffered by the carriers) in the surface region, the surface
mobility is reduced.This is mobility degradation.
Modification of threshold votage
Subthreshold conduction in small-geometry MOS transistors- The channel current that
flows under these conditions (VGS < Vtn) is called the subthreshold current.
Punch-through
The channel length is on the same order of magnitude as source and drain depletion region
thicknesses. For large drain-bias voltages, the depletion region surrounding the drain can
extend farther toward the source, and the two depletion regions can eventually merge. This
condition is termed punch-through the current rises sharply once punch-through occurs.
Oxide breakdown
Another limitation on the scaling of thickness of oxide tox is the possibility of oxide
breakdown. If the oxide electric field perpendicular to the surface is larger than a certain
breakdown field, the silicon-dioxide layer may sustain permanent damage during operation,
leading to device failure.
Hot carrier injection
This decrease in critical device dimensions to submicron ranges, accompanied by increasing
substrate doping densities, results in a significant increase of the horizontal and vertical
electric fields in the channel region. Electrons and holes gaining high kinetic energies in the
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VLSI DESIGN
electric field (hot carriers) may, however, be injected into the gate oxide, and cause
permanent changes in the oxide interface charge distribution, degrading the current-voltage
characteristics of the MOSFET
BiCMOS (refer written notes or QP answer key+pucknell text)
Combines Bipolar and CMOS transistors in a single integrated circuit. By retaining benefits of bipolar
and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance. The
superiority of the BiCMOS gate lies in the high current drive capability of the bipolar output
transistors, the zero static power dissipation, and the high input impedance provided by the MOSFET
configuration.
BiCMOS STRUCTURE (text-pucknell)
Bicmos technology is a mixture of bipolar and CMOS technologies,therefore many of processing
steps are shared b/w bipolar and mos devices.for eg.n+ source and drian doping step is used for
emitter and collector contact of bipolar structure.The p channel source and drain implant is used for
base contact of bipolar structure.
The simplest bicmos structure is shown here.
It is a triple diffused Bicmos structure formed by simple addition of npn transistor to basic nwell cmos
process.In this pmos n well is used as collector of bipolar device .An additional mask is used for p
base region .The nmos device is built in 5to 10micrometer thick p epilayer on top of a
p+substrate,wher pmos is built in implanted n well .The p+ substrate is used to reduce latch up
possibility by providing low impedance current path through a vertical pnp parasitic device.Poly
gates are used for n and p channel device.
3dBiCMOS structure has following limitation
 The n well is lightly doped.This leads to high collector resistance which limits usefulness of
bipolar transistor.
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VLSI DESIGN
Above limitation is overcome by introducing a buried n+ layer under n well.The resulting structure
is called standard buried collector Bi CMOS.
The pwell step is also used for junction isolation structure of collector region.
COMPARISON B/W CMOS AND BIPOLAR TECHNOLOGIES
CMOS BIPOLAR
Low static power dissipation High static power dissipation
High i/p impedance Low i/p impedance
High noise margin Low noise margin(low voltage swing logic
High packing density Low packing density
High delay sensitivity to load Low delay sensitivity to load
Low output drive current High output drive current
Low gm(transconductance) Large gm(transconductance)
Bidirectional capability unidirectional
Nearly ideal switching device Non ideal switching device
Advantages of BiCMOS
 BiCMOS devices offer high load current sinking and sourcing is required. The high current
gain of the NPN transistor greatly improves the output drive capability of a conventional
CMOS device.
 Improved speed over purely-CMOS technology
 Lower power dissipation than purely-bipolar technology (simplifying packaging and board
requirements)
 Latchup immunity
 Flexible I/Os (i.e., TTL, CMOS or ECL compatible) BiCMOS technology is well suited for
I/O intensive applications. ECL, TTL and CMOS input and output levels can easily be
generated
DISADVANTAGE
 Costlier due to added Processing Complexity.Additional masking steps than in CMOS to
fabricate bipolar structure along with CMOS
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VLSI DESIGN
COMPARISON B/W CMOS BIPOLAR AND BiCMOS TECHNOLOGIES
CMOS BIPOLAR BiCMOS
Low static power dissipation High static power dissipation Low static power dissipation
than Bipolar
Low speed(Slow switching) High speed Faster than CMOS
Low o/p current drive High o/p current drive High o/p current drive
High i/p impedance Low i/p impedance High i/p impedance
High noise margin(high o/p
voltage swing)
Low noise margin High noise margin compared to
bipolar
Fabrication process simpler
compared to BiCMOS
Simpler fabrication Fabrication process is complex
BiCMOS Logic gates
Designed with MOS circuits to implement the logic and bipolar transistors to drive output loads.
Charactreristics of BiCMOS logic gates(write for inverter,nand and nor)
 The o/p logic levels will be god nd will be close to rail voltages
 High i/p impedance
 Low o/p impedance
 High current drive capability,occupies relatives smaller area
 High noise margin
BiCMOS invereter
BiCMOS inverter circuit consists of two bipolartransistors T1 and T2 with one nMOS T3 and one
pMOS transistor T4,both being enhancemnet mode devices.
OPERATION OF CIRCUIT
 With Vin=0 volts(GND),T3 is off so that T1 will be non conductiong.but T4 is on and
supplies current to base of T2 which will conduct and act as current source to charge load CL
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VLSI DESIGN
towards +5 VOLTS(VDD). The O/P of inverter rise +5 volts less base to emitter voltage
VBEof T2.
 With Vin=+5 volts(VDD),T4 is off so that T2 will be non conductiong.but T3 is on and
supplies current to base of T1 which will conduct and act as current sink to disccharge load
CL towards 0 VOLTS(GND). The O/P of inverter will fall to 0 volts plus saturation voltage
VCEsat from collector to emitter of T1.
 T1 AND T2 will present low impedances when turned on into saturation and load CL will be
charged or discharged rapidly.
 The o/p logic levels will be god nd will be close to rail voltages
 Inverter has High i/p impedance
 Inverter has Low o/p impedance
 Inverter has High current drive capability,occupies relatives smaller area
 Inverter has High noise margin
LIMITATIONS OF BASIC INVERETER CONFIGURATION
 Owing to presence of DC path from VDD to GND through T3 and T1 ,this is not a ood
arrangement to implement since there will be a significant static current flow whenever
Vin=logic1.
 Thre is no diharge path for current from base of either bipolar transistor when it is being
turned off.This will slow down action of circuit.
An improved BiCMOS inverter WITH NO STATIC CURRENT FLOW
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VLSI DESIGN
DC path through T3 and T1 is eliminated but o/p voltage swing is now reduced since output cannot
fall below base to emitter voltage of T1.(this o/p volt is in effect base voltage of T1 in this
arrangement.T1 wil turn off if o/p volt fall below VBE OF T1.)
Consider the simple BiCMOS inverter circuit shown in figure which consists of two MOS transistors
and two' npn-type bipolar transistors which drive a large output capacitance Cload. The operation
concept of this circuit can be very briefly summarized as follows.
The complementary pMOS and nMOS transistors MP and MN supply base currents to the bipolar
transistors and thus act as "trigger" devices for the bipolar output stage. The bipolar transistor Q 1 can
effectively pull up the output voltage in the presence of a large output capacitance, whereas Q2 pulls
down the output voltage, similar to the well-known totem pole configuration. Depending on the logic
level of the input voltage, either MN or MP can be turned on in steady state, therefore assuring a fully
complementary pushpull operation mode for the two bipolar transistors. In this very simplistic
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VLSI DESIGN
configuration, two resistors are used to remove the base charge of the bipolar transistors when they
are in cut-off mode. In this circuit resistors provide better improved o/p swing of voltage .
To reduce the turn-off times of the bipolar transistors during switching, two minimum-size nMOS
transistors (MB 1 and MB2) are usually added to provide the necessary base discharge path, instead
of the two resistors(resistors are space consuming). The resulting six-transistor inverter circuit, shown
in Fig.,below is the most widely used conventional BiCMOS inverter configuration.
Conventional BiCMOS inverter.
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VLSI DESIGN
BiCMOS NOR2(refer written notes or QP answer key)
Figure shows the circuit diagram of a BiCMOS NOR2 gate. Here, the base of the bipolar pull-up
transistor Q1 is being driven by two series-connected Pmos transistors. Therefore, the pull-up device
can be turned on only if both of the inputs are logic-low. The base of the bipolar pull-down transistor
Q2 is driven by two parallel-connected nMOS transistors. Therefore, the pull-down device can be
turned on if either one or both of the inputs are logic-high. Also, the base charge of the pull-up device
is removed by two minimum-size nMOS transistors connected in parallel between the base node and
the ground. Notice that only one nMOS transistor, MB2, is being used for removing the base charge
of Q2, when both inputs are logic-low.
BiCMOS NAND2
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VLSI DESIGN
Figure shows the circuit diagram of a BiCMOS NAND2 gate. In this case, the base of the bipolar
pull-up transistor Q I is being driven by two parallel-connected Pmos transistors. Hence, the pull-up
device is turned on when either one or both of the inputs are logic-low. The bipolar pull-down
transistor Q2, on the other hand, is driven by two series-connected nMOS transistors between the
output node and the base. Therefore, the pull-down device can be turned on only if both of the inputs
are logic-high. For the removal of the base charges of Q1 during turn-off, two series-connected nMOS
transistors are used, whereas only one nMOS transistor is utilized for removing the base charge of Q2.
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VLSI DESIGN
MODULE 5
Galium Arsenide Technology(pucknell text)
For high speed operaton in semiconductor medium three factors become significant
 Carrier mobility
 Carrier saturation velocity
 Existence of semi insulating substrate.
Ga As compound possess all these features.High speed electron mobility of gallium arsenide
with respect to silicon ,a semi insulating substrate with consequent lower parasitics a 1.4
improvement factor for carrier saturation velocity over Si,opto electrical properties and
significant improvement in power dissipation and hardness provides system performance
advantage for GaAs devices.
Ga As crystal structure
Gallium (Ga), a toxic material, is produced as a by-product in both the zinc and aluminium
production processes. Similarly, arsenic (As), which is also very toxic, is produced from ores
such as AS2S3 or AS2S4. The oxidation reaction of the ores is first entailed to produce AS2O3.
Later through the reduction with carbon, arsenic is produced.
In order to better appreciate the structure and the properties of gallium arsenide crystal, it is
better to know more about the characteristics of the individual atoms, Arsenic and Gallium.
The figure below shows Bohr’s model of the atomic structures for gallium and arsenic. For
the sake of better understanding, they are also compared with Silicon.
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VLSI DESIGN
Bohr’s Model For Si, Ga, and As
Gallium has a positively charged nucleus of +31, while the arsenic atom’s nucleus has a
positive charge of+33. In both the cases, the total positive charge of the nucleus is equalized
by the total effective negative charge of the electrons.
Electrons, travelling within their respective orbits, possess energy since they are a definite
mass in motion (that is, rest mass of electron is 9.108*10-23
gm). This means each electron in
its relationship with its parent nucleus exhibits an energy value and functions at its own
energy level. This energy level is dictated by the electron’s momentum and its physical
proximity to the nucleus. The closer the electron is to the nucleus, the greater is the holding
influence of the nucleus on the electron and the greater is the energy required for the electron
to break loose and become free.
Due to the ability of the outer orbit electrons to break loose from the parent atom, they are
known to be stronger than the inner orbit electrons. That is why, the outer orbit electrons are
also referred to as ‘valence electrons’. The outer orbit in which valence electrons exist is
called the ‘valence band’. It is the electrons from this band that are being considered in much
of the discussions in the section to follow.
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VLSI DESIGN
Crystal chemical bonds result through sharing of valence electrons. In materials such as Si,
Ga and As, the outer-shell valence configuration is shown below.
Si→3s2
3p2
Ga→4s2
4p1
As→4s2
4p3
Here the core is not shown and the superscripts denote the number of electrons in the
subshells (that is, s and p orbitals).
GaAs – A Compound Semiconductor
Gallium arsenide is a compound semiconductor which may be defined as a semiconductor
made of a compound of two elements (as opposed to silicon, which is a single element
semiconductor).
The figure below shows the arrangement of atoms in a gallium arsenide substrate material.
Note the alternate positioning of gallium and arsenic atoms in their exact crystallographic
locations. Since gallium arsenide is a binary semiconductor special care is required during the
processing to avoid high temperatures that could result in dissociation of the surface, this
being one of the basic difficulties in the growth of GaAs bulk material.
Gaas Atom Arrangement
GaAs Doping Process
Much as it is with silicon, it is necessary to introduce impurities into the semi insulating Ga
As material in order to facilitate the creation of switching devices Selection of the impurity
and its concentration density determine the behaviour of the switching clement. According to
the dopant used, both n-type and p-type material can be realized.
• n-type material
Group IV elements such as silicon can act as either donors (that is, on Ga sites) or acceptors
(that is, on As sites). Since arsenic is smaller than gallium and silicon (the covalent radius for
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VLSI DESIGN
Ga is 1.26 A and for As is 1.18 A), group IV impurities tend to occupy gallium sites. Thus,
silicon is used as the dopant for the formation of n-type material as shown in the figure
below.
The shrinkage of atomic radii across a given row of the periodic table can best be explained
by noting that in any given period, electrons are added to s and p orbitals, which are not able
to shield each other effectively from the increasing positive nuclear charge. Thus an increase
in the positive charge of the nucleus results in an increase in the effective nuclear charge,
thereby decreasing the effective, atomic radius. This is why, for example, an As atom is
smaller than a Ga atom.
N-Type-Material
• p-type material
Beryllium (Be) or magnesium (group II) can be used for the formation of p-type material.
Since Be is the lightest p-type dopant for GaAs, deep implantation of the dopant atoms can be
accompiished with relatively less lattice damage. Nevertheless, Mg is also finding its way as
a suitable dopant in a number of processes.
Energy Band Structure of Gallium Arsenide (GaAs)
One of the important characteristics that is attributed to GaAs is its superior electron mobility
brought about as the result of its energy band structure as shown in the figure below. Gallium
Arsenide (GaAs) is a direct gap material with a maximum valence band and a minimum
conduction band and is supposed to coincide in k-space at the Brillouin zone centers. In the
graph shown below, we can see that the some valleys in the band structure are narrow and
some are sharply curved. These curves and narrows differ corresponding to the electrons with
low effective mass state, while valleys that are wide with gentle curvature are characterized
by larger effective masses. The curvature that is seen in the graph of the energy versus
electron momentum profile clearly shows the effective mass of electrons travelling through
the crystal. The minimum point of gallium arsenide’s conduction band is near the zero point
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VLSI DESIGN
of crystal-lattice momentum, as opposed to silicon, where conduction band minimum occurs
at high momentum. Now, mobility, µ, depends upon
• Concentration of impurity, N
• Temperature, T
• And is also inversely related to the electron effective mass, m.
Energy Band Strucure of GaAs
For GaAs, the effective mass of these electrons is 0.067 times the mass of free electron (that
is, 0.067me, where me is the free electron rest mass). Thus the shapes in the conduction band
bring about a superior electron mobility. Due to this, the electrons travel faster in Gallium
Arsenide (GaAs) than in Silicon. However the conduction of electrons of GaAs is very similar
to that of Silicon in the higher valleys. The reason behind this is the high mass and strong
inter-valley scattering which provide very low mobility. Furthermore, Gallium Arsenide is a
direct-gap semiconductor. Its conduction band minimum occurs at the same wave vector as
the valence band maximum , which means little momentum change is necessary for the
transition of an electron from the conduction band, to the valence band. Since the probability
of photon emission with energy nearly equal to the band gap is somewhat high, GaAs makes
an excellent light-emitting diode. Silicon on the other hand, is an indirect-gap semiconductor
since the minimum associated with its conduction band is separated in momentum from the
valence band minimum. Therefore it cannot be a light-emitting device.
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VLSI DESIGN
Gallium Arsenide (GaAs) – Electron Velocity-Field Behaviour
The charge carriers in the GaAs material that is the electrons will obtain energy as soon as an
electric field [E] is applied. When the energy is obtained from the field, the electrons will also
lose certain amount of energy due to collisions that occur due to optical photon scattering
with the lattice. Thus, due to the gaining and losing of energy, the resultant balance will
either be positive or negative. If it is positive, an increase in the applied field will cause a
rapid increase in the energy and drift velocity of the charge carriers. Sometimes the resulting
balance will be equal, that is the energy gained from the applied field will become equal to
the energy lost due to collision. This will cause the drift velocity to reach a limiting value,
known as the saturation velocity, Vsat.
Gallium Arsenide (GaAs) is known to be a multi-valley semi-conductor. Thus when there is
an increase in the energy level of the lower valley electrons, the electrons tend to attain a high
temperature and become hot. The increase in energy level is normally referred to as electric
fields which are greater than almost 3500V/cm. These high temperature electrons are known
to have an upper conduction band in some regions of the electron velocity-field
characteristics. This phenomenon occurs due to the high electron effective mass. Due to this
problem, there will be a decrease in the drift velocity of the electrons. There will also be a
decrease in the number of high mobility electrons.
The region where the hot electrons occupy an upper conduction band, the drift velocity will
no longer be proportional to the electric field. But instead, it will pass through a maximum of
about 2*107 cm/sec with increasing field, and also decrease to an electric field independent
saturation value of about 1.4*107 cm/sec.
The velocity-field characteristics illustrating the three regions of interest are shown in the
figure below.
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VLSI DESIGN
Electron Velocity Field vs Electric Field Graph
For convenience of comparison, characteristics for silicon are also illustrated. From the figure
it can readily be noted that in low electric field regions, silicon has a much lower mobility
than gallium arsenide. This increases monotonically until the drift velocity saturates at a
value of about 1*107
cm/sec.
Gallium Arsenide (GaAs) – Channeling Effect
This introduces an orientation dependency that changes the properties of GaAs field effect
transistor accordingly. For example, consider a high energy ion entering a single crystal
lattice at a critical angle to the major axis of the GaAs crystal, during ion-implantation. The
ion will steer down the open directions of the lattice. This steering is called axial
channelling. Thus we can arrive at the conclusion that a random equivalent direction is not
used during ion implantation. Thus, the depth distribution will be greater than those predicted
by range statistics which are used to establish penetration depth.
The channelling effect is not as high as we think in the <100> direction when compared with
<110> direction. Many of the current GaAs wafers tend to take the <100> direction. It should
be noted that the profile difference between the aligned <100> direction implant and any
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VLSI DESIGN
other direction of implant has a major influence upon the threshold voltages of the fabricated
devices.
Comparison of silicon with gallium arsenide
Electron mobility of 6 to 7 times that of silicon resulting in very fast electron transit
times
Saturated drift velocity for GaAs and Si is approximately equal that is 1.4*10^7cm/s
and 1*10^7 cm/s respectively.For Galium arsenide saturation velocity occurs at lower
threshold field than for silicon
Large energy bandgap offers bulk semi insulating substrate with resistivitities in order
of 10^7 to 10^8 ohm.cmThis minimizes parasitic capacitances and allows easy isolation
of multiple devices in single substrate.
Radiation resistance is stronger due to the absence of gate oxide to trap charges.
A wider operating temperature is possible because of large band gap.Can with stand
temp variations in range -200 to +200 degree celcius
Direct band gp of Ga As allows efficient radiative recombination of electrons and holes
and forward biased pn junctions can act as light emitters.
Upto 70% reduction in power dissipation over fastest of silicon technology ECL.
Si
Ga AsCMOS BIPOLAR
Low dissipation High Medium
High i/p impedance Low High
High noise margin Medium Low
Medium speed High speed Very high speed
high voltage swing low volt swing low swing
High packing density Low High
high delay
sensitivitylow low
low o/p drive high o/p drive low
biderectional Unidirectional biderectional
ideal switching device not ideal switching device Reasonable
indirect band gap Indirect direct
mask levels 12-16 mask levels 12-20 mask levels 6-10
Metal Semi-conductor FET (MESFET) (pucknell text)
The gallium arsenide (GaAs) field-effect transistor (FET) is a bulk current-conduction
majority-carrier device. This device is , is fabricated from bulk gallium arsenide with the help
of high-resolution photolithography as well as ion implantation method into a semi-
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VLSI DESIGN
insulating GaAs substrate. The processing of this device is very simple as it does not need
more than 6 to 8 masking stages. The figure below is used to compare the complexity in
processing the device with the number of masks in the Y-axis and the function of time for
both silicon and gallium arsenide technologies in the X-axis.
Mesfet Evolution Process
The structure of the basic MESFET as shown in the figure below is very simple. The
MESFET has a thin n-type active region which is used to join the two ohmic contacts . A thin
metal Schottky barrier gate is used to separate the highly doped drain and source terminals.
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VLSI DESIGN
MESFET STRUCTURE (pucknell text)
GaAs MESFETs are similar to silicon MOSFETs. The major difference is the presence of a
Schottky diode at the gate region which separates two thin n-type active regions, that is,
source and drain, connected by ohmic contacts. It should be noted that both D type and E
type MESFETs, that is, ‘ON’ and ‘OFF’ devices, operate by the depletion of an existing
doped channel. This can be compared with silicon MOS devices where the E [Enhancement]
mode transistor functions by inverting the region below the gate to produce a channel, while
the D [depletion] mode device operates by doping the region under the gate slightly in order
shift the threshold to a normally ‘ON’ condition.
This similarity provides us with the basis for extending to gallium arsenic the design
methodology used so successfully in silicon to simplify circuit as system design and layout
issues.
The D-MESFET is normally ‘ON’ and its threshold voltage, Vtdep, is negative. The E-MES
FET is normally ‘OFF’ and its threshold Vtenh is positive. The threshold voltage is determined
by the channel thickness, a, and concentration density of the implanted impurity, ND. A
highly doped, thick channel exhibits a larger negative threshold voltage. By reducing the
channel thickness, and decreasing the concentration density a normally ‘ OFF’ enhancement
mode MESFET with a positive threshold voltage can be fabricated. Circuit symbols for the
depletion and enhancement mode MESFETs arc set out in the figure below.
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VLSI DESIGN
D-MESFET and E-MESFET Circuit Symbol
The MESFET has a maximum gate to source voltage V of about 0.7-0.8 volt owing to the
diode action of the Schottky diode gate. Since the principle underlying the operation of
MESFETs is based upon the behaviour of metal-semiconductor interface, we will briefly
outline some of the features that characterize such an interface.
Characteristics of Schottky Barriers
When a metal is brought into contact with a semiconductor, an electrostatic potential barrier
(referred to as Schottky barrier) is created at the interface as the result of the difference in the
work function of the two materials. To appreciate the physical nature of the barrier we can
model the interface by visualizing a situation whereby the metal is gradually brought toward
the semiconductor surface until the separation becomes zero.
As this separation between the metal-semiconductor surface is reduced, the induced charge in
the semiconductor increases, while at the same time the space charge layer widens. A greater
part of the contact potential difference begins to appear across the space charge layer within
the semiconductor. Because the carrier concentration in the metal is several orders of
magnitude larger than that in the semiconductor when the separation is brought to zero, the
entire potential drop then appears within the semiconductor itself. This is in the form of a
depletion layer situated adjacent to the metal and extending into the semiconductor.
Gallium Arsenide (GaAs) Fabrication Techniques
Various methods are used for the fabrication of Gallium Arsenide (GaAs). Out of all the
methods, the main growth technique that is used is the liquid-encapsulated Czochralski
(LEC) growth of GaAs crystals from high purified pyrolytic boron nitride (PBN) in high
pressure.
The GaAs crystals can be easily achieved from the above method as the liquid-encapsulated
Czochralski material grow in the <100> direction. As a results, round (100) wafers with very
large diameters are obtained. The wafers that are grown in the <100> orientation is usually
selected as they have semi-insulating properties and are also know to be thermally stable.
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VLSI DESIGN
Since the <110> cleavage planes are at a right angle, square chips can be obtained with a
diamond scribe and break. This means that by adhering to the <100> growth plane most of
the difficulties that occur while cutting and handling of the chips can be reduced.
The methods for making GaAs wafers is very similar to the preparation of silicon wafers.
First of all, the As- grown boules are grinded to a precise diameter and then incorporatied
with orientation flats. This is followed by the following steps.
• Wafering using a diamond ID saw
• Edge rounding
• Lapping
• Polishing
• Wafer Scrubbing
STUDY DMESFET FABRICATION AND SELF ALIGNED E/D MESFET
FABRICATION FROM (pucknell )TEXT
INTRODUCTION TO PLA
A programmable logic array (PLA) provides a regular structure for implementing
combinational logic specified in sum-of-products canonical form. Any logic function can be
expressed in sum-of-products form; i.e., where each output is the OR (sum) of the ANDs
(products) of true and complementary inputs. The inputs and their complements are called
literals. The AND of a set of literals is called a product or minterm. The outputs are ORs of
minterms. The PLA consists of an AND plane to compute the minterms and an OR plane to
compute the outputs.
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VLSI DESIGN
nxkxm PLA takes n inputs,has k no:of AND gates to compute k min terms and m OR
gates to produce m outputs.
NOR gates are particularly efficient in pseudo-nMOS and dynamic logic because they use
only parallel, never series, transistors. Hence, we use DeMorgan’s law to replace the AND
and OR gates with NORs after inverting inputs and outputs, as shown in Figure
(NOR with inverted i/p-AND
NOR with inverted o/p-OR)
eg:full adder using PLA
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VLSI DESIGN
AND/OR REPRESENATION OF PLA
DOT DIAGRAM REPRESENATION OF PLA
The most straightforward design for a small PLA uses a pseudo-nMOS NOR
gate(nMOS pull down n/w implementing logic and pMOS transistor with gate connected to
ground as pull up.
Figure shows the circuit diagram for the full adder PLA. Advantages of this PLA
include simplicity and small size. Disadvantages include the static power dissipation of the
NOR gates(due to pseudo nmos structure,pmos is always ON as its gate is grounded and if
nmos pulldown n/w is ON curren flows fromm VDD to Gnd.)
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VLSI DESIGN
NOR REPRESENTATION OF PLA is shown above
(BUBBLED AND IS EQUIVALENT TO NOR,ALL INPUTS ARE INVERTED TO EACH
BUBBLED AND.HENCE it is NOR with inverted inputs which is AND)
Pseudo nMOS PLA schematic
FPGA(Field Programmable Gate Array
FPGA chip consists of an array of logic cells surrounded by programmable routing
resources.As the name suggests, FPGAs are completely programmable even after a product is
shipped or “in the field.” Two basic versions exist. The first uses a special process option
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VLSI DESIGN
such as a fuse or antifuse to permanently program interconnect and personalize logic. These
are one-time programmable. The second type uses static RAM or flash memory to configure
routingand logic functions ie reconfigurable
Simplified FPGA floor plan
FPGA consists of
 Configurable logic blocks-consists of look up tables to implement combinational
logic functions.flipflops to implement sequential functions,and multiplexers to select
the appropriate logic function to be implemented.
 Programmabble routing structure-connection b/w clb,includes horizontal and vertical
routing channels and routing switches.
 Configurable I/O cells- can be used as input, output, or bidirectional pads
The chip is composed of an array of configurable logic blocks (CLBs). Metal routing tracks
run vertically and horizontally between the array of CLBs. These terminate at the gray
blocks, which are routing switches that can be implemented using antifuses, CMOS
transmission gates, or tristate buffers. The routing resources can also be connected to the
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VLSI DESIGN
inputs and outputs of the adjacent CLBs. CLBs use programmable lookup tables to compute
any function of several variables. Configurable I/O cells that can be used as input, output, or
bidirectional pads surround the core array of CLBs
A simple SRAM-based FPGA logic cell is shown in Figure . It is composed of a 16x1
static RAM as the logic element. This provides for any logic function of four variables
merely by loading the RAM with the appropriate contents. Table illustrates how the look up
table should be loaded to perform various logic functions. A full adder can be implemented in
two CLBs (one for carry and one for sum). The CLB shown also provides
an optional output register(sequential element).
RAM CLB
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VLSI DESIGN
MODEL QUESTIONS
Module 1
1. Explain the process of epitaxial growth.
2. Discuss how ion implantation is done.
3. Explain in detail the diffusion process. Discuss the physical mechanism and laws
governing this process.
4. Discuss the various ways in which lithography can be performed.
5. What is meant by dry oxidation ?
6. Explain the physical mechanism of diffusion of impurities. Also state and explain
Flick's I and II law of diffusion.
7. Discuss about : (i) Chemical vapour deposition. (ii) Metallisation.
8. List the various steps involved in the monolitic circuit fabrication and explain with
the help of diagrams.
9. Compare Si and Ge as raw materials for IC fabricator.
10. Write a note on wire bonding.
11. Explain the epitaxial growth process. What are its features?
12. Explain ion implantation. What are its advantages?
13. What is meant by wet oxidation ?
14. Discuss about the following with reference to diffusion of Impurities
(i) Complementary error function.
(ii) Gaussian Distribution profile.
iii) Diffusion coefficients.
15. Explain the following : -
(i) Photolithography.
(ii) Electron beam and X-ray lithography.
16. Compare electron beam lithography and X-ray lithography ?
17. Explain Czochralski process ? What are its advanteges?
18. Explain different printing techniques in lithography ?
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VLSI DESIGN
19. State Ficks II law of diffusion.
20. Explain about lithography.
21. Explain about Fine line lithography.
22. Explain the steps in a Silicon wafer preparation. Discuss the Czochralski process.
23. Explain the chemical wafer deposition process with the help of diagram showing the
equipment.
24. Explain the following terms : (i) Patterning and (ii) Wire bonding.
25. What is the role of epitaxy in IC fabrication
26. Explain the advantage of ion implantation over diffusion
27. What are the functions of oxide layer
28. Why aluminium is the best choice for metalization
29. What is the relevance of fineline lithograthy over optical lithography
30. Expain annealing techniques
31. Expalin ion impalntatyion sytem.What are its advantages and disadvaantges.
32. Explain diffusion mechanisms.
33. Give an account of epitaxial reactors.
34. Explain in detail wafer preperation process.
35. Explain photolithography.
36. Explain CVD techiques.
37. Give an account of tin oxide growth and factors that affect oxidation
Module 2
1. Discuss a construction of Schottky diodes and transistors.
2. Explain the PMOS and NMOS fabrication techniques.
3. Mention the need for isolation
4. List the advantages of using polysilicon as gate material in MOS transistors.
5. With the help of diagram, explain the fabrication steps for a silicon gate nMOS
transistor.
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VLSI DESIGN
6. Write a note on vias.
7. Write a note on monolithic resistors.
8. Explain Si gate technology. Compare it with metal gate technology.
9. Explain the different techniques for the isolation of components in IC fabrication.
10. Explain the fabrication steps in a BiCMOS process.
11. Name the different isolation methods.
12. How capacitor can be produced in monolithic integrated circuits ?
13. Discuss about : (i) Monolithic resistor. (ii) Monolithic capacitor
14. Write a note on junction isolation.
15. Write a note on Schottky diodes.
16. Explain how threshold voltage of a MOS transistor can be controlled ?
17. Discuss the differences and similarities between FET, JFET and MOSFET.
18. What is the need for an isolation ? Explain junction isolation.
19. How MOS resistors and capacitors are fabricated ? Explain.
20. Compare dielectric isolation with PN junction isolation
21. What is the role of IC cross overs and vias
22. What is sheet resistance
23. Compare nMOS technology over pMOS
24. Give an account of schottky transistor.
25. Give an account of JFET structure.
Module 3
1. Using a diagram show the CMOS logic implementation using NOR
2. Show the fabrication of an inverter using CMOS technology
3. Explain the working of a serial shifter and discuss its design.
4. What are latch up ? What is its effect on the chip ?
5. Draw the diagram of CMOS NAND gate.
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VLSI DESIGN
6. Draw the CMOS NAND gate circuit and its stick diagram and explain.
7. Write a note on stick diagrams.
8. Describe the n-well C-MOS process steps with the help of diagram.
9. Design a two input CMOS NAND gate ?
10. Explain the VTC of an inverter.
11. Draw and explain the operation of a CMOS NAND gate.
12. Sketch stickdiagram of a 3 input CMOS NAND gate.
13. Draw the stick diagram of a typical CMOS circuit and explain its operation.
14. With a circuit diagram, explain the operation of a basic CMOS 2 input NOR gate.
15. What is stick diagram.Give an acount of stick diagram repesentaion of CMOS
circuits
16. What is the advantage of CPL over convention CMOS logic
17. Expalin basic operation of transmission gate.
18. Draw the stick diagram of a) 3 input NAND b)3 input NOR
19. Explain Latch up in CMOS structures.How can you prevent latch up
20. Implent 2 input XOR using transmission gate.
21. Implement a 4x1 mux using transmission gate
22. Implement 2 input a)XOR and b)XNOR in CMOS logic
23. Implement complex logic circuits using CMOS logic
Y=(A+B+C).D+E
Y=(A.B.C)+D.E
24. Draw the stick diagram of the circuit given by Y=AB+C
25. Explain in detail CMOS structure
26. Design full adder using CMOS logic with minimum no:of transistors.
27. Design CPL a)NAND b)NOR c)XOR
28. Explain 4 bit shifter.
Module 4
1. Write a brief note on scaling of MOS structures
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VLSI DESIGN
2. Discuss the BiCMOS fabrication steps and the circuit design process
3. State the principle of scaling
4. Discuss about BiCMOS technology.
5. Write a note on Bi CMOS logic.
6. List the names of at least 4 CMOS technologies.
7. Draw the BiCMOS' NAND gate circuit with n-p-n pull-down and nMOS pull-down
and explain
8. Draw the BiCMOS inverter circuit.
9. Explain the following : (i) CMOS inverter ; (ii) Pseudo NMOS inverter.
10. Explain the fabrication process of BiCMOS inverter circuit with neat diagram
11. Compare various logic family
12. Expalin D-Latch circuit.
13. Compare BiCMOS with CMOS and bipolar technology.
14. Explain CMOS implemnetation of SR Flip flop.
15. Explain CMOS implemnetation JK flip flop.
16. Compare BiCMOS with CMOS and bipolar technology.
17. What is scaling .What are its limitations
18. Give an account of scaling of MOSFETS and effect of miniaturisation.
19. Give an account of CMOS logic systems.
20. Explain a)BiCMOS Inverter b)BiCMOS NAND c)BiCMOS NOR
Module 5
1. Discuss the principles'specific to GaAs fabrication
2. Explain the crystal structure of GaAs using diagrams
3. Explain the doping process in Gallium Arsenide technology.
4. Explain the channelling effect and how it affects the fabrication process.
5. Compare the basic structure of GaAs MESFET with silicon MOSFET.
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VLSI DESIGN
6. Draw the structure of metal gate depletion mode MESFET and explain
7. Explain the self aligned gate E/D process in detail.
8. Write a note on the features of GaAs technology.
9. Explain the working of a MESFET.
10. Explain the fabrication steps in GaAs technology.
11. Compare CMOS and GaAs technology.
12. Explain channeling effect.
13. Give an account of PLA
14. Compare Silicon and Ga AS technology.
15. Give an account of FPGA
............................................................................................................................
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