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VLSI DESIGN
Reference Material
By
Verilog Course Team
Where Technology and Creativity Meet

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Revision: 1
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Due care and diligence has been taken while editing of this material. Verilog
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statutory, including to fitness for a particular purpose and freedom from
computer virus, is given with respect to the contents of this material or its
hyperlinks to other Internet resources. The material acts as just a reference to
move forward and understand the concept. Reference in this material to any
specific commercial products, processes, or services, or the use of any trade,
firm or corporation name is for the information, and does not constitute
endorsement, recommendation, or favoring.

About Verilog Course Team
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Preface
The India Semiconductor Association (ISA), an Indian semiconductor
industry organization, has briefed growth, trends and forecasts for the Indian
semiconductor market in collaboration with a U.S. consulting company Frost
& Sullivan.
The report titled as "ISA-Frost & Sullivan 2007/2008 Indian Semiconductor
Market Update."
According to the report, total semiconductor consumption in India (total value
of semiconductors used for devices marketed in India) was $2.69 billion
(USD) in 2006. The $2.69 billion represents 1.09% of the global
semiconductor market. Of the total semiconductor consumption in India,
consumption by local Indian set manufacturers accounted for $1.26 billion.
The overall Indian semiconductor consumption will grow at an average rate of
26.7% per year in 2006 through 2009. Based on the actual consumption in
2006, the overall Indian semiconductor consumption is forecast to be $5.49
billion in 2009. This represents 1.62% of the global semiconductor market in
2009.
Semiconductor consumption by local Indian set manufacturers is predicted to
increase at 35.8% per year in 2006 through 2009 and amount to $3.18 billion
in 2009.
This material is the result of the Verilog Course Team’s practical experience
both in Design/Verification and Training. Many of the examples illustrated
throughout the material are real designs models. With Verilog Course Team’s
training experience has led to step by step presentation, which addresses
common mistakes and hard-to-understand concepts in a way that eases
learning.
Verilog Course Team invites suggestion and feedbacks from both students and
faculty community to improve the quality, content and presentation of the
material.

VLSI DESIGN
Verilog Course Team www.verilogcourseteam.com
Dream IT, We make U to Deliver
UNIT-I CMOS TECHNOLOGY
1. An overview of silicon semiconductor technology 1
1.1 The Fabrication of a Semiconductor Device 1
1.1.2 Wafer Fabrication 2
1.1.3 Assembly 6
1.2 Basic CMOS Technology 8
1.2.1 A Basic n-well CMOS Process 9
1.2.2 A Basic p-well CMOS Process 13
1.2.3 Twin-Tub (Twin-Well) CMOS Process 13
1.2.4 Silicon On Insulator (SOI) Process 14
1.3 INTERCONNECT 18
1.3.1 Metal Interconnect 18
1.3.2 Polysilicon/Refractory Metal Interconnect 19
1.3.3 Local Interconnect 20
1.4 CIRCUIT ELEMENTS 21
1.4.1 Resistors 21
1.4.2 Capacitors 21
1.4.3 Electrically Alterable ROMs 23
1.4.4 Bipolar Transistors 24
1.4.5 LatchUp 26
1.4.5.1 The Physical Origin of Latchup 26
1.4.5.2 Latchup Triggering 28
1.4.6 Latchup Prevention 29
1.5. LAYOUT DESIGN RULES 30
1.5.1 Layer Representations 31
1.5.2 CMOS n-well Rules 32
1.5.3 Scribe Line 34

VLSI DESIGN
1.5.4 SOI Rules 34
1.5.5 Layer Assignments 35
1.6 PHYSICAL DEISGN 35
1.6.1 Basic Concept 35
1.6.2 CAD Tools sets 37
1.6.3 Physical Design-The Inverter 38
1.6.4 Physical Design-The NOR 38
1.6.5 Physical Design-The NAND 39
1.7 DESIGN STRATEGIES 39
1.7.1 Structured Design Strategies 40
1.7.2 Hierarchy 40
UNIT 2 MOS TRANSISTOR THEORY
2 .1 NMOS ENHANCEMENT TRANSISTOR 41
2.2 PMOS ENHANCEMENT TRANSISTOR 45
2.3 THRESHOLD VOLTAGE 45
2.3.1 Threshold Voltage Equations 46
2.4 BODY EFFECT 48
2.5 MOS Device Design Equations 48
2.5.1 Basic DC Equations 48
2.5.2 Second Order Effects 50
2.5.2.1 Threshold Voltage-Body Effect 51
2.5.2.2 Subthreshold Region 51
2.5.2.3 Channel-length Modulation 52
2.5.2.4 Mobility Variation 52
2.6 MOS MODELS 53
2.7 SMALL SIGNAL AC CHARACTERISTICS 54

VLSI DESIGN
2.8THE COMPLEMENTARY CMOS INVERTER –
DC CHARACTERISTICS 55
2.8.1 βn/βp ratio 61
2.8.2 Noise Margin 62
2.9 THE TRANSMISSION GATE 64
2.10 THE TRISTATE INVERTER 68
UNIT 3 SPECIFIFCATION OF VERILOG HDL
3. HISTORY OF VERILOG 69
3.1 BASIC CONCEPTS 69
3.1.1 Hardware Description Language 69
3.1.2 VERILOG Introduction 69
3.1.3 VERILOG Features 70
3.1.4 Design Flow 70
3.1.5 Design Hierarchies 73
3.1.5.1 Bottom up Design 73
3.1.5.2 Top-Down Design 74
3.1.6 Lexical Conventions 74
3.1.6.1 Whitespace 75
3.1.6.2 Comments 75
3.1.6.3 Identifiers and Keywords 76
3.1.6.4 Escaped Identifiers 76
3.1.7 Numbers in Verilog 76
3.1.7.1 Integer Numbers 77
3.1.7.2 Real Numbers 77
3.1.7.3 Signed and Unsigned Numbers 77
3.1.8 Strings 78
3.1.9 Data types 79

VLSI DESIGN
3.1.9.1 Data Types Value set 79
3.1.9.2 Nets 79
3.1.9.3 Vectors 80
3.1.9.4 Integer, Real and Time Register Data Types 80
3.1.9.5 Arrays 81
3.1.9.6 Memories 82
3.1.9.7 Parameters 82
3.1.9.8 Strings 82
3.2 MODULES 83
3.2.1 Instances 84
3.3 PORTS 84
3.3.1 Port Declaration 85
3.3.2 Port Connection Rules 85
3.3.3 Ports Connection to External Signals 86
3.4 GATE DELAYS 87
3.4.1 Rise, Fall, and Turn-off Delays 87
3.4.2 Min/Typ/Max Values 88
3.5 MODELING CONCEPTS 89
3.6 SWITCH LEVEL MODELING 90
3.6.1 Switch level primitives 91
3.6.2 MOS switches 92
3.6.3 CMOS Switches 93
3.6.4 Bidirectional Switches 94
3.6.5Power and Ground 95
3.6.6 Resistive Switches 95
3.8 Delay Specification on Switches 96
3.8.1 MOS and CMOS switches 96
3.8.2 Bidirectional pass switches 97

VLSI DESIGN
3.9 GATE LEVEL MODELING 101
3.9.1 Gate Types 101
3.10 BEHAVIORAL AND RTL MODELING 108
3.10.1 Operators 108
3.10.1.1 Arithmetic Operators 108
3.10.1.2 Relational Operators 109
3.10.1.3 Bit-wise Operators 110
3.10.1.4 Logical Operators 112
3.10.1.5 Reduction Operators 113
3.10.1.6 Shift Operators 114
3.10.1.7 Concatenation Operator 115
3.10.1.8 Replication Operator 116
3.10.1.9 Conditional Operator 116
3.10.1.10 Equality Operators 117
3.10.2 Operator Precedence 119
3.10.3 Timing controls 119
3.10.3.1 Delay-based timing control 119
3.10.3.2 Event based timing control 122
3.10.3.3 Level-Sensitive Timing Control 124
3.10.4 Procedural Blocks 124
3.10.5 Procedural Assignment Statements 125
3.10.6 Procedural Assignment Groups 126
3.10.7 Sequential Statement Groups 128
3.10.8 Parallel Statement Groups 128
3.10.9 Blocking and Nonblocking assignment 129
3.10.10 assign and deassign 130
3.10.11 force and release 131
3.10.12 Conditional Statements 131

VLSI DESIGN
3.10.12.1 The Conditional Statement if-else 131
3.10.12.2 The Case Statement 132
3.10.12.3 The casez and casex statement 134
3.10.13 Looping Statements 136
3.10.13.1 The forever statement 136
3.10.13.2 The repeat statement 136
3.10.13.3 The while loop statement 137
3.10.13.4 The for loop statement 138
3.11 DATA FLOW MODELING AND RTL 139
3.11.1 Continuous Assignment Statements 139
3.11.2 Propagation Delay 141
3.12 STRUCTURAL GATE LEVEL DESCRIPTION 141
3.12.1 2 to 4 Decoder 141
3.12.2 Comparator 142
3.12.3 Priority Encoder 144
3.12.4 D-latch 144
3.12.5 D Flip Flop 145
3.12.6 Half adder 145
3.12.7 Full adder 146
3.12.8 Ripple Carry Adder 146
UNIT 4 CMOS CHIP DESIGN
4.1 INTRODUCTION TO CMOS 148
4.2 LOGIC DESIGN WITH CMOS 149
4.2.1 COMBITIONAL LOGIC 149
4.2.2 INVERTER 150
4.2.3 The NAND Gate 151
4.2.4 The NOR Gate 152

VLSI DESIGN
4.3 TRANSMISSION GATES 153
4.3.1Multiplexers 153
4.3.2 Lathes 153
4.4 CMOS CHIP DESIGN OPTIONS 154
4.4.1 ASIC 154
4.4.2 Uses of ASICs 155
4.4.3 Full Custom ASICs 155
4.4.5 Semi-Custom ASICs 156
4.4.6 Standard- Cell-Based ASIC 156
4.4.7 Gate Array Asic 157
4.4.8 Channeled Gate Array 158
4.4.9 Channelless Gate Array 158
4.4.10 Structured Gate Array 159
4.5 PROGRAMMABLE LOGIC 159
4.5.1 Programmable Logic Structures 160
4.5.2 Programmable of PALs 161
4.5.3 Fusible Links 161
4.5.4 UV-erasable EPROM 161
4.5.5 EEPROM 161
4.5.6 Programmable Interconnect 162
4.6 ASIC DESIGN FLOW 163
UNIT-5 CMOS TEST METHODS
5.1 THE NEED FOR TESTING 165
5.1.1 Functionality Tests 166
5.2 MANUFACTURING TEST PRINCIPLS 166
5.2.1 FAULT MODELS 167
5.2.1.1 Stuck-At-Faults 167

VLSI DESIGN
5.2.1.2 Short-Circuit and Open-Circuit Faults 168
5.2.2 Observability 170
5.2.3 Controllability 171
5.2.4 Fault Coverage 171
5.2.5 Automatic Test Pattern Generation (Atpg) 171
5.2.6 Fault Grading And Fault Simulation 177
5.2.7 Delay Fault Testing 178
5.2.8 Statistical Fault Analysis 179
5.2.9 Fault Sampling 180
5.3 DESIGN STRATEGIES FOR TEST 180
5.3.1 Design for Testability 180
5.3.2 Ad-Hoc Testing 181
5.3.3 Scan-Based Test Techniques 184
5.3.3.1 Level Sensitive Scan Design (LSSD) 185
5.3.3.2 Serial Scan 187
5.3.3.3 Partial Serial Scan 188
5.3.3.4 Parallel Scan 190
5.3.4 Self-Test Techniques 191
5.3.4.1 Signature Analysis and BILBO 191
5.3.4.2 Memory Self-Test 193
5.3.4.3 Iterative logic array testing 194
5.3.5 IDDQ testing 194
5.4 CHIP-LEVEL TEST TECHNIQUES 194
5.4.1 Regular Logic Array 194
5.4.2 Memories 195
5.4.3 Random Logic 196
5.5 SYSTEM-LEVEL TEST TECHNIQUES 196
5.5.1 Boundary Scan 196

VLSI DESIGN
5.5.1.1 Introduction 196
5.5.1.2 The Test Access Port (TAP) 197
5.5.1.3 The Test Architecture 197
5.5.1.4 The TAP controller 198
5.5.1.5 The Instruction Register (IR) 198
5.5.1.6 Test-Data Registers 199
5.5.1.7 Boundary Scan Registers 199

VLSI DESIGN CMOS TECHNOLOGY
Dream IT, We make U to Deliver 1
UNIT-I
An overview of silicon semiconductor technology
Silicon in its pure or intrinsic state is a semiconductor, having a bulk electrical
resistance somewhere between that of a conductor and an insulator. The
conductivity of silicon can be varied over several orders of magnitude by
introducing impurity atoms onto silicon crystal lattice. These dopants may either
supply free electrons or holes. Impurity elements that use electrons are referred to
as acceptors, since they accept some of the electrons already in the silicon,
leaving vacancies or holes. Similarly, donor elements provide electrons. Silicon
that contains a majority of donors is known as n-type and that which contains a
majority are brought together, the region where the silicon changes from n-type
and p-type materials are brought together, the region where the silicon changes
from n-type to p-type is called a junction. By arranging junctions in certain
physical structures and combining these with other physical structures, various
semiconductor devices may be constructed. Over the years, silicon semiconductor
processing has evolved sophisticated techniques for building these junctions and
other structures having special properties.
An integrated circuit is a small but sophisticated device implementing several
electronic functions. It is made up of two major parts: a tiny and very fragile
silicon chip (die) and a package which is intended to protect the internal silicon
chip and to provide users with a practical way of handling the component. The
various steps in manufacturing processes of transistor both in “front-end” and
“back-end” is taken as example, because it uses the MOS technology. Actually,
this technology is used for the majority of the ICs manufacturing companies.
1.1 The Fabrication of a Semiconductor Device
The manufacturing phase of an integrated circuit can be divided into two steps.
The first, wafer fabrication, is the extremely sophisticated and intricate process of
manufacturing the silicon chip. The second, assembly, is the highly precise and
automated process of packaging the die. Those two phases are commonly known
as “Front-End” and “Back-
end”. They include two test steps:
• Wafer probing and Final test.
The flow chart is shown in figure 1.1.

Figure 1.1 Manufacturing Flow Chart of an Integrated Circuit
1.1.2 Wafer Fabrication (Front-End)
Identical integrated circuits, called die, are made on each wafer in a multi-step
process. Each
step adds a new layer to the wafer or modifies the existing one. These layers form
the elements of the individual electronic circuits. The main steps for the
fabrication of a die are summarized in the following table. Some of them are
repeated several times at different stages of the process. The order given here
doesn't reflect the real order of fabrication process.
PhotoMasking
This step shapes the different components. The
principle is quite simple (see drawing on next page).
Resin is put down on the wafer which is then exposed
to light through a specific mask. The lighten part of
the resin softens and is rinsed off with solvents
(developing step).
Etching
This operation removes a thin film material. There are
two different methods: wet (using a liquid or soluble
compound) or dry (using a gaseous compound like
oxygen or chlorine).
Diffusion
This step is used to introduce dopants inside the
material or to grow a thin oxide layer onto the wafer.
Wafers are inserted into a high temperature furnace
(up to 1200 ° C) and doping gazes penetrate the
silicon or react with it to grow a silicon oxide layer.

Ionic
Implantation
It allows to introduce a dopant at a given depth into
the material using a high energy electron beam.
Metal
Deposition
It allows the realization of electrical connections
between the different cells of the integrated circuit
and the outside. Two different methods are used to
deposit the metal: evaporation or sputtering.
Passivation
Wafers are sealed with a passivation layer to prevent
the device from contamination or moisture attack.
This layer is usually made of silicon nitride or a
silicon oxide composite.
Back-lap
It’s the last step of wafer fabrication. Wafer thickness
is reduced (for microcontroller chips, thickness is
reduced from 650 to 380 microns), and sometimes a
thin gold layer is deposited on the back of the wafer.
Initially, the silicon chip forms part of a very thin (usually 650 microns), round
silicon slice: the raw wafer. Wafer diameters are typically 125, 150 or 200 mm (5,
6 or 8 inches). However raw pure silicon has a main electrical property: it is an
isolating material. So some of the features of silicon have to be altered, by means
of well controlled processes. This is obtained by "doping" the silicon.
Dopants (or doping atoms) are purposely inserted in the silicon lattice, hence
changing the features of the material in predefined areas: they are divided into
“N” and “P” categories representing the negative and positive carriers they hold.
Many different dopants are used to achieve these desired features: Phosphorous,
Arsenic (N type) and Boron (P type) are the most frequently used ones.
Semiconductors manufacturers purchase wafers predoped with N or P impurities
to an impurity level of.1 ppm (one doping atom per ten million atoms of silicon).
There are two ways to dope the silicon. The first one is to insert the wafer into a
furnace. Doping gases are then introduced which impregnate the silicon surface.
This is one part of the manufacturing process called diffusion (the other part being
the oxide growth). The second way to dope the silicon is called ionic
implantation. In this case, doping atoms are introduced inside the silicon using an
electron beam. Unlike diffusion, ionic implantation allows to put atoms at a given
depth inside the silicon and basically allows a better control of all the main

parameters during the process. Ionic implantation process is simpler than
diffusion process but more costly (ionic implanters are very expensive machines).
Figure 1.2 Diffusion and Ionic Implantation Processes
PhotoMasking (or masking) is an operation that is repeated many times during
the process. This operation is described in figure 1.3. This step is called
photomasking because the wafer is “masked” in some areas (using a specific
pattern), in the same way one “masks out” or protects the windscreens of a car
before painting the body. But even if the process is somewhat similar to the
painting of a car body, in the case of a silicon chip the dimensions are measured
in tenth of microns. The photoresist will replicate this pattern on the wafer. The
exposed part of the photoresist is then rinsed off with a solvent (usually
hydrofluoric or phosphoric acid).
Figure 1.3 Photo Masking Process
Metal deposition is used to put down a metal layer on the wafer surface. There
are two ways to do that. The process shown in the figure 1.4, is called sputtering.
It consists first in creating a plasma with argon ions. These ions bump into the
target surface (composed of a metal, usually aluminium) and rip metal atoms from
the target. Then, atoms are projected in all the directions and most of them
condense on the substrate surface.

Figure 1.4 Metal Deposition Process
Etching process is used to etch into a specific layer the circuit pattern that has
been defined during the photomasking process. Etching process usually occurs
after deposition of the layer that has to be etched. For instance, the poly gates of a
transistor are obtained by etching the poly layer. A second example is the
aluminium connections obtained after etching of the aluminum layer.
Figure 1.5 Etching Process
Photomasking, ionic implantation, diffusion, metal deposition, and etching
processes are repeated many times, using different materials and dopants at
different temperatures in order to achieve all the operations needed to produce the
requested characteristics of the silicon chip. The resolution limit (minimal line
size inside the circuit) of current technology is 0.35 microns. Achieving such
results requires very sophisticated processes as well as superior quality levels.
Backlap is the final step of wafer fabrication. The wafer thickness is reduced
from 650 microns to a minimum of 180 microns (for smartcard products).
Wafer fabrication takes place in an extremely clean environment, where air
cleanliness is one million times better than the air we normally breathe in a city,
or some orders of magnitude better than the air in a heart transplant operating
theatre. Photomasking, for example, takes place in rooms where there’s maximum

one particle whose diameter is superior to 0.5 micron (and doesn’t exceed 1
micron) inside one cubic foot of air.
All these processes are part of the manufacturing phase of the chip itself. Silicon
chips are grouped on a silicon wafer (in the same way postage stamps are printed
on a single sheet of paper) before being separated from each other at the
beginning of the assembly phase.
Wafer Probing. This step takes place between wafer fabrication and assembly. It
verifies the functionality of the device performing thousands of electrical tests, by
means of special microprobes. Wafer probing is composed of two different tests:
1. Process parametric test: This test is performed on some test samples and
checks the wafer fabrication process itself.
2. Full wafer probing test: This test verifies the functionality of the finished
product and is performed on all the dies. The bad dies are automatically marked
with a black dot so they can be separated from good die after the wafer is cut. A
record of what went wrong with the non-working die is closely examined by
failure analysis engineers to determine where the problem occurred so that may be
corrected. The percentage of good die on an individual wafer is called its yield.
Figure 1.6 Description of the Wafer Probing Operation
1.1.3 Assembly (Back-End)
Figure 1.7

The first step of assembly is to separate the silicon chips: this step is called die
cutting (figure 1.7). Then, the dies are placed on a lead frame: the “leads” are the
chip legs (which will be soldered or placed in a socket on a printed circuit board.
On a surface smaller than a baby's fingernail we now have thousands (or millions)
of electronic components, all of them interconnected and capable of implementing
a subset of a complex electronic function. At this stage the device is completely
functional, but it would be impossible to use it without some sort of supporting
system. Any scratch would alter its behavior (or impact its reliability), any shock
would cause failure. Therefore, the die must be put into a ceramic or plastic
package to be protected from the external world.
Figure 1.8 Description of The Assembly Process
Figure 1.9 Wire Bonding
Wires thinner than a human hair (for microcontrollers the typical value is 33
microns) are required to connect chips to the external world and enable electronic
signals to be fed through the chip. The process of connecting these thin wires
from the chip’s bond pads to the package lead is called wire bonding.
The chip is then mounted in a ceramic or plastic package. The package not only
protects the chip from external shocks, but also makes the whole device easier to
handle. These packages come in a variety of shapes and sizes depending on the
die itself and the application in which it will be used.

Figure 1.10 Wire Bonding Operation
Products are then marked with a “traceability code” which is used by the
manufacturer and the user to identify the function of the device (and its date of
fabrication). At the end of the assembly process, the integrated circuit is tested by
automated test equipment. Only the integrated circuits that passed the tests will be
packed and shipped to their final destination.
Figure 1.11 Different Kinds of Plastic Packages
1.2 Basic CMOS Technology
Complementary metal–oxide–semiconductor (CMOS) (pronounced "see-
moss), is a major class of integrated circuits. CMOS technology is used in
microprocessors, microcontrollers, static RAM, and other digital logic circuits.
CMOS technology is also used for a wide variety of analog circuits such as image
sensors, data converters, and highly integrated transceivers for many types of
communication. Frank Wanlass got a patent on CMOS in 1967 (US Patent
3,356,858).

CMOS is also sometimes referred to as complementary-symmetry metal–
oxide–semiconductor. The words "complementary-symmetry" refer to the fact
that the typical digital design style with CMOS uses complementary and
symmetrical pairs of p-type and n-type metal oxide semiconductor field effect
transistors (MOSFETs) for logic functions.
Two important characteristics of CMOS devices are high noise immunity and low
static power consumption. Significant power is only drawn when the transistors in
the CMOS device are switching between on and off states. Consequently, CMOS
devices do not produce as much waste heat as other forms of logic, for example
transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices
without p-channel devices. CMOS also allows a high density of logic functions on
a chip.
The four main CMOS technologies are;
• n-well process.
• p-well process.
• twin-tub process.
• Silicon on insulator.
1.2.1 A Basic n-well CMOS Process
The basic process steps for pattern transfer through lithography, and having gone
through the fabrication procedure of a single n-type MOS transistor, the
generalized fabrication sequence of n-well CMOS integrated circuits, as shown in
figure. 1.12 In the following figures, some of the important process steps involved
in the fabrication of a CMOS inverter will be shown by a top view of the
lithographic masks and a cross-sectional view of the relevant areas. The n-well
CMOS process starts with a moderately doped (with impurity concentration
typically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer
is grown on the entire surface. The first lithographic mask defines the n-well
region. Donor atoms, usually phosphorus, are implanted through this window in
the oxide.
Figure 1.12

Once the n-well is created, the active areas of the nMOS and pMOS transistors
can be defined. Figures 1.13 through 1.18 illustrate the significant milestones that
occur during the fabrication process of a CMOS inverter.
Following the creation of the n-well region, a thick field oxide is grown in the
areas surrounding the transistor active regions, and a thin gate oxide is grown on
top of the active regions. The thickness and the quality of the gate oxide are two
of the most critical fabrication parameters, since they strongly affect the
operational characteristics of the MOS transistor, as well as its long-term
reliability.
Polysilicon Gate Connections
Figure 1.13
The polysilicon layer is deposited using chemical vapor deposition (CVD) and
patterned by dry (plasma) etching. CVD Chemical Reactions
• SiH4(gas) + O2(gas) Î SiO2(solid) + 2H2 (gas)
• SiH4(gas) + H2(gas) +SiH2(gas) Î 2H2(gas) + PolySilicon (solid)
•
Figure 1.14

Isolation layer
Figure 1.15
The created polysilicon lines will function as the gate electrodes of the nMOS and
the pMOS transistors and their interconnects. Also, the polysilicon gates act as
self-aligned masks for the source and drain implantations that follow this step.
Using a set of two masks, the n+ and p+ regions are implanted into the substrate
and into the n- well, respectively. Also, the ohmic contacts to the substrate and to
the n-well are implanted in this process step.
Figure 1.16
An insulating silicon dioxide layer is deposited over the entire wafer using CVD.
Then, the contacts are defined and etched away to expose the silicon or
polysilicon contact windows. These contact windows are necessary to complete
the circuit interconnections using the metal layer, which is patterned in the next
step.
Figure 1.17

Metal (aluminum) is deposited over the entire chip surface using metal
evaporation, and the metal lines are patterned through etching.
Figure 1.18
Since the wafer surface is non-planar, the quality and the integrity of the metal
lines created in this step are very critical and are ultimately essential for circuit
reliability. The composite layout and the resulting cross-sectional view of the
chip, showing one nMOS and one pMOS transistor (built-in n-well), the
polysilicon and metal interconnections. The final step is to deposit the passivation
layer (for protection) over the chip, except for wire-bonding pad areas. The
patterning process by the use of a succession of masks and process steps is
conceptually summarized in Figure. 1.19. It is seen that a series of masking steps
must be sequentially performed for the desired patterns to be created on the wafer
surface. An example of the end result of this sequence is shown as a cross-section
on the right.
Figure 1.19

1.2.2 A Basic p-well CMOS Process
N-well processes have emerged in popularity in recent years. Prior to this p-well
process was one of the most commonly available forms of CMOS. Typical p-well
fabrication steps are similar to an n-well process, except that a p-well is
implemented rather than an n-well. The first masking step defines the p-well
regions. This is followed by a low-dose boron implant driven in by a high-
temperature step for the formation of the p-well. The well depth is optimized to
ensure against n-substrate to n+ diffusion breakdown, without compromising p-
well to p+ separation.
The next steps are to define the devices and other; to grow field oxide; contact
cuts; and metallization. A p-well mask is used to define the p-channel transistors
and Vss contacts. Alternatively, an n-plus mask to define the n-channel
transistors, because the masks usually are the complement of each other. P-well
process are preferred in circumstances where the characteristics of the n- and p-
transistors are required to be more balanced than that achievable in an n-well
process. Because the transistor that resides in the native substrate tends to have
better characteristics, the p-well process has better p devices than an n-well
process. Because p-devices inherently have lower gain than n-devices, the n-well
process exacerbates this difference while a p-well process moderates the
difference.
1.2.3 Twin-Tub (Twin-Well) CMOS Process
Twin-tub technology provides the basis for separate optimization of the nMOS
and pMOS transistors, thus making it possible for threshold voltage, body effect
and the channel transconductance of both types of transistors to be tuned
independently. Generally, the starting material is a n+ or p+ substrate, with a
lightly doped epitaxial layer on top. This epitaxial layer provides the actual
substrate on which the n-well and the p-well are formed.
Figure 1.20 Twin-well CMOS process cross section
Since two independent doping steps are performed for the creation of the well
regions, the dopant concentrations can be carefully optimized to produce the
desired device characteristics. The aim of epitaxy is to grow high-purity silicon

layers of controlled thickness with accurately determined dopant concentration
distributed homogenously throughout the layer.
The electrical properties of this layer are determined by the dopant and its
concentration in the silicon. The process sequence, which is similar to the n-well
process apart from the tub formation where both p-well and n-well are utilized,
entails the following steps,
• Tub formation.
• Thin-oxide construction.
• Source and drain implantations.
• Contact cut definition.
• Metallization.
In the conventional n-well CMOS process, the doping density of the well region is
typically about one order of magnitude higher than the substrate, which, among
other effects, results in unbalanced drain parasitics. The twin-tub process (figure
1.20) also avoids this problem.
1.2.4 Silicon On Insulator (SOI) Process
Silicon on insulator technology (SOI) refers to the use of a layered silicon-
insulator-silicon substrate in place of conventional silicon substrates in
semiconductor manufacturing, especially microelectronics, to reduce parasitic
device capacitance and thereby improve performance. SOI-based devices differ
from conventional silicon-built devices in that the silicon junction is above an
electrical insulator, typically silicon dioxide or (less commonly) sapphire. The
choice of insulator depends largely on intended application, with sapphire being
used for radiation-sensitive applications and silicon oxide preferred for improved
performance and diminished short channel effects in microelectronics devices.
The insulating layer and topmost silicon layer also vary widely with application.
The first implementation of SOI was announced by IBM in August 1998. Rather
than using silicon as the substrate, the technologies have sought to use an
insulating substrate to improve process characteristics such as latchup and speed.
Hence the emergence of Silicon On Insulator (SOI) technologies. SOI CMOS
processes have several potential advantages over the traditional CMOS
technologies. These include closer packing of p- and n- transistors, absence of
latchup problems, and lower parasitics substrate capacitances. In the SOI process
a thin layer of single-crystal silicon film is epitaxially grown on an insulator such
as sapphire or magnesium aluminium spinal. Alternatively, the silicon may be
grown on SiO2 that has been in turn grown on silicon. This option has proved
more popular in recent years due to the compatibility of the starting material with
conventional silicon CMOS fabrication. Various masking and doping techniques

(figure 1.21) are then used to form p-channel and n-channel devices. Unlike the
more conventional CMOS approaches, the extra steps in well formation do not
exist in the technology.
The steps used in typical SOI CMOS process are as follows. A thin film (7-8 µm)
of very lightly –doped n-type Si is grown over an insulator, Sapphire or SiO2 is
commonly used insulator (figure 1.21 a).
• An anisotropic etch is used away the Si except where a diffusion area (n or p)
will be needed. The etch must be anisotropic since the thickness of the Si is much
greater than the spacing desired between the Si “islands: (figure 1.21 b, c).
• The p-islands are formed next by masking the n-islands with a photoresist. A
p-type dopant, boron, for example is then implanted. It is masked by the
photoresist, but forms p-islands at the unmasked islands. The p-islands will
become the n-channel devices (figure 1.12 d).
• The p-islands are then covered with a photoresist and an n-type dopant-
phosphorus, for example is implanted to form the n-islands. The n-islands will
become the p-channel devices (figure 1.12 e).
• A thin gate oxide (around 100-250 A) is grown over all of the Si structures,
this is normally done by thermal oxidation.
• A polysilicon film is deposited over the oxide. Often the polysilicon is doped
with phosphorus to reduce its resistivity (figure 1.12f).
• The polysilicon is then patterned by photomasking and is etched. This defines
the polysilicon layer in the structure (figure 1.12 g).
• The next step is to form the n-doped source and drain of the n-channel devices
in the p-islands. The n-islands are covered with a photoresist and an n-type
dopant, normally phosphorus is implanted. The dopant and an n-type dopant,
normally phosphorus is implanted. The dopant will be blocked at the n-islands by
the photoresist, and it will be blocked from the gate region of the p-islands by the
polysilicon. After this step the n-channel devices are complete (figure 1.12 h).
• The p-channel devices are formed next by masking the p-islands and
implanting a p-type dopant such as boron. The polysilicon over the gate of the n-
island will block the dopant from the gate, thus forming the p-channel devices
(figure 1.12 i).
• A layer of phosphorus glass or some other insulator such as silicon dioxide is
then deposited over the entire structure.
• The glass is etched as contact –cut locations. The metallization layer is formed
next by evaporating aluminum over the entire surface and etching it to leave only
the desired metal wires. The aluminium will flow through the contact cuts to
make contact with the diffusion or polysilicon regions (figure 1.12 j).
• A final passivation layer of phosphorus glass is deposited and etched over
bonding pad locations (not shown in figure).

Because the diffusion regions extend to the insulating substrate, only “sidewall”
areas associated with source and drain diffusion contribute to the parasitic
junction capacitance. Since sapphire and SiO2 are extremely good insulators,
leakage currents between transistors and substrate and adjacent devices are almost
eliminated.
In order to improve the yield, some processes use “preferential etch” in which he
island edges are tapered. Thus aluminium or poly runners can enter and leave the
islands with a minimum step height. This is contrasted to “fully anisotropic etch”
in which the undercut is brought to zero, as shown in figure 1.13.An” isotropic
etch” is also shown in the same diagram for the comparison.
Figure 1.12 SOI Process Flow

The advantages of SOI technology are as follows,
• Due to absence of wells, transistor structures denser than bulk silicon are
feasible. Also direct n-to-p connections may be made.
• Lower substrate capacitances provide the possibility for faster circuits.
• No field-inversion problems exist( insulating substrate)
• There is no latchup because of the isolation of the n-and p-transistors by the
insulating substrate.
• Because there is no conducting substrate, there are no body-effect problems.
However the absence of a backside substrate contact could lead to odd device
characteristic such as the “kink” effect in which the drain current increases
abruptly at around 2 to 3 volts.
Some of the disadvantages are,
• Due to absence of substrate diodes, the inputs are somewhat more difficult to
protect. Because device gains are lower, I/O structures have to be larger.
• Single crystal sapphire, spinel substrate, and silicon SiO2 are considerably
more expensive than silicon substrate and their processing techniques tend to be
less developed than bulk silicon techniques.
Figure 1.13 Classification of Etching processes

1.3 INTERCONNECT
The most important additions for CMOS logic processes are additional signal-
and power-routing layers. This eases the routing (especially automated
netting) of logic signals between modules and improves the power and clock
distribution to modules. Improved mutability is achieved through additional
layers of metal or by improving the existing polysilicon interconnection
layer.
1.3.1 Metal Interconnect
A second level of metal is almost mandatory for modern CMOS digital. A
third layer is becoming common and is certainly required for leading-edge
high-density, high-speed chips. Normally, aluminum is used for the metal
layers. If some form of planarization is employed the second-level metal
pitch can be the same as the first. As the vertical topology becomes more
varied, the width and spacing of metal conductors has to increase so that
the conductors do not thin and hence break at vertical topology jumps (step
coverage).
Contacting the second-layer metal to the first-layer metal is achieved by a
via, as shown in figure 1.14. If further contact to diffusion or polysilicon is
required, a separation between the via and the contact cut is usually
required. This requires a first-level metal tab to bridge between metal2 and
the lower-level conductor. It is important to realize that in contemporary
processes first level metal must be involved in any contact to underlying
areas. A number of contact geometries are shown in figure 1.15.
Figure 1.14 Two-level metal process cross section
Processes usually require metal borders around the via on both levels of
metal although some process require none. Processes may have no
restrictions on the placement of via with respect to underlying layers

(figure 1.15a) or they may have to be placed inside (figure 1.15b) or
outside (figure1.15c) the underlying polysilicon or diffusion areas.
Aggressive processes allow the stacking of vias on top of contacts, as
shown in figure 1.15 (d).
a
b
c
d
Figure 1.15 Two-level metal /via contact geometrics
Consistent with the relatively large thickness of the intermediate isolation
layer, the vias might be larger than contact cuts and second-layer metal
may need to be thicker and require a larger via overlap although modern
processes strive for uniform pitches on metal I and metal2.
The process steps for a two-metal process are briefly as follows:
• The oxide below the first-metal layer is deposited by atmospheric
chemical vapor deposition (CVD).
• The second oxide layer between the two metal layers is applied in a
similar manner.
• Depending on the process, removal of the oxide is accomplished using
a plasma etcher designed to have a high rate of vertical ion bombardment.
This allows fast and uniform etch rates. The structure of a via etched
using such a method is shown in figure1.14.
1.3.2 Polysilicon/Refractory Metal Interconnect
The polysilicon layer used for the gates of transistors is commonly used
as it interconnect layer. However, the sheet resistance of doped
polysilicon is between 20Ω and 40Ω/square. If used as a long distance
conductor, a polysilicon wire can represent a significant delay.

One method to improve this that requires no extra mask levels is to
reduce the polysilicon resistance by combining it with a refractory metal.
Three such approaches are illustrated in figure 1.16.In figure 1.16(a)
a silicide (e.g., silicon and tantalum) is used as the gate material. Sheet
resistances of the order of 1 to 5Ω/square may be obtained. This is called
the, silicide gate approach.
Figure 1.16 Refractory metal interconnect
Silicides are mechanically strong and may be dry ached in plasma
reactors. Tantalum silicide is stable throughout standard processing and
has the advantage that it may be retrofitted into existing process lines.
Figure 1.16(b) uses a sandwich of silicide upon polysilicon, which is
commonly called the polycide approach. Finally, the silicide/polysilicon
approach may he extended to include the formation of source and drain
regions using the silicide. This is called the salicide process (Self
Aligned SILICIDE) (figure 1.16c). The effect of all of these processes
is to reduce the "second layer"
interconnect resistance, allowing the gate
material to be used as a moderate long-distance interconnect. This is
achieved by minimum perturbation of an existing process. An increasing
trend in process is to use the salicide approach to reduce the resistance of
both gate and source/drain conductors.
1.3.3 Local Interconnect
The silicide itself may be used as a "local interconnect" layer for
connection within cells. TiN is used as an example. Local
interconnect allows a direct connection between polysilicon and
diffusion, thus alleviating the need for area intensive contacts and metal.
Figure 1.17 shows a portion (p-devices only) of a six transistor SRAM
cell that uses local interconnect. The local interconnect has been used to
make the polysilicon-to-diffusion connections within the cell, thereby
alleviating the need to use metal (and contacts). Metal2 (not shown) bit
lines run over the cell vertically. Use of local interconnect in this RAM
reduced the cell area by 25%.

Figure 1.17 Local interconnect as used in a RAM cell
In general, local interconnect if available can be used to complete intracell
routing, leaving the remaining metal layers for global wiring.
1.4 CIRCUIT ELEMENTS
1.4.1 Resistors
Polysilicon, if left undoped, is highly resistive. This property is used to build
resistors that are used in static memory cells. The process step is achieved by
preventing the resistor areas from being implanted during normal
processing. Resistors in the tera-Ω (1012
Ω) region are used. A value of
3TΩ results in a standby current of 2µA for a 1 Mbit memory.
For mixed signal CMOS (analog and digital), a resistive metal such as
nichrome may be added to produce high-value, high-quality resistors. The
resistor accuracy might be further improved by laser trimming the result
resistors on each chip to some predetermined test specification. In this
process a high-powered laser vaporizes areas of the metal resistor until it
meets a measurement constraint. Sheet resistance values in the KΩ/square
are normal. The resistors have excellent temperature stability and long-term
reliability.
1.4.2 Capacitors
Good quality capacitors are required for switched-capacitor analog circuits
while small high-value/area capacitors are required for dynamic memory
cells. Both types of capacitors are usually added by using at least one extra
layer of polysilicon, although the process techniques are very different.

Polysilicon capacitors for analog applications are the most straightforward.
A second thin-oxide layer is required in order to have an oxide sandwich
between the two polysilicon layers yielding a high-capacitance/unit area.
Figure 1.18 shows a typical polysilicon capacitor. The presence of this,
second oxide can also be used to fabricate transistors. These may differ,
characteristics from the primary gate oxide devices. For memory capacitors
recent processes have used three dimensions to increase the
capacitance/area.
Figure 1.18 Polysilicon Capacitor
One popular structure is the trench capacitor,
which has evolved considerably over the years to push memory densities to
64Mbits and beyond. A typical trench structure is shown in figure 1.19(a).
The sides of the trench are doped n+ and coated with a thin 1Onm oxide.
Sometimes oxynitride is used because its high dielectric constant increases
capacitance.
a
b
Figure 1.19 Dynamic memory capacitors
The trench is filled with a polysilicon plug, which forms the bottom plate of
the cell storage capacitor. This is held at VDD/2 via a metal connection at the

edge of the array. The sidewall n+ forms the other side of capacitor and one
side of the pass transistor that is used to enable data onto the bit lines. The
bottom of the trench has a p+ plug that forms a channel stop region to isolate
adjacent capacitors. The trench is 4µm deep and has a capacitance of 90fF.
Rather than building a trench, figure 1.19(b) shows a fintype- capacitor used
in a 64-Mb DRAM. The storage capacitance is 20 to 30 fF. The fins have the
additional advantage of reducing the bit capacitance by shielding the bit
lines. The fabrication of 3D-process structures such as these is a constant
reminder of the skill, perseverance, and ingenuity of the process engineer.
1.4.3 Electrically Alterable ROMs
Electrically alterable/erasable ROM (EAROM/EEPROM) is added to
CMOS processes to yield permanent but reprogrammable storage to a
process. This is usually added by adding a polysilicon layer. Figure 1.20
shows a typical memory structure, which consists of a stacked-gate
structure. The normal gate is left floating, while a control gate is placed
above the floating gate. A very thin oxide called the tunnel oxide
separates the floating gate from the source, drain, and substrate.
Figure 1.20 EEPROM technology
This is usually 10 nm thick. Another thin oxide separates the control gate
from the floating gate. By controlling the control-gate, source, and drain
voltages, the thin tunnel oxide between the floating gate and the drain of
the device is used to allow electrons to "tunnel" to or from the floating
gate to turn the cell or on, respectively, using Fowler-Nordheim tunneling.
Alternatively, by setting the appropriate voltages on the terminals, "hot
electrons" can be induced to charge the floating gate, thereby
programming the transistor. In non-electrically alterable versions of the
technology, the process can be reversed by illuminating the gate with UV
light. In these the chips are usually housed in glass-lidded packages.

1.4.4 Bipolar Transistors
The addition of the bipolar transistor to the device repertoire forms the
basis for BiCMOS processes. Adding an npn-transistor can markedly aid in
reducing the delay times of highly loaded signals, such as memory word
lines microprocessor busses. Additionally, for analog applications bipolar
transistors may be used to provide better performance analog functions than
MOS alone. To get merged bipolar/CMOS functionality,
Figure 1.21 Typical mixed signal BiCMOS process cross section
Figure 1.22 BiCMOS process steps for the cross section shown in
figure 1.21

MOS transistors can add to a bipolar process or vice versa. In past days,
MOS processes always had to have excellent gate oxides while bipolar
processes had to have precisely controlled diffusions.
A BiCMOS process has to have both. A mixed signal BiCMOS process
cross section is shown in figure 1.21. This process features both npn- and
pnp-transistors in addition to pMOS and nMOS transistors. The major
processing steps are summarized in figure 1.22, showing the particular
device to which they correspond. The base layers of the process are similar
to the process shown in figure 1.12. The starting material is a lightly-
doped p-type substrate into which antimony or arsenic are diffused to
form an n+ buried layer. Boron is diffused to form a buried p+
layer. An n-
type epitaxial layer 4.0 µm thick is then grown. N-wells and p-wells are then
diffused so that they join in the middle of the epitaxial layer. This
epitaxial layer isolates the pnp-transistor in the horizontal direction, while
the buried n+ layer isolates it vertically. The npn-transistor is junction-
isolated. The base for the pnp is then ion-implanted using phosphorous. A
diffusion step follows this to get the right doping profile. The npn-
collector is formed by depositing phosphorus before LOCOS. Field
oxidation is carried out and the gate oxide is grown. Boron is then used to
form the p-type base of the npn transistor.
Following the threshold adjustment of the pMOS transistors, the
polysilicon gates are defined. The emitters of the npn-transistors employ
polysilicon rather than a diffusion. These are formed by opening windows
and depositing polysilicon. The n+ and p+ source/drain implants are then
completed. This step also dopes the npn-emitter and the extrinsic bases of
the npn- and pnp-transistors (extrinsic because this is the part of the base
that is not directly between collector and emitter).
Following the deposition of PSG, the normal two-layer metallization steps
are completed. Representative of a high-density digital BiCMOS process
is that represented by the cross section shown in figure 1.23. The buried-
layer-epitaxial layer-well structure is very similar to the previous
structure. However because this is a 0.8µm process, LDD structures must
be constructed for the p-transistors and the n-transistors. The npn is formed
by a double-diffused sequence in which both base and emitter are formed
by impurities that diffuse out of a covering layer of polysilicon. This
process, intended for logic applications, has only an npn-transistor. The
collector of the npn is connected to the n-well, which is in turn connected
to the VDD supply. Thus all npn-collectors are commoned. A typical npn-
transistor with a 0.8µm-square emitter has a current gain of 90 and an ft. of
15 GHz.

Figure 1.23 Digital BiCMOS process cross section
1.4.5 LatchUp
If every silver lining has a cloud, then the cloud that has plagued CMOS is
a parasitic circuit effect called "latchup." The result of this effect is the
shorting of the VDD and Vss lines, usually resulting in chip self-
destruction or at least system failure with the requirement to power down.
This effect was a critical factor in the lack of acceptance of early CMOS
processes, but in cur-rent processes it is controlled by process innovations
and well-understood circuit techniques.
1.4.5.1 The Physical Origin of Latchup
The source of the latchup effect may be explained by examining the
process cross section of a CMOS inverter, shown in figure 1.24(a), on
which is overlaid an equivalent circuit. The schematic depicts, in addition
to the expected nMOS and pMOS transistors, a circuit composed of an
npn-transistor, a pnp-transistor, and two resistors connected between the
power and ground rails (figure 1.24b). Under the right conditions, this
parasitic circuit has the VI characteristic shown in figure 1.24(c), which
indicates that above some critical voltage (known as the trigger point) the
circuit "snaps" and draws a large current while maintaining a low voltage
across the terminals (known as the holding voltage). This is, in effect, a
short circuit. As mentioned, the bipolar devices and resistors shown in
figure 1.24 (b) are parasitic, that is an unwanted byproduct of producing
pMOS and nMOS transistors. From the figure 1.24(a) reveals how these
devices are constructed. The figure shows a cross-sectional view of a
typical (n-well) CMOS process. The (vertical) pnp-transistor has its
emitter formed by the p+ source/drain implant used in the pMOS
transistors. Note that either the drain or source may act as the emitter
although the source is the only terminal that can maintain the latchup
condition. The base is formed by the n-well, while the collector is the p-

substrate. The emitter of the (lateral) npn-transistor is the n+ source/drain
implant, while the base is the p-substrate and the collector is the n-well. In
addition, substrate resistance Rsubstrate and well resistance Rwell are due to
the resistivity of the semiconductors involved.
Figure 1.24 The origin model, and VI characteristics of CMOS Latchup
Consider the circuit shown in figure 1.24(b). If a current is drawn from the
npn-emitter, the emitter voltage becomes negative with respect to the base until
the base emitter voltage is approximately 0.7 volts. At this point the npn-
transistor turns on and a current flows in the well resistor due to common emitter
current amplification. This raises the base emitter voltage of the pnp-
transistor, which turns on when the pnp Vbe = -0.7 volts. This in turn
raises the npn base voltage causing a positive feedback condition, which
has the characteristic shown in figure 1.24(c). At a certain npn-base-
emitter voltage, called the trigger point, the emitter voltage suddenly
"snaps back" and enters a stable state called the ON state. This state will
persist as long as the voltage across the two transistors is greater than the
holding voltage shown in the figure. As the emitter of the npn is the
source/drains of the n-transistor, these terminals are now at roughly 4
volts. Thus there is about 1 volt across the CMOS inverter, which will

most likely cause it to cease operating correctly. The current drawn is
usually destructive to metal lines supplying the latched up circuitry.
1.4.5.2 Latchup Triggering
For latchup to occur the parasitic npn-pnp circuit has to be triggered and
the holding state has to be maintained. Latchup can be triggered by
transient cur-rents or voltages that may occur internally to a chip during
power-up or externally due to voltages or currents beyond normal
operating ranges. Radiation pulses can also cause latchup. Two distinct
methods of triggering are possible, lateral triggering and vertical
triggering.
Lateral triggering occurs when a current flows in the emitter of the lateral
npn-transistor. The static trigger point is set by
Intrigger ~ Vpnp-on (1.1)
αnpn Rwell
where
Vpnp_on~ 0.7 volts the turn-on voltage of the vertical pnp-transistor
anpn = common base gain of the lateral npn-transistor
Rwell = well resistance.
Vertical triggering occurs when a sufficient current is injected into the
emitter of the vertical-pnp transistor. Similar to the lateral case, this
current is multiplied by the common-base-current gain, which causes a
voltage drop across the emitter base junction of the npn transistor due to
the resistance, Rsubstrate. When the holding or sustaining point is entered, it
represents a stable operating point provided the current required to stay in
the state can he maintained.
Current has to be injected into either the npn- or pnp-emitter to initiate
latchup. During normal circuit in internal circuitry this may occur due to
supply voltage transients, but this is unlikely. However, these conditions
may occur at the I/O circuits employed on a CMOS chip, where the
internal circuit voltages meet the external world and large currents can
flow. Therefore extra precautions need to be taken with peripheral CMOS
circuits.

a
b
Figure 1.25 Externally included latchup
Figure 1.25(a) illustrates an example where the source of an nMOS output
transistor experiences undershoot with respect to Vss due to some external
circuitry. When the output dips below Vss by more than 0.7V, the drain of
the nMOS output driver is forward biased, which initiates latchup. The
complementary case is shown in figure 1.25(b) where the pMOS output
transistor experiences an overshoot more than 0.7V beyond VDD. Whether
or not in these cases latchup occurs depends on the pulse widths and
speed of the parasitic transistors.
1.4.6 Latchup Prevention
For latchup to occur an analysis of the circuit in figure 1.25(b) finds the
following inequality has to be true
βnpnβpnp> 1+ (βnpn+1
) I
Rsubstrate+I
Rwellβpnp) (1.2)
I
DD - I
Rsubstrate
Where
I
Rsubstrate == Vbe npn
R
substrate
I
Rwell = Vbe pnp
Rwell
IDD =total supply current

This equation yields the keys to reducing latchup to the point where it
should never occur under normal circuit conditions. Thus, reducing the
resistor values and reducing the gain of the parasitic transistors are the
basis for eliminating latchup.
Latchup may be prevented in two basic ways:
• Latchup resistant CMOS processes.
• Layout techniques.
A popular process option that reduces the gain of the parasitic transistors
is the use of silicon starting-material with a thin epitaxial layer on top of a
highly doped substrate. This decreases the value of the substrate resistor
and also provides a sink for collector current of the vertical pnp-transistor.
As the epi layer is thinned, the latchup performance improves until a point
where the up-diffusion of the substrate and the down-diffusion of any
diffusions in subsequent high-temperature procession steps thwart
required device doping profiles. The so-called retrograde well structure is
also used. This well has a highly doped area at the bottom of the well,
whereas the top of the well is more lightly doped. This preserves good
characteristics for the pMOS (or nMOS in p-well) transistors but reduces
the well resistance deep in the well. A technique linked to these two
approaches is to increase the holding voltage above the VDD supply. This
guarantees that latchup will not occur.
It is hard to reduce the betas of the bipolar transistors to meet the condi-
tion set above. Nominally, for a 1µ n-well process, the vertical pnp has a
beta of 10-100, depending on the technology. The lateral npn-current-
gain which is a function of n+ drain to n-well spacing , is between 2
and 5.
1.5 LAYOUT DESIGN RULES
Layout rules, also referred to as design rules, can be considered as a pre-
scription for preparing the photomasks used in the fabrication of
integrated circuits. The rules provide a necessary communication link
between circuit designer and process engineer during the manufacturing
phase. The main objective associated with layout rules is to obtain a
circuit with optimum yield (functional circuits versus nonfunctional
circuits) in as small an area as possible without compromising reliability
of the circuit.
In general, design rules represent the best possible compromise between
performance and yield. The more conservative the rules are, the more
likely it is that the circuit will function. However, the more aggressive the

rules are, the greater the probability of improvements in circuit
performance. This improvement may be at the expense of yield.
Design rules specify to the designer certain geometric constraints on the
layout artwork so that the patterns on the processed wafer will preserve
the topology and geometry of the designs. It is important to note that
design rules do not represent some hard boundary between correct and
incorrect fabrication. Rather, they represent a tolerance that ensures very
high probability of correct fabrication and subsequent operation. For
example, one may find that a layout that violates design rules may still
function correctly, and vice versa. Nevertheless, any significant or
frequent departure (design-rule waiver) from design rules will seriously
prejudice the success of a design.
Two sets of design-rule constraints in a process relate to line widths and
interlayer registration. If the line widths are made too small, it is possible
for the line to become discontinuous, thus leading to an open circuit wire.
On the other hand, if the wires are placed too close to one another, it is
possible for them to merge together; that is, shorts can occur between two
independent circuit nets. Furthermore, the spacing between two
independent layers may be affected by the vertical topology of a process.
The design rules primarily address two issues:
(1) The geometrical reproduction of features that can be reproduced by
the mask- making and litho-graphical process and
(2) The interactions between different layers.
There are several approaches that can be taken in describing the design
rules. These include 'micron' rules stated at some micron resolution, and
lambda (λ) based rules. Micron designs rules are usually given as a list
of minimum feature sizes and spacings for all masks required in a given
process.
1.5.1 Layer Representations
The advances in the CMOS processes are generally complex and
somewhat inhibit the visualization of all the mask levels that are used in
the actual fabrication process. Nevertheless the design process can be
abstracted to a manageable number of conceptual layout levels that
represent the physical features observed in the final silicon wafer. At a
sufficiently high conceptual level all CMOS processes use the following
features:
• Two different substrates.
• Doped regions of both p- and n-transistor-forming material.
• Transistor gate electrodes.

• Interconnection paths.
• Interlayer contacts.
The layers for typical CMOS processes are represented in various figures
in terms of:
• A color scheme proposed by JPL based on the Mead-Conway colors.
• Other color schemes designed to differentiate CMOS structures
(e.g., the colors as used on the from cover of this hook)
• Varying stipple patterns.
• Varying line styles.
Some of these representations are shown in below table.
1.5.2 CMOS n-well Rules
In this section a version of n-well rules based on the MOSIS CMOS
Scalable Rules and compares those with the rules for a hypothetical
commercial 1µ CMOS process shown in below table. The MOSIC rules
are expressed in terms of λ. These rules allow some degree of scaling
between processes as, in principal, we only need to reduce the value of λ and
the designs will be valid in the next process down in size. Unfortunately, history
has shown that processes rarely shrink uniformly. Thus industry usually uses the
actual micron-design rules and codes designs in terms of these dimensions, or
uses symbolic layout systems to target the design rules exactly. At this time, the
amount of polygon pushing is usually constrained to a number of frequently used

standard cells or memories, where the effort expended is amortized over many
designs. Alternatively, the designs are done symbolically, thus relieving the
designer of having to deal directly with the actual design rules.
The rules are defined in terms of:
• Feature sizes.
• Separations and overlaps.

1.5.3 Scribe Line
The scribe line is specifically designed structure that surrounds the
completed chip and is the point at which the chip is cut with a diamond
saw. The construction of the scribe line varies from manufacturer to
manufactures
1.5.4 SOI Rules
SOI rules closely follow bulk CMOS rules except the n+ and p+ regions
can abut. This allows some interesting and latch circuits. A spacing rule
between the poly and island edges. This can be caused by thin or faculty
oxide covering over the islands.

1.5.5 Layer Assignments
The below table lists the MOSIS Scalable CMOS design-rule layer
assignments for the Caltech Intermediate Form (CIF) and Calma stream
format.
1.6. PHYSICAL DEISGN
1.6.1 Basic Concept
Figure 1.26 shows part of the design flow, the physical design steps, for
an ASIC (omitting simulation, test, and other logical design steps that
have already been covered). Some of the steps in Figure 1.26 might be
performed in a different order from that shown. For example, depending
on the size of the system, perform system partitioning before any design
entry or synthesis. There may be some iteration between the different
steps too. First to apply system partitioning to divide a microelectronics
system into separate ASICs.
In floorplanning sizes estimate and set the initial relative locations of the
various blocks in our ASIC (sometimes we also call this chip planning).

At the same time to allocate space for clock and power w i r i n g a n d
decide on the location of the I/O and power pads. Placement defines the
location of the logic cells within the flexible blocks and sets aside space for
the interconnect to each logic cell. Placement for a gate-array or standard-
cell design assigns each logic cell to a position in a row.
Figure 1.26 Part of ASIC Design Flow
For an FPGA, placement chooses which o f the fixed logic resources on the
chip are used for which logic cells. Floorplanning and placement are
closely related and are sometimes combined in a single CAD tool.
Routing makes the connections between logic cells. Routing is a hard
problem by itself is normally split into two distinct steps, called global
and local routing. Global routing determines where the interconnections
between the placed logic cells and blocks will be situated. Only the routes
to he used by the interconnections within the wiring areas.
Global routing is sometimes called loose routing for this reason. Local
routing joins the logic cells with interconnections. Information on which
interconnections areas to use comes from the global router. Only at this
stage of layout d, finally decide on the width, mask layer, and exact
location of the interconnections local routing is also known as detailed
routing.

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four years, to commence 4th day of March next, information of his
said election:"
It passed in the negative.
Ordered, That the resolution this day agreed to by the House of
Representatives, relative to the notification of the election of the Vice
President elect, be referred to Messrs. Mason, Hillhouse, and Sedgwick,
to consider and report thereon to the Senate.
Mr. Mason reported, from the committee last appointed; and, the
report being read, was amended and adopted as follows:
Resolved, That the President Of the United States be requested to
cause to be transmitted to Thomas Jefferson, Esq., of Virginia, Vice
President elect of the United States, notification of his election to that
office; and that the President of the Senate do make out and sign a
certificate in the words following:
Be it known, that the Senate and House of Representatives of the
United States of America, being convened in the city of Philadelphia,
on the second Wednesday in February, in the year of our Lord one
thousand seven hundred and ninety-seven, the underwritten Vice
President of the United States and President of the Senate did, in
the presence of the said Senate and House of Representatives, open
all the certificates and count all the votes of the Electors for a
President and for a Vice President; by which it appears that Thomas
Jefferson, Esquire, was duly elected, agreeably to the constitution,
Vice President of the United States of America.
"In witness whereof, I have hereunto set my hand and seal, this
10th day of February, 1797."
Ordered, That the Secretary lay this resolution before the President
of the United States.
Monday, February 13.

On request, the Vice President was excused from further attendance
in the Senate after Wednesday next.
Wednesday, February 15.
Withdrawal of the Vice-President, (now President elect of the United
States,) and his Valedictory to the Senate.
After the consideration of the Executive business, a motion was
made that the Senate now adjourn; when the Vice-President
addressed them as follows:
Gentlemen of the Senate:
If, in the general apprehension of an intention to retire in that most
eminent citizen, to whom all eyes had been directed, and all hearts
attracted, as the centre of our Union, for so long a period, the public
opinion had exhibited any clear indication of another, in whom our
fellow-citizens could have generally united, as soon as I read that
excellent Address, which announced the necessity of deliberation in
the choice of a President, I should have imitated the example of a
character with which I have co-operated, though in less conspicuous
and important stations, and maintained an uninterrupted friendship
for two and twenty years. But, as a number of characters appeared
to stand in the general estimation so nearly on a level, as to render
it difficult to conjecture on which the majority would fall; considering
the relation in which I stood to the people of America, I thought it
most respectful to them, and most conducive to the tranquillity of
the public mind, to resign myself, with others, a silent spectator of
the general deliberation, and a passive subject of public discussions.
Deeply penetrated with gratitude to my countrymen in general, for
their long continued kindness to me, and for that steady and
affecting confidence, with which those who have most intimately
known me, from early life, have, on so many great occasions,
intrusted to me the care of their dearest interests; since a majority
of their Electors, though a very small one, have declared in my favor,

and since, in a Republican Government, the majority, though ever so
small, must of necessity decide, I have determined, at every hazard
of a high but just responsibility, though with much anxiety and
diffidence, once more to engage in their service. Their confidence,
which has been the chief consolation of my life, is too precious and
sacred a deposit ever to be considered lightly; as it has been
founded only on the qualities of the heart, it never has been, it
never can be, deceived, betrayed, or forfeited by me.
It is with reluctance, and with all those emotions of gratitude and
affection, which a long experience of your goodness ought to
inspire, that I now retire from my seat in this House, and take my
leave of the members of the Senate.
I ought not to declare, for the last time, your adjournment, before I
have presented to every Senator present, and to every citizen who
has ever been a Senator of the United States, my thanks, for the
candor and favor invariably received from them all. It is a
recollection of which nothing can ever deprive me, and it will be a
source of comfort to me, through the remainder of my life, that as,
on the one hand, in a government constituted like ours, I have for
eight years held the second situation under the Constitution of the
United States, in perfect and uninterrupted harmony with the first,
without envy in one, or jealousy in the other; so, on the other hand,
I have never had the smallest misunderstanding with any member of
the Senate. In all the abstruse questions, difficult conjectures,
dangerous emergencies, and animated debates, upon the great
interests of our country, which have so often and so deeply
impressed all our minds, and interested the strongest feelings of the
heart, I have experienced a uniform politeness and respect from
every quarter of the House. When questions of no less importance
than difficulty have produced a difference of sentiment, (and
difference of opinion will always be found in free assemblies of men,
and probably the greatest diversities upon the greatest questions,)
when the Senators have been equally divided, and my opinion has
been demanded according to the constitution, I have constantly
found, in that moiety of the Senators from whose judgment I have

been obliged to dissent, a disposition to allow me the same freedom
of deliberation, and independence of judgment, which they asserted
for themselves.
Within these walls, for a course of years, I have been an admiring
witness of a succession of information, eloquence, patriotism, and
independence, which, as they would have done honor to any Senate
in any age, afford a consolatory hope, (if the Legislatures of the
States are equally careful in their future selections, which there is no
reason to distrust,) that no council more permanent than this, as a
branch of the Legislature, will be necessary, to defend the rights,
liberties, and properties of the people, and to protect the
Constitution of the United States, as well as the constitutions and
rights of the individual States, against errors of judgment,
irregularities of the passions, or other encroachments of human
infirmity, or more reprehensible enterprise, in the Executive on one
hand, or the more immediate representatives of the people on the
other.
These considerations will all conspire to animate me in my future
course, with a confident reliance, that as far as my conduct shall be
uniformly measured by the Constitution of the United States, and
faithfully directed to the public good, I shall be supported by the
Senate, as well as by the House of Representatives, and the people
at large; and on no other conditions ought any support at all to be
expected or desired.
With cordial wishes for your honor, health, and happiness, and
fervent prayers for a continuation of the virtues, liberties, prosperity,
and peace, of our beloved country, I avail myself of your leave of
absence for the remainder of the session.
Thursday, February 16.
The Vice-President being absent, the Senate proceeded to the choice
of a President pro tempore, as the constitution provides, and the
honorable William Bingham was duly elected.

Ordered, That the Secretary wait on the President of the United
States, and notify him of the election of the Honorable William
Bingham, to be President of the Senate pro tempore.
Ordered, That the Secretary notify the House of Representatives of
this election.
On motion,
Ordered, That Messrs. Sedgwick, Burr, and Tracy, be a committee to
prepare and report the draft of an answer to the Address delivered
yesterday to the Senate, by the Vice President of the United States.
Tuesday, February 21.
The bill to accommodate the President was read the third time; and,
being further amended,
On motion that it be Resolved, That this bill pass, it was decided in
the affirmative—yeas 28, nays 3, as follows:
Yeas.—Messrs. Bingham, Bloodworth, Blount, Bradford, Brown,
Foster, Goodhue, Gunn, Henry, Hillhouse, Howard, Langdon, Latimer,
Laurance, Livermore, Marshall, Martin, Pain, Read, Ross, Rutherford,
Sedgwick, Stockton, Tattnall, Tazewell, Tichenor, Tracy, and Vining.
Nays.—Messrs. Cocke, Hunter, and Mason.
So it was Resolved, That this bill pass; that it be engrossed; and that
the title thereof be, "An act to accommodate the President."
Mr. Sedgwick reported from the committee appointed for the purpose,
the draft of an answer to the Address of the Vice President of the
United States, on his retiring from the Senate; which was read.
On motion, that it be printed for the use of the Senate, it was
disagreed to.
Ordered, That the report lie for consideration.

Wednesday, February 22.
The Senate took into consideration the report of the committee, in
answer to the Address of the Vice President of the United States, on
his retiring from the Senate.
On motion to recommit the report, it passed in the negative: and the
report being amended, was adopted, as follows:
Sir: The Senate of the United States would be unjust to their own
feelings, and deficient in the performance of a duty their relation to
the Government of their country imposes, should they fail to express
their regard for your person, and their respect for your character, in
answer to the Address you presented to them, on your leaving a
station which you have so long and so honorably filled as their
President.
The motives you have been pleased to disclose which induced you
not to withdraw from the public service, at a time when your
experience, talents, and virtues, were peculiarly desirable, are as
honorable for yourself, as, from our confidence in you, sir, we trust
the result will be beneficial to our beloved country.
When you retired from your dignified seat in this House, and took
your leave of the members of the Senate, we felt all those emotions
of gratitude and affection, which our knowledge and experience of
your abilities and undeviating impartiality ought to inspire; and we
should, with painful reluctance, endure the separation, but for the
consoling reflection, that the same qualities which have rendered
you useful, as the President of this branch of the Legislature, will
enable you to be still more so, in the exalted station to which you
have been called.
From you, sir, in whom your country have for a long period placed a
steady confidence, which has never been betrayed or forfeited, and
to whom they have on so many occasions intrusted the care of their
dearest interests, which have never been abused; from you, who,
holding the second situation under the Constitution of the United

States, have lived in uninterrupted harmony with him who has held
the first; from you we receive, with much satisfaction, the
declaration which you are pleased to make of the opinion you
entertain of the character of the present Senators, and of that of
those citizens who have been heretofore Senators. This declaration,
were other motives wanting, would afford them an incentive to a
virtuous perseverance in the line of conduct which has been honored
with your approbation.
In your future course, we entertain no doubt that your official
conduct will be measured by the constitution, and directed to the
public good; you have, therefore, a right to entertain a confident
reliance, that you will be supported, as well by the people at large as
by their constituted authorities.
We cordially reciprocate the wishes which you express for our honor,
health, and happiness; we join with yours our fervent prayers for the
continuation of the virtues and liberties of our fellow-citizens, for the
public prosperity and peace; and for you we implore the best reward
of virtuous deeds—the grateful approbation of your constituents,
and the smiles of Heaven.
WILLIAM BINGHAM,
President of the Senate pro tempore.
Ordered, That the committee who drafted the Address wait on the
Vice President, with the Answer of the Senate.
Thursday, February 23.
Mr. Sedgwick reported, from the committee, that, agreeably to order,
they had waited on the Vice President of the United States, with the
answer to his Address, on retiring from the Senate—to which the
Vice President was pleased to make the following Reply:
An Address so respectful and affectionate as this, from gentlemen of
such experience and established character in public affairs, high
stations in the Government of their country, and great consideration,

in their several States, as Senators of the United States, will do me
great honor, and afford me a firm support, wherever it shall be
known, both at home and abroad. Their generous approbation of my
conduct, in general, and liberal testimony to the undeviating
impartiality of it, in my peculiar relation to their body, a character
which, in every scene and employment of life, I should wish above
all others to cultivate and merit, has a tendency to soften asperities,
and conciliate animosities, wherever such may unhappily exist; an
effect at all times to be desired, and in the present situation of our
country, ardently to be promoted by all good citizens.
I pray the Senate to accept my sincere thanks.
JOHN ADAMS.
Wednesday, March 1.
Executive Veto on the Army Bill.
The President of the United States having stated his objections to the
bill, entitled "An act to alter and amend an act, entitled 'an act to
ascertain and fix the Military Establishment of the United States,'"
the House of Representatives proceeded to consider the objections
to the said bill, and have resolved that it do not pass.

SPECIAL SESSION
Saturday, March 4.
Installation of Thomas Jefferson as Vice President of the
United States and President of the Senate, and inauguration
of John Adams as President of the United States.
To the Vice President and Senators of the United States respectively:
Sir: It appearing to be proper that the Senate of the United States
should be convened on Saturday, the fourth of March instant, you
are desired to attend in the Chamber of the Senate, on that day at
ten o'clock in the forenoon, to receive any communications which
the President of the United States may then lay before you touching
their interests.
G. WASHINGTON.
March 1, 1797.
In conformity with the summons from the President of the United
States, above recited, the Senate accordingly assembled in their
Chamber.
PRESENT:
Thomas Jefferson, Vice President of the United States and President of
the Senate.
John Langdon and Samuel Livermore, from New Hampshire.
Theodore Sedgwick and Benjamin Goodhue, from Massachusetts.
Theodore Foster, from Rhode Island.
James Hillhouse and Uriah Tracy, from Connecticut.

Elijah Payne and Isaac Tichenor, from Vermont.
John Laurance, from New York.
Richard Stockton, from New Jersey.
James Ross and William Bingham, from Pennsylvania.
John Vining and Henry Latimer, from Delaware.
John Henry and John E. Howard, from Maryland.
Henry Tazewell and Stevens T. Mason, from Virginia.
John Brown and Humphrey Marshall, from Kentucky.
Alexander Martin and Timothy Bloodworth, from North Carolina.
William Blount, from Tennessee.
Jacob Read, from South Carolina.
James Gunn and Josiah Tattnall, from Georgia.
Mr. Bingham administered the oath of office to the Vice President, who
took the chair, and the credentials of the following members were
read.
Of Mr. Foster, Mr. Goodhue, Mr. Hillhouse, Mr. Howard, Mr. Latimer, Mr.
Mason, Mr. Ross, and Mr. Tichenor.
And the oath of office being severally administered to them by the
Vice President, they took their seats in the Senate.
The Vice President then addressed the Senate as follows:
Gentlemen of the Senate:
Entering on the duties of the office to which I am called, I feel it
incumbent on me to apologize to this honorable House for the
insufficient manner in which I fear they may be discharged. At an
earlier period of my life, and through some considerable portion of it,
I have been a member of Legislative bodies, and not altogether
inattentive to the forms of their proceedings; but much time has
elapsed since that; other duties have occupied my mind, and, in a

great degree, it has lost its familiarity with this subject. I fear that
the House will have but too frequent occasion to perceive the truth
of this acknowledgment. If a diligent attention, however, will enable
me to fulfil the functions now assigned me, I may promise that
diligence and attention shall be sedulously employed. For one
portion of my duty, I shall engage with more confidence, because it
will depend on my will and not my capacity. The rules which are to
govern the proceedings of this House, so far as they shall depend on
me for their application, shall be applied with the most rigorous and
inflexible impartiality, regarding neither persons, their views, nor
principles, and seeing only the abstract proposition subject to my
decision. If, in forming that decision, I concur with some and differ
from others, as must of necessity happen, I shall rely on the
liberality and candor of those from whom I differ, to believe, that I
do it on pure motives.
I might here proceed, and with the greatest truth, to declare my
zealous attachment to the Constitution of the United States, that I
consider the union of these States as the first of blessings and as the
first of duties the preservation of that constitution which secures it;
but I suppose these declarations not pertinent to the occasion of
entering into an office whose primary business is merely to preside
over the forms of this House, and no one more sincerely prays that
no accident may call me to the higher and more important functions
which the constitution eventually devolves on this office. These have
been justly confided to the eminent character which has preceded
me here, whose talents and integrity have been known and revered
by me through a long course of years, have been the foundation of a
cordial and uninterrupted friendship between us, and I devoutly pray
he may be long preserved for the government, the happiness, and
prosperity, of our common country.[1]
On motion, it was agreed to repair to the Chamber of the House of
Representatives to attend the administration of the oath of office to
John Adams, President of the United States; which the Senate
accordingly did; and, being seated, the President of the United States

(attended by the Heads of Departments, the Marshal of the District
and his officers) came into the Chamber of the House of
Representatives and took his seat in the chair usually occupied by
the Speaker. The Vice President and Secretary of the Senate were
seated in advance, inclining to the right of the President, the late
Speaker of the House of Representatives and Clerk on the left, and
the Justices of the Supreme Court were seated round a table in front
of the President of the United States. The late President of the United
States, the great and good Washington,[2] took a seat, as a private
citizen, a little in front of the seats assigned for the Senate, which
were on the south side of the House, the foreign Ministers and
members of the House of Representatives took their usual seats—a
great concourse of both sexes being present. After a short pause,
the President of the United States arose, and communicated the
following Address:
"When it was first perceived, in early times, that no middle course
for America remained, between unlimited submission to a foreign
Legislature, and a total independence of its claims, men of reflection
were less apprehensive of danger, from the formidable power of
fleets and armies they must determine to resist, than from those
contests and dissensions, which would certainly arise concerning the
forms of government to be instituted over the whole and over the
parts of this extensive country. Relying, however, on the purity of
their intentions, the justice of their cause, and the integrity and
intelligence of the people, under an overruling Providence, which
had so signally protected this country from the first, the
Representatives of this nation, then consisting of little more than half
its present number, not only broke to pieces the chains which were
forging, and the rod of iron that was lifted up, but frankly cut
asunder the ties which had bound them, and launched into an ocean
of uncertainty.
"The zeal and ardor of the people, during the Revolutionary war,
supplying the place of government, commanded a degree of order,
sufficient at least for the preservation of society. The Confederation,

which was early felt to be necessary, was prepared from the models
of the Batavian and Helvetic Confederacies, the only examples which
remain, with any detail and precision, in history, and certainly the
only ones which the people at large had ever considered. But,
reflecting on the striking difference, in many particulars, between
this country and those where a courier may go from the seat of
Government to the frontier in a single day, it was then certainly
foreseen by some who assisted in Congress at the formation of it,
that it could not be durable.
"Negligence of its regulations, inattention to its recommendations, if
not disobedience to its authority, not only in individuals but in States,
soon appeared, with their melancholy consequences: universal
languor; jealousies and rivalries of States; decline of navigation and
commerce; discouragement of necessary manufactures; universal
fall in the value of lands and their produce; contempt of public and
private faith; loss of consideration and credit with foreign nations;
and, at length, in discontents, animosities, combinations, partial
conventions, and insurrection, threatening some great national
calamity.
"In this dangerous crisis, the people of America were not abandoned
by their usual good sense, presence of mind, resolution, or integrity.
Measures were pursued to concert a plan, to form a more perfect
union, establish justice, ensure domestic tranquillity, provide for the
common defence, promote the general welfare, and secure the
blessings of liberty. The public disquisitions, discussions, and
deliberations, issued in the present happy constitution of
Government.
"Employed in the service of my country abroad, during the whole
course of these transactions, I first saw the Constitution of the
United States in a foreign country. Irritated by no literary altercation,
animated by no public debate, heated by no party animosity, I read
it with great satisfaction, as a result of good heads, prompted by
good hearts; as an experiment, better adapted to the genius,
character, situation, and relations, of this nation and country, than

any which had ever been proposed or suggested. In its general
principles and great outlines, it was conformable to such a system of
government as I had ever most esteemed, and in some States, my
own native State in particular, had contributed to establish. Claiming
a right of suffrage, in common with my fellow-citizens, in the
adoption or rejection of a constitution which was to rule me and my
posterity, as well as them and theirs, I did not hesitate to express
my approbation of it, on all occasions, in public and in private. It was
not then, nor has been since, any objection to it, in my mind, that
the Executive and Senate were not more permanent. Nor have I
ever entertained a thought of promoting any alteration in it, but
such as the people themselves, in the course of their experience,
should see and feel to be necessary or expedient, and by their
Representatives in Congress and the State Legislatures, according to
the constitution itself, adopt and ordain.
"Returning to the bosom of my country, after a painful separation
from it, for ten years, I had the honor to be elected to a station
under the new order of things, and I have repeatedly laid myself
under the most serious obligations to support the constitution. The
operation of it has equalled the most sanguine expectations of its
friends, and from an habitual attention to it, satisfaction in its
administration and delight in its effects upon the peace, order,
prosperity, and happiness of the nation, I have acquired an habitual
attachment to it, and veneration for it.
"What other form of government, indeed, can so well deserve our
esteem and love?
"There may be little solidity in an ancient idea that congregations of
men into cities and nations are the most pleasing objects in the sight
of superior intelligences: but this is very certain, that, to a
benevolent human mind, there can be no spectacle presented by
any nation more pleasing, more noble, majestic, or august, than an
assembly like that which has so often been seen in this and the
other chamber of Congress, of a Government, in which the Executive
authority, as well as that of all the branches of the Legislature, are

exercised by citizens selected, at regular periods, by their neighbors,
to make and execute laws for the general good. Can any thing
essential, any thing more than mere ornament and decoration, be
added to this by robes and diamonds? Can authority be more
amiable and respectable, when it descends from accidents, or
institutions established in remote antiquity, than when it springs
fresh from the hearts and judgments of an honest and enlightened
people? For, it is the people only that are represented: it is their
power and majesty that are reflected, and only for their good, in
every legitimate Government, under whatever form it may appear.
The existence of such a Government as ours, for any length of time,
is a full proof of a general dissemination of knowledge and virtue
throughout the whole body of the people. And what object or
consideration more pleasing than this can be presented to the
human mind? If national pride is ever justifiable or excusable, it is
when it springs, not from power or riches, grandeur or glory, but
from conviction of national innocence, information, and benevolence.
"In the midst of these pleasing ideas, we should be unfaithful to
ourselves, if we should ever lose sight of the danger to our liberties,
if any thing partial or extraneous should infect the purity of our free,
fair, virtuous, and independent elections. If an election is to be
determined by a majority of a single vote, and that can be procured
by a party, through artifice or corruption, the Government may be
the choice of a party, for its own ends, not of the nation for the
national good. If that solitary suffrage can be obtained by foreign
nations, by flattery or menaces, by fraud or violence by terror,
intrigue, or venality, the Government may not be the choice of the
American people, but of foreign nations. It may be foreign nations
who govern us, and not we the people who govern ourselves. And
candid men will acknowledge, that, in such cases, choice would have
little advantage to boast of, over lot or chance.
"Such is the amiable and interesting system of Government (and
such are some of the abuses to which it may be exposed) which the
people of America have exhibited to the admiration and anxiety of
the wise and virtuous of all nations, for eight years, under the

administration of a citizen, who, by a long course of great actions,
regulated by prudence, justice, temperance, and fortitude,
conducting a people, inspired with the same virtues, and animated
with the same ardent patriotism and love of liberty, to independence
and peace, to increasing wealth and unexampled prosperity, has
merited the gratitude of his fellow-citizens, commanded the highest
praises of foreign nations, and secured immortal glory with posterity.
"In that retirement which is his voluntary choice, may he long live to
enjoy the delicious recollection of his services, the gratitude of
mankind, the happy fruits of them to himself and the world, which
are daily increasing, and that splendid prospect of the future
fortunes of this country, which is opening from year to year. His
name may be still a rampart, and the knowledge that he still lives a
bulwark, against all open or secret enemies of his country's peace.
His example has been recommended to the imitation of his
successors, by both Houses of Congress, and by the voice of the
Legislatures and the people throughout the nation.
"On this subject it might become me better to be silent, or to speak
with diffidence; but as something may be expected, the occasion, I
hope, will be admitted as an apology, if I venture to say, that if a
preference upon principle, of a free Republican Government, formed
upon long and serious reflection, after a diligent and impartial
inquiry after truth; if an attachment to the Constitution of the United
States, and a conscientious determination to support it, until it shall
be altered by the judgments and wishes of the people, expressed in
the mode prescribed in it; if a respectful attention to the
constitutions of the individual States, and a constant caution and
delicacy towards the State Government; if an equal and impartial
regard to the rights, interest, honor, and happiness, of all the States
in the Union, without preference or regard to a Northern or
Southern, an Eastern or Western position, their various political
opinions on unessential points, or their personal attachments; if a
love of virtuous men of all parties and denominations; if a love of
science and letters, and a wish to patronize every rational effort to
encourage schools, colleges, universities, academies, and every

institution for propagating knowledge, virtue, and religion, among all
classes of the people, not only for their benign influence on the
happiness of life in all its stages and classes, and of society in all its
forms, but as the only means of preserving our constitution from its
natural enemies, the spirit of sophistry, the spirit of party, the spirit
of intrigue, the profligacy of corruption, and the pestilence of foreign
influence, which is the angel of destruction to elective governments;
if a love of equal laws, of justice, and humanity, in the interior
administration; if an inclination to improve agriculture, commerce,
and manufactures, for necessity, convenience, and defence; if a
spirit of equity and humanity towards the aboriginal nations of
America, and a disposition to meliorate their condition, by inclining
them to be more friendly to us, and our citizens to be more friendly
to them; if an inflexible determination to maintain peace and
inviolable faith with all nations, and that system of neutrality and
impartiality among the belligerent powers of Europe, which has been
adopted by this Government, and so solemnly sanctioned by both
Houses of Congress, and applauded by the Legislatures of the States
and the public opinion, until it shall be otherwise ordained by
Congress; if a personal esteem for the French nation, formed in a
residence of seven years, chiefly among them, and a sincere desire
to preserve the friendship which has been so much for the honor
and interest of both nations; if, while the conscious honor and
integrity of the people of America, and the internal sentiment of
their own power and energies must be preserved, an earnest
endeavor to investigate every just cause, and remove every
colorable pretence of complaint; if an intention to pursue, by
amicable negotiation, a reparation for the injuries that have been
committed on the commerce of our fellow-citizens by whatever
nation, and, if success cannot be obtained, to lay the facts before
the Legislature, that they may consider what further measures the
honor and interest of the Government and its constituents demand;
if a resolution to do justice, as far as may depend upon me, at all
times and to all nations, and maintain peace, friendship, and
benevolence, with all the world; if an unshaken confidence in the
honor, spirit, and resources of the American people, on which I have

so often hazarded my all, and never been deceived; if elevated ideas
of the high destinies of this country, and of my own duties towards
it, founded on a knowledge of the moral principles and intellectual
improvements of the people, deeply engraven on my mind in early
life, and not obscured, but exalted by experience and age; and with
humble reverence, I feel it to be my duty to add, if a veneration for
the religion of a people who profess and call themselves Christians,
and a fixed resolution to consider a decent respect for Christianity
among the best recommendations for the public service, can enable
me, in any degree, to comply with your wishes, it shall be my
strenuous endeavor, that this sagacious injunction of the two Houses
shall not be without effect.
"With this great example before me, with the sense and spirit, the
faith and honor, the duty and interest, of the same American people,
pledged to support the Constitution of the United States, I entertain
no doubt of its continuance in all its energy, and my mind is
prepared, without hesitation, to lay myself under the most solemn
obligations to support it to the utmost of my power.
"And may that Being who is supreme over all, the Patron of Order,
the Fountain of Justice, and the Protector, in all ages of the world, of
virtuous liberty, continue his blessing upon this nation and its
Government, and give it all possible success and duration, consistent
with the ends of His Providence."
The oath of office was then administered to him by the Chief Justice
of the Supreme Court of the United States, the Associate Justices
attending. After which, the President of the United States retired, and
the Senate repaired to their own Chamber.
On motion,
Ordered, That Messrs. Langdon and Sedgwick be a committee to wait
on the President of the United States, and notify him that the Senate
is assembled, and ready to adjourn unless he may have any
communications to make to them.

Mr. Langdon reported, from the committee, that they had waited on
the President of the United States, who replied, that he had no
communication to make to the Senate, except his good wishes for
their health and prosperity, and a happy meeting with their families
and friends.
The Senate then adjourned without day.

FOURTH CONGRESS.—SECOND
SESSION.
PROCEEDINGS AND DEBATES
IN
THE HOUSE OF REPRESENTATIVES.
Monday, December 5, 1796.
This being the day appointed by the constitution for the annual
meeting of Congress, in the House of Representatives, the following
named members appeared and took their seats, viz:
From New Hampshire.—Abiel Foster, Nicholas Gilman, John S.
Sherburne, and Jeremiah Smith.
From Massachusetts.—Fisher Ames, Theophilus Bradbury, Henry
Dearborn, Dwight Foster, Nathaniel Freeman, Jr., Samuel Lyman, William
Lyman, John Read, George Thatcher, Joseph B. Varnum, and Peleg
Wadsworth.
From Rhode Island.—Francis Malbone.
From Connecticut.—Joshua Coit, Chauncey Goodrich, Roger Griswold,
Nathaniel Smith, and Zephaniah Swift.
From New York.—Theodorus Bailey, William Cooper, Ezekiel Gilbert,
Henry Glenn, Jonathan N. Havens, John E. Van Allen, Philip Van
Cortlandt, and John Williams.
From New Jersey.—Jonathan Dayton, Aaron Kitchell, and Isaac Smith.

From Pennsylvania.—Albert Gallatin, Samuel Maclay, Frederick Augustus
Muhlenberg, John Richards, Samuel Sitgreaves, and John Swanwick.
From Delaware.—John Patton.
From Maryland.—George Dent, William Hindman, and Richard Sprigg, Jr.
From Virginia.—John Clopton, Isaac Coles, George Jackson, James
Madison, Anthony New, and Robert Rutherford.
From Kentucky.—Christopher Greenup.
From North Carolina.—Thomas Blount and Matthew Locke.
From South Carolina.—William Smith.
From Georgia.—Abraham Baldwin.
The following new members appeared, produced their credentials,
were qualified, and took their seats, viz:
From Tennessee.—Andrew Jackson.
From Maryland.—William Craik, in place of Jeremiah Crabb, resigned.
From Connecticut.—James Davenport, in place of James Hillhouse,
appointed a Senator of the United States.
The Speaker laid before the House a letter from the Governor of
Pennsylvania, with the return of the election of George Ege, to serve
as a member of the House in place of Daniel Heister, resigned.
A quorum, consisting of a majority of the whole number, being
present, it was ordered that the Clerk wait on the Senate, to inform
them that this House was ready to proceed to business; but it
appeared that the Senate had not been able to form a quorum by
one member, and had adjourned.
Mr. William Smith presented a petition from Thomas Lloyd, proposing
to take, in short-hand, and publish the Debates of Congress at
$1,000 per session salary. The expense of printing, &c. he estimated
at $540, for which he would furnish the House with five hundred
copies of that work; engaging to use every possible precaution, and
pay prompt attention.

Mr. S. referred to the unfavorable reception of a proposal of this
nature at the last session, and supposed this would not be more
successful; however, he moved that it be referred to a committee.
The motion was agreed to, and Mr. W. Smith, Mr. Gallatin, and Mr.
Swift, were appointed to examine the petition, and report thereon to
the House.
Tuesday, December 6.
Several other members, to wit: from Vermont, Israel Smith; from
New Jersey, Mark Thompson; from Pennsylvania, Richard Thomas; from
Virginia, Carter B. Harrison, John Heath, and Abraham Venable; and
from North Carolina, Jesse Franklin, William Barry Grove, James
Holland, and Nathaniel Macon, appeared, and took their seats in the
House.
The Speaker observed, that, as there were several returns of new
elections of members to serve in this session, it was proper that,
pursuant to a rule of the House, a Committee of Elections be
appointed.
A committee was accordingly appointed, of Mr. Venable, Mr. Swift, Mr.
Dent, Mr. Dearborn, Mr. Blount, Mr. Muhlenberg, and Mr. A. Foster.
Mr. Macon moved that a Committee of Revisal and Unfinished
Business of last session be appointed, pursuant to the Standing
Rules and Orders of the House, observing that, as the session would
be but short, it would be necessary to be early in the appointment of
committees.
Whereon Mr. Gilman, Mr. R. Sprigg, Jr., and Mr. Macon were appointed.
Notice was received that a quorum of the Senate was formed.
On motion, it was, therefore, resolved, that a committee of three
members be appointed to wait on the President of the United States,
in conjunction with a committee from the Senate, to inform him that
a quorum of both Houses was assembled, and ready to receive any

communications that he may please to make. Mr. Ames, Mr. Madison,
and Mr. Sitgreaves, were accordingly appointed.
A message was received from the Senate informing the House that
they had formed a quorum: whereupon the Clerk went to the Senate
with the resolution of this House. The Secretary soon after returned,
informing the House that the Senate had concurred in the resolution,
and formed a committee for that purpose.
Mr. Ames, from the committee appointed for that purpose, reported
that the committee had waited on the President, who was pleased to
signify to them that he would make a communication to both Houses
of Congress to-morrow, at 12 o'clock, in the Representatives'
Chamber.
Wednesday, December 7.
Another member, to wit, Samuel Sewall, from Massachusetts, in place
of Benjamin Goodhue, appointed a Senator of the United States,
appeared, produced his credentials, was qualified, and took his seat.
A message was sent to the Senate, informing them that this House
was ready, agreeably to appointment, to receive communications
from the President; whereon the Senate attended, and took their
seats. At 12 o'clock the President attended, and, after taking his seat,
rose and delivered the following Address:
Gentlemen of the Senate, and of the House of Representatives:
In recurring to the internal situation of our country, since I had last
the pleasure to address you, I find ample reason for a renewed
expression of that gratitude to the Ruler of the Universe, which a
continued series of prosperity, has so often and so justly called forth.
To an active external commerce, the protection of a Naval force is
indispensable: this is manifest with regard to wars in which a State is
itself a party. But besides this, it is in our own experience, that the
most sincere neutrality is not a sufficient guard against the
depredations of nations at war. To secure respect to a neutral flag,

requires a Naval force, organized and ready to vindicate it from
insult or aggression. This may even prevent the necessity of going to
war, by discouraging belligerent powers from committing such
violations of the rights of the neutral party as may, first or last, leave
no other option. From the best information I have been able to
obtain, it would seem as if our trade to the Mediterranean, without a
protecting force, will always be insecure, and our citizens exposed to
the calamities from which numbers of them have but just been
relieved.
These considerations invite the United States to look to the means,
and to set about the gradual creation of a Navy. The increasing
progress of their navigation promises them, at no distant period, the
requisite supply of seamen; and their means in other respects favor
the undertaking. It is an encouragement likewise that their particular
situation will give weight and influence to a moderate Naval force in
their hands. Will it not, then, be advisable to begin, without delay, to
provide and lay up the materials for the building and equipping of
ships of war, and to proceed in the work by degrees, in proportion as
our resources shall render it practicable without inconvenience; so
that a future war of Europe may not find our commerce in the same
unprotected state in which it was found by the present?
Congress have repeatedly, and not without success, directed their
attention to the encouragement of manufactures. The object is of
too much consequence not to ensure a continuance of their efforts
in every way which shall appear eligible. As a general rule,
manufactures on public account are inexpedient. But where the state
of things in a country leaves but little hope that certain branches of
manufacture will for a great length of time obtain, when these are of
a nature essential to the furnishing and equipping of the public force
in time of war; are not establishments for procuring them on public
account, to the extent of the ordinary demand for the public service,
recommended by strong considerations of national policy, as an
exception to the general rule? Ought our country to remain in such
cases dependent on foreign supply, precarious, because liable to be
interrupted? If the necessary articles should in this mode cost more

in time of peace, will not the security and independence thence
arising form an ample compensation? Establishments of this sort,
commensurate only with the calls of the public service in time of
peace, will, in time of war, easily be extended in proportion to the
exigencies of the Government, and may even, perhaps, be made to
yield a surplus for the supply of our citizens at large, so as to
mitigate the privations from the interruption of their trade. If
adopted, the plan ought to exclude all those branches which are
already, or likely soon to be established in the country, in order that
there may be no danger of interference with pursuits of individual
industry.
It will not be doubted that with reference either to individual or
national welfare, agriculture is of primary importance. In proportion
as nations advance in population, and other circumstances of
maturity, this truth becomes more apparent, and renders the
cultivation of the soil more and more an object of public patronage.
Institutions for promoting it grow up, supported by the public purse;
and to what object can it be dedicated with greater propriety?
Among the means which have been employed to this end, none
have been attended with greater success than the establishment of
Boards, composed of proper characters, charged with collecting and
diffusing information, and enabled by premiums, and small
pecuniary aids, to encourage and assist a spirit of discovery and
improvement. This species of establishment contributes doubly to
the increase of improvement, by stimulating to enterprise and
experiment, and by drawing to a common centre the results every
where of individual skill and observation, and spreading them thence
over the whole nation. Experience accordingly has shown that they
are very cheap instruments of immense national benefits.
I have heretofore proposed to the consideration of Congress the
expediency of establishing a National University, and also a Military
Academy. The desirableness of both these institutions has so
constantly increased with every new view I have taken of the
subject, that I cannot omit the opportunity of once for all recalling
your attention to them.

The Assembly to which I address myself is too enlightened not to be
fully sensible how much a flourishing state of the arts and sciences
contributes to national prosperity and reputation. True it is that our
country, much to its honor, contains many seminaries of learning
highly respectable and useful; but the funds upon which they rest
are too narrow to command the ablest professors in the different
departments of liberal knowledge for the institution contemplated,
though they would be excellent auxiliaries.
Amongst the motives to such an institution the assimilation of the
principles, opinions, and manners of our countrymen, by the
common education of a portion of our youth from every quarter, well
deserves attention. The more homogeneous our citizens can be
made in these particulars, the greater will be our prospect of
permanent union; and a primary object of such a national institution
should be the education of our youth in the science of Government.
In a Republic, what species of knowledge can be equally important?
and what duty more pressing on its Legislature, than to patronize a
plan for communicating it to those who are to be the future
guardians of the liberties of the country?
The institution of a Military Academy is also recommended by cogent
reasons. However pacific the general policy of a nation may be, it
ought never to be without an adequate stock of military knowledge
for emergencies. The first would impair the energy of its character,
and both would hazard its safety, or expose it to greater evils when
war could not be avoided: besides, that war might often not depend
upon its own choice. In proportion as the observance of pacific
maxims might exempt a nation from the necessity of practising the
rules of the military art, ought to be its care in preserving and
transmitting by proper establishments the knowledge of that art.
Whatever argument may be drawn from particular examples,
superficially viewed, a thorough examination of the subject will
evince that the art of war is at once comprehensive and
complicated; that it demands much previous study; and that the
possession of it, in its most improved and perfect state, is always of
great moment to the security of a nation. This, therefore, ought to

be a serious care of every Government; and for this purpose an
Academy, where a regular course of instruction is given, is an
obvious expedient, which different nations have successfully
employed.
The compensations to the officers of the United States in various
instances, and in none more than in respect to the most important
stations, appear to call for Legislative revision. The consequences of
a defective provision are of serious import to the Government.
If private wealth is to supply the defect of public retribution, it will
greatly contract the sphere within which the selection of character
for office is to be made, and will proportionally diminish the
probability of a choice of men, able, as well as upright. Besides, that
it would be repugnant to the vital principles of our Government
virtually to exclude from public trusts, talents, and virtue, unless
accompanied by wealth.
While in our external relations some serious inconveniences and
embarrassments have been overcome, and others lessened, it is
with much pain and deep regret I mention that circumstances of a
very unwelcome nature have lately occurred. Our trade has suffered,
and is suffering, extensive injuries in the West Indies, from the
cruisers and agents of the French Republic; and communications
have been received from its Minister here which indicate the danger
of a further disturbance of our commerce, by its authority, and which
are, in other respects, far from agreeable.
It has been my constant, sincere, and ardent wish, in conformity
with that of our nation, to maintain cordial harmony and a perfectly
friendly understanding with that Republic. This wish remains
unabated; and I shall persevere in the endeavor to fulfil it to the
utmost extent of what shall be consistent with a just and
indispensable regard to the rights and honor of our country; nor will
I easily cease to cherish the expectation that a spirit of justice,
candor, and friendship on the part of the Republic will eventually
ensure success.

My solicitude to see the Militia of the United States placed on an
efficient establishment has been so often and so ardently expressed
that I shall but barely recall the subject to your view on the present
occasion; at the same time that I shall submit to your inquiry,
whether our harbors are yet sufficiently secured.
The situation in which I now stand, for the last time, in the midst of
the Representatives of the people of the United States, naturally
recalls the period when the administration of the present form of
government commenced; and I cannot omit the occasion to
congratulate you and my country on the success of the experiment;
nor to repeat my fervent supplications to the Supreme Ruler of the
Universe and Sovereign Arbiter of Nations, that His providential care
may still be extended to the United States; that the virtue and
happiness of the people may be preserved; and that the
Government which they have instituted for the protection of their
liberties may be perpetual.
G. WASHINGTON.
United States, December 7, 1796.
When the President had concluded his Address, he presented copies
of it to the President of the Senate and the Speaker of the House of
Representatives. The President and the Senate then withdrew, and
the Speaker took the Chair. The Address was again read by the Clerk,
and on motion, committed to a Committee of the whole House to-
morrow.
Thursday, December 8.
James Gillespie, from North Carolina, appeared, and took his seat in
the House.
A new member, to wit, George Ege, from Pennsylvania, in place of
Daniel Heister, resigned, appeared, produced his credentials, was
qualified, and took his seat.

Address to the President.
On the motion of Mr. W. Smith, the House went into a Committee of
the Whole on the President's Address, according to the order of the
day. The Speech was read by the Clerk.
Mr. D. Foster moved the following resolution: |
"Resolved, That it is the opinion of this committee, that a respectful
Address ought to be presented from the House of Representatives,
to the President of the United States, in answer to his Speech to
both Houses of Congress, at the commencement of the session,
containing assurances that this House will take into consideration the
many important matters recommended to their attention."
Which was unanimously agreed to, and Mr. Ames, Mr. Baldwin, Mr.
Madison, Mr. Sitgreaves, and Mr. W. Smith were appointed a committee
to draw up the Address. The committee rose, and the resolution was
adopted by the House.
Friday, December 9.
David Bard, from Pennsylvania, Josiah Parker, from Virginia, and
Nathan Bryan, from North Carolina, appeared and took their seats in
the House.
The Speaker said, that it had been usual for the House to come to
some order on the President's Address, which was to refer it to a
Committee of the Whole on the state of the Union. On which Mr.
Williams moved, that it be committed to a Committee of the Whole
on the state of the Union, which was done accordingly.
Mr. Bayley moved, that a Committee of Commerce and Manufactures
be appointed, when Mr. William Smith, Mr. Sewall, Mr. Coit, Mr. Parker,
Mr. Blount, and Mr. Dent, were named for that committee.

Mr. Bayley then moved, that when this House adjourn, it adjourn till
Monday at eleven o'clock.
[The reason stated during the last session for the House not meeting
to do business on Saturdays was, that the standing committees were
numerous, besides many special committees for different purposes,
whose business was frequently very important and troublesome, it
was therefore necessary that Saturday be allowed for the
committees to sit, else business would be much protracted, and
become too burdensome on gentlemen in committees.]
Monday, December 12.
Several other members, to wit: from New York, Edward Livingston;
from Pennsylvania, Andrew Gregg; from Maryland, Gabriel Christie;
from Virginia, William B. Giles, Andrew Moore, and John Nicholas; and
from South Carolina, Robert Goodloe Harper, appeared, and took their
seats in the House.
Tuesday, December 13.
Two other members, to wit, Thomas Claiborne and John Page, from
Virginia, appeared and took their seats in the House.
A new member, viz: William Strudwick, from North Carolina, in place
of Absalom Tatom resigned, appeared, produced his credentials, was
qualified, and took his seat.
Mr. W. Smith then moved for the order of the day on the report of
the committee in answer to the President's Address.
Mr. Giles said, that as the printed copy of the answer was but just
laid before the House, he hoped the gentleman would not insist on

his motion, as he declared he had not had time to read it; he would
therefore move that it be deferred till to-morrow.
Mr. Parker seconded the motion. He said he was not able to judge
whether the answer would meet his approbation or not; he wished
time to be given for the consideration of it.
Mr. W. Smith said he knew no instance in which the answer to the
President's Address had been laid over, and he thought it ought to be
despatched with all possible speed.
Mr. Heath said, he hoped his colleague would not insist on his motion
for letting it lie over till to-morrow; he thought it could as well be
acted on to-day.
Mr. Ames observed, that it would look very awkward to let it lie over
till to-morrow, as it was very unusual, if not unprecedented, so to
do; he thought gentlemen might make up their minds about it if laid
on the table about an hour; they could, in the mean time, despatch
other business, which would come before them.
Mr. Giles said, he had experienced extreme inconvenience from
gentlemen pressing for a subject before it had been matured in the
minds of members; he thought it would be extremely improper and
unusual, and in its consequences disagreeable, to go into the subject
before gentlemen had time to reflect on it.
Mr. Sitgreaves said, that the more expeditious the House were on the
answer to the President's Address the greater the effect of it would
be. He hoped, therefore, that there would be no delay. He had in
recollection a Message which was received from the President
respecting the Colors of the French Republic, at the last session.
Those very gentlemen who now wished a delay, then thought that,
to let the subject lie over, would lose its principal effect, although
several of the members wished it to lie over, and but for one day.
Surely we have as much respect for the President as we have for the
French Republic. He really hoped the business would not lie over.
Mr. W. Lyman hoped gentlemen did not look upon this answer to the
President's Address as merely complimentary. He declared he took it

up in a very different light; he viewed it as of the most extensive
consequence; it related to the subjects recommended to the notice
of the House by the President, which might relate to the alteration of
the laws, and, perhaps, to the forming new laws; and could
gentlemen have time to form their minds on such an important part
of their business? He had only seen the report this morning, and
hoped he should have time to consider it before it passed through
the House.
The Speaker said, that the subject before the House now was,
whether the unfinished business should be postponed in order to
make room for a Committee of the Whole to sit on the report of the
committee on the answer?
Mr. Parker observed, that he could not say whether he approved or
disapproved of the answer before the House. He had not read the
report; he therefore hoped that the unfinished business would be
taken up and this postponed: he thought it was too important to be
hastened. He wished gentlemen to be very careful how they
committed themselves at a juncture so critical, and on business so
momentous. We had just been told by the President that we did not
stand well with the French nation; and the Senate, in their answer,
had accorded with his observations on that subject. [Mr. P. was here
informed that the business of the Senate ought not to be introduced
here.[3]] He therefore hoped a day might be allowed to take the
subject into consideration.
Mr. Williams said, he had searched and could find no precedent in
the journal to encourage a delay of this business. He found that
when a report was made by the committee on such an occasion, it
was usual to be taken up by a Committee of the whole House; and if
gentlemen disagreed on the subject, it should be recommitted to the
same committee who formed it, to make such alterations whereby it
may meet more general approbation, or be amended by the House
and passed. He hoped no new precedent would be made.
The Speaker again observed, that the question was on postponing the
unfinished business to take up this report.

Mr. W. Smith said, that if this business was delayed, it ought to be for
substantial reasons. The principal reason gentlemen had urged was,
that they had not had time to acquaint themselves with the answer.
How, then, he asked, could they make their observations on it as
they had done? The committee had, he thought, drafted it in such
general terms that it could not be generally disapproved. There are
but two parts in which he thought there would be differences of
opinion, viz: that which related to the French Republic, and that
which complimented the President for his services. As to the first, he
thought it so expressed as to need no delay in the answer. With
respect to the latter, he hoped no gentleman would refuse to pay a
due regard to the President's services.
The Speaker again informed the House what was the question.
Mr. W. Smith said, we ought not now to reflect on any thing we may
judge has not been done as we could wish. Could we refuse a
tribute of respect to a man who had served his country so much? He
thought a delay at present would have a very unpleasant
appearance. He hoped we should go into this business immediately,
agreeably to the former practice of the House on similar occasions.
The unfinished business was yesterday postponed for want of proper
information, and he thought the same reason was yet in force with
respect to it. He hoped nothing would impede this business, lest it
should appear like a want of respect in us. He hoped to see a
unanimous vote in favor of a respectful answer to the Chief
Magistrate, whose services we ought zealously to acknowledge.
Mr. Gilbert saw no reason to depart from a practice which had been
usual; he therefore hoped the report might come under
consideration to-day. He thought if it laid on the table an hour or an
hour and a half, gentlemen could then be prepared to consider it.
The Speaker again put the House in mind of the question.
Mr. Nicholas said, if the business was pressed too precipitately,
gentlemen may be sensible of their error when it was too late. Many
bad consequences might attend hastening the subject before it was

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