VLSI IEEE PROJECTS LIST 2015 - 2016 / IEEE VLSI PROJECTS LIST 2015 - 2016
- 1. VLSI IEEE PAPERS LIST 2015-16 Clarozon Technologies | 1 NO TITLE YEAR CLVLSI-01 An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability JAN 2015 CLVLSI-02 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications JAN 2015 CLVLSI-03 Recursive Approach to the Design of a Parallel Self-Timed Adder JAN 2015 CLVLSI-04 Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing JAN 2015 CLVLSI-05 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block JAN 2015 CLVLSI-06 Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories FEB 2015 CLVLSI-07 Fault Tolerant Parallel Filters Based on Error Correction Codes FEB 2015 CLVLSI-08 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations FEB 2015 CLVLSI-09 Z-TCAM: An SRAM-based Architecture for TCAM FEB 2015 CLVLSI-10 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic MAR 2015 CLVLSI-11 Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line MAR 2015 CLVLSI-12 Diagnosis and Layout Aware (DLA) Scan Chain Stitching MAR 2015 CLVLSI-13 A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS MAR 2015 CLVLSI-14 Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set MAR 2015 CLVLSI-15 An Efficient Constant Multiplier Architecture Based on Vertical- Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis APR 2015 CLVLSI-16 Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip- Flop APR 2015 CLVLSI-17 A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator MAY 2015 CLVLSI-18 Fine-Grained Fast Field-Programmable Gate Array Scrubbing MAY 2015 CLVLSI-19 Design of Efficient Content Addressable Memories in High- Performance FinFET Technology MAY 2015 CLVLSI-20 A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write- Assist MAY 2015
- 2. VLSI IEEE PAPERS LIST 2015-16 Clarozon Technologies | 2 CLVLSI-21 A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix- 2 FFT MAY 2015 CLVLSI-22 A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes MAY 2015 CLVLSI-23 Variable Latency Speculative Han-Carlson Adder MAY 2015 CLVLSI-24 Low-Power and Area-Efficient Shift Register Using Pulsed Latches JUNE 2015 CLVLSI-25 Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications JUNE 2015 CLVLSI-26 Code Compression for Embedded Systems Using Separated Dictionaries FP 2015 CLVLSI-27 Design for Testability of Sleep Convention Logic FP 2015 CLVLSI-28 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels FP 2015 CLVLSI-29 WCET-Aware Energy-Efficient Data Allocation on Scratchpad Memory for Real-Time Embedded Systems FP 2015 CLVLSI-30 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic FP 2015 CLVLSI-31 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks FP 2015 CLVLSI-32 An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating FP 2015 CLVLSI-33 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication FP 2015 CLVLSI-34 Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames FP 2015 CLVLSI-35 A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies FP 2015 CLVLSI-36 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers FP 2015 CLVLSI-37 A Novel Quantum-Dot Cellular Automata X-bit ×32-bit SRAM FP 2015 CLVLSI-38 Reliable and Error Detection Architectures of Pomaranch for False- Alarm-Sensitive Cryptographic Applications FP 2015 CLVLSI-39 A High-Speed FPGA Implementation of an RSD-Based ECC Processor FP 2015 CLVLSI-40 Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves FP 2015 CLVLSI-41 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell FP 2015 CLVLSI-42 VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm FP 2015
- 3. VLSI IEEE PAPERS LIST 2015-16 Clarozon Technologies | 3