Vlsi 2015 2016 ieee project list-(m)
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This document contains details of VLSI projects completed in 2015 and 2014. It lists 23 projects completed in 2015 related to topics like logic circuit design using single-flux-quantum, elliptic curve cryptosystem processors, approximate multipliers, reversible adders, and low power SRAM cells. It also lists 12 projects completed in 2014 on topics such as carry-select adders, shift registers, neural networks, barrel shifters, multipliers, and reversible circuitry for computations. The document appears to be listing details of student or research projects conducted by S3 Infotech in the areas of very-large-scale integration (VLSI) design and implementation.
Vlsi 2015 2016 ieee project list-(m)
- 1. S3 INFOTECH +919884848198 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com VLSI IEEE 2015 PROJECTS S.No Project Title Year IEEE 1 Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates 2015 2 Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves 2015 3 Implementation of Sub-threshold Adiabatic Logic for Ultralow-Power Application 2015 4 A Design Approach for Compressor Based Approximate Multipliers 2015 5 New Constructions of Codes for Asymmetric Channels via Concatenation 2015 6 Efficient Coding Schemes for Fault Tolerant Parallel Filters 2015 7 Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing 2015 8 Design of Optimized Reversible Binary and BCD Adders 2015 9 Design of a Low Power 4x4 Multiplier Based on Five Transistor (5-T) Half Adder, Eight Transistor (8-T) Full Adder & Two Transistor (2-T) AND Gate 2015 10 Design of Full Adder circuit using Double Gate MOSFET 2015 11 Implementation of high performance SRAM Cell Using Transmission Gate 2015 12 Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT using 9/7 and 5/3 Filters 2015 13 Self Driven Pass-Transistor based Low-Power Pulse Triggered Flip-Flop Design 2015 14 Analysis of Low Power 1-bit Adder Cells using different xor-xnor gates 2015 15 VLSI Implementation of a Key Distribution Server based Data Security Scheme for RFID system 2015 16 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications 2015 17 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block 2015 18 Partially Parallel Encoder Architecture for Long Polar Codes 2015 19 FPGA Trojans through Detecting and Weakening of Cryptographic Primitives 2015
- 2. S3 INFOTECH +919884848198 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com 20 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication 2015 21 Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology 2015 22 Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design 2015 23 Design and Analysis of Approximate Compressors for Multiplication 2015 S.No Project Title 2014 VLSI Projects Completed Year 1 Area–Delay–Power Efficient Carry-Select Adder 2014 2 Shift Register Design Using Two Bit Flip-Flop 2014 3 Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells 2014 4 Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit 2014 5 Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function 2014 6 Implementation Of Barrel Shifter using Diode free Adiabatic Logic (DFAL) 2014 7 Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes 2014 8 High Speed Vedic Multiplier Designs-A Review 2014 9 Efficient Integer DCT Architectures for HEVC 2014 10 SDR - Implementation Of Low Frequency Trans-Receiver On FPGA 2014 11 Design of Dedicated Reversible Quantum Circuitry for Square Computation 2014 12 Low power Square and Cube Architectures Using Vedic Sutras 2014