High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
Download as DOCX, PDF0 likes102 views
This document presents a new technique for constructing transformation matrices and a more efficient search algorithm to improve the hardware efficiency and speed of high-speed parallel linear feedback shift register (LFSR) architectures. The proposed LFSR architecture and search algorithm were implemented using Modelsim and Xilinx ISE software. Analysis showed the proposed architecture improved hardware efficiency by around 35% and the search algorithm found desirable transformation matrices much faster than prior methods.
1 of 1
Download to read offline
More Related Content
What's hot (13)
Ad
Similar to High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations (20)
Ad
More from JAYAPRAKASH JPINFOTECH (20)
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
- 1. High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations ABSTRACT: Linear feedback shift register (LFSR) has been widely applied in BCH and CRC encoding. In order to increase the system throughput, the parallelization of LFSR is usually needed. Previously, a technique named state-space transformation was presented to reduce the complexity of parallel LFSR architectures. Exhaustive searches are performed to find good transformation matrix candidates. This brief proposes a new technique for construction of the transformation matrix together with a more efficient searching algorithm. The realization results indicate that the proposed architecture outperforms the prior arts, improving the hardware efficiency by around 35% and the corresponding searching algorithm finds the desirable transformation matrix much faster. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. SOFTWARE IMPLEMENTATION: Modelsim Xilinx ISE