Dynamic Shift Frequency Scaling Of ATPG Patterns

Dynamic Shift Frequency Scaling of ATPG Patterns Aditya Ramachandran Open-Silicon Research Pvt.Ltd

Agenda Introduction Scan Shift Power Analysis Optimal Shift Frequency Calculation Generation of Scaled Patterns Results and Analysis Conclusion

Test time directly affects cost-per-part TEST TIME TEST COST COST-PER-PART UDSM Pattern count explosion Test time reduction is required now more than ever ! Introduction 130NM and above 90NM and below Stuck-at Transition Path-Delay Bridging Stuck-at

Background Test Time Reduction Reduction of Test Time ATPG Test Time ≈ ( # of Patterns x Length ) / Frequency Pattern Compression Adaptive Scan More Scan Chains Increase!

Factors Affecting Shift Frequency TIMING POWER Scan Shift Setup Timing Last Shift Launch Methodologies Dynamic Power Dissipation! Power ~ Switching Activity Power ~ Frequency Increased Switching -> Lower Frequency Background Shift Frequency

Background Solution Power Dissipation is limiting Shift Frequency Lower Power Dissipation Higher Shift Frequency Assertion #1 : Power Dissipation is pattern-dependent Assertion #2 : The difference is significant

Background Sample Power Analysis Results of Shift Power Analysis for Test Design Leakage Dynamic

Background Solution Power Dissipation is limiting Shift Frequency Lower Power Dissipation Higher Shift Frequency Assertion #1 : Power Dissipation is pattern-dependent Assertion #2 : The difference is significant Solution Speed up low-power patterns

Scan Shift Power Analysis Flow Power Analysis Flow Simulation Create Saif Power Analysis Testbench Netlist VCD Saif Libraries - Synopsys VCS - Serial Patterns - vcd2saif - Per-Pattern saif - PrimePower - Saif-based flow

Optimal Shift Frequencies Step #1 STEP #1: Calculate Frequency Bounds SHIFT POWER <= FUNCTIONAL POWER Pdyn(new) + Plek <= Pfunc Pdyn(new) <= Pfunc - Plek Pdyn(old) * Fshift(new) <= (Pfunc – Plek) --------------------------------- Fshift(old) Max Power Minimum Shift Frequency Min Power Maximum Shift Frequency

Optimal Shift Frequencies Step #1 Results STEP #1: Calculate Frequency Bounds (Test Design) SHIFT POWER <= FUNCTIONAL POWER 0.01102W * Fmin <= ( 0.032W – 8.3e-4W ) ---------------------- 10MHZ 0.0048W * Fmax <= (0.032W – 8.3e-4W) ---------------------- 10MHZ Fmin = 28MHZ Fmax = 65MHZ

Optimal Shift Frequencies Step #2 STEP #2: Choose a Set of Shift Frequencies Fmin <= {F1, F2.., Fn} <= Fmax Reduces Complexity! For The Test Design: {28MHZ, 37MHZ, 52MHZ, 63MHZ} {35ns, 27ns, 19ns, 16ns}

Optimal Shift Frequencies Step #3 STEP #3: Assign New Shift Frequency to Patterns Foreach Pattern: Assign Maximum Fi from {F1,F2,..Fn} such that: Pshift(Fi) <= Pfunc

Optimal Shift Frequencies Step #3 Results STEP #3: Assign New Shift Frequency to Patterns Shift Frequency Allocation (Test Design) TOTAL PATTERNS 701 28MHZ 8 37MHZ 54 52MHZ 477 63MHZ 159

Generation of Patterns Objectives Shift at multiple frequencies All else remain unchanged

Creation of STIL File Create STIL File WaveformTables for each Shift Frequency Use slowest shift table as Shift{} Waveform load_unload" { W "_default_WFT_"; C { ... } Shift { V { "_clk" = ...; "_si" = #; "_so" = #; } } ... } load_unload" { W "_default_WFT_"; C { ... } Shift { W "_SlowShift_WFT_"; V { "_clk" = ...; "_si" = #; "_so" = #; } } ... }

Generation of WGL In Tetramax Set DRC File to new STIL File Read in patterns in binary format Write out patterns in WGL format Customize (perl script) Change timeplates for the shift task of each pattern

Generation of WGL Example { pattern 1 parallel_clock basic_scan } { load_unload } vector("_default_WFT_") := [ 1 0 0.... ]; scan("_SlowShift_WFT_") := [ 1 1 0.... ], ..... { pattern 1 parallel_clock basic_scan } { load_unload } vector("_default_WFT_") := [ 1 0 0.... ]; scan("_Shift17ns_WFT_") := [ 1 1 0.... ], ..... Change timeplate for scan()

Verilog Testbench Write verilog testbench at highest shift frequency Hold is frequency-independent Setup met at highest shift will meet at lower frequencies In STIL File Set Shift Waveform to fastest shift In Tetramax Set DRC File to new STIL File Read in patterns in binary format Write out verilog testbench for verification

Generation of SDC Write SDC at highest shift frequency Hold is frequency-independent Setup met at highest shift will meet at lower frequencies In STIL File Set Shift Waveform to fastest shift In Tetramax Set DRC File to new STIL File Write SDC using write_timing_constraints

Results and Analysis Test Design Information Test Design Parameters Max Scan Length : 4892 Fault Model : Stuck-at Number of Patterns : 701

Results and Analysis Effective Shift Frequency Effective Shift Frequency TOTAL PATTERNS 701 28MHZ 8 37MHZ 54 52MHZ 477 63MHZ 159 Effective Shift Frequency = 53MHZ

Reduction in Test Time Original Patterns @ 28MHZ Scaled Patterns @ 53MHZ Max scan length = 4892 Number of patterns = 701 Shift Period = 35ns Test Time =~ 0.12 sec Max scan length = 4892 Number of patterns = 701 Shift Period = 19ns Test Time =~ 0.06 sec Test Time is reduced by ~45%

Reduction in Test Cost Original Patterns @ 28MHZ Scaled Patterns @ 53MHZ Test Time =~ 0.12 sec Test cost/sec = $0.0076 Shipping Volume = 10Million Total Cost = $91219 Test Time =~ 0.06 sec Test cost/sec = $0.0076 Shipping Volume = 10Million Total Cost = $49597 Save $41,000 per 10M parts

Advantages LOWER TEST TIME NO DESIGN CHANGES SCAN ARCHITECTURE INDEPENDENT POST-TAPEOUT/PRE-TAPEOUT

Conclusion What? Why? How? Multiple Shift Frequencies for ATPG patterns within the same pattern set To Reduce Test Time without excessive power dissipation Increase Shift Frequency of Patterns with Low Power Dissipation

Dynamic Shift Frequency Scaling Of ATPG Patterns

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Dynamic Shift Frequency Scaling Of ATPG Patterns