![stick diagram nMOS implementation
of the function f’ = [(x.y)+z]
DR.HBB notes VLSI DESIGN 24](https://image.slidesharecdn.com/vlsi-module-3-230810115728-8a8e796f/85/VLSI-Module-3-pdf-24-320.jpg)
VLSI-Module-3.pdf
- 1. STICK DIAGRAMS MODULE 3 VLSI DESIGN 17EC63/15EC63 Dr.H.B.B ACSCE Bangalore DR.HBB notes VLSI DESIGN 1
- 2. Introduction • A popular method of symbolic design ---- stick layout. • Designer draw a free hand sketch of a Layout, using coloured lines to represent various process layers such as Diffusion ( p or n) , Metal and Poly-silicon where Polysilicon layer crosses diffusion ------- Transistor are created. Metal wires join Diffusion or poly ------- contacts are formed. • Design rules are communication link b/w the designer specifying requirements and fabricator who materializes them. VLSI design aims to translate circuit concepts onto silicon. • First set of Design rules were introduced by Lambda based. DR.HBB notes VLSI DESIGN 2
- 3. • Mask design is aimed at turning a specification into masks for processing silicon to meet the specification. • Stick Diagrams may be used to convey the layer information through the use of colour code. • Note: For Depletion mode transistor, Implant within the thin oxide is a must. • Stick diagram and mask layout is one and the same ,but in mask layout ,aspect ratio (L:W) & distance between any dimensions has to be shown. • Nwell CMOS inverter: In CMOS ,we have both pmos and nmos on same substrate, so we take P-substrate and create n-well. Apply VDD to all well in mask layout. DR.HBB notes VLSI DESIGN 3
- 4. • N-well CMOS circuit are superior to p-well because of lower substrate bias effects on transistor threshold and inherently low parasitic capacitances associated with source and drain regions. • For students ,some of the hints are: if transistors are in parallel ----- construct active layer in U shape . if transistors are in series combination ----- construct active layer in zigzag shape. Demarcation Line ( Brown ) - - - - - In mask layout , n-well has to be created. P-type transistors are placed above and n-type are place below the demarcation line. DR.HBB notes VLSI DESIGN 4
- 5. • In cmos ,no depletion tr is used. • In cmos ,Diffusion path must not cross demarcation line. • n Diffusion and Diffusion wires must not join. ‘n’ and ‘p’ features are normally joined by metal where a connection is needed. • We should not forget to place a cross on Vdd and Vss rails to represent the substrate and p well respectively. • Metal and poly-silicon can cross demarcation line. ▪Does not show •Exact placement of components •Transistor sizes •Wire lengths, wire widths, tub boundaries. •Any other low level details such as parasitics.. DR.HBB notes VLSI DESIGN 5
- 6. ENCODING FOR SINGLE METAL NMOS PROCESS DR.HBB notes VLSI DESIGN 6
- 7. Encodings for CMOS process DR.HBB notes VLSI DESIGN 7
- 8. N type enhancement mode transistor G S D STICK DIAGRAM MASK LAYOUT SYMBOL 2λ x 2λ N diffusion P- diffusion DR.HBB notes VLSI DESIGN 8
- 9. N type depletion mode transistor STICK DIAGRAM SYMBOL MASK LAYOUT S D G DR.HBB notes VLSI DESIGN 9
- 10. P type enhancement mode transistor in cmos p-well process SYMBOL DR.HBB notes VLSI DESIGN 10
- 11. N type enhancement mode transistor in cmos p-well process SYMBOL G S D DR.HBB notes VLSI DESIGN 11
- 12. nMOS depletion load inverter green blue DR.HBB notes VLSI DESIGN 12
- 13. nMOS enhancement load inverter DR.HBB notes VLSI DESIGN 13
- 14. nMOS enhancement load inverter DR.HBB notes VLSI DESIGN 14
- 15. CMOS INVERTER DR.HBB notes VLSI DESIGN 15
- 16. Mask layout – CMOS INVERTER DR.HBB notes VLSI DESIGN 16
- 17. 2 INPUT – CMOS NAND GATE DR.HBB notes VLSI DESIGN 17
- 18. MASK LAYOUT –CMOS NAND GATE DR.HBB notes VLSI DESIGN 18
- 19. Two input - Nmos NAND GATE DR.HBB notes VLSI DESIGN 19
- 20. NOR gate DR.HBB notes VLSI DESIGN 20
- 21. MASK LAYOUT –CMOS NOR GATE DR.HBB notes VLSI DESIGN 21
- 22. MASK LAYOUT DR.HBB notes VLSI DESIGN 22
- 23. FUNCTION Power Ground Out A C B DR.HBB notes VLSI DESIGN 23
- 24. stick diagram nMOS implementation of the function f’ = [(x.y)+z] DR.HBB notes VLSI DESIGN 24
- 25. n-well Bi-CMOS inverter. DR.HBB notes VLSI DESIGN 25
- 26. Bi –CMOS NAND gate DR.HBB notes VLSI DESIGN 26
- 27. I bit cmos shift register • Refer module -5 for stick diagram DR.HBB notes VLSI DESIGN 27
- 28. Design Rules • Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry in silicon • Interface between circuit designer and fabrication engineer • Compromise – Circuit designer wants tighter, smaller layouts or improved performance. – Process engineer wants design rules that result in a controllable, reproducible process. • Lambda based design rules – work of Mead and Conway – used widely. DR.HBB notes VLSI DESIGN 28
- 29. Lambda Based Design Rules • Design rules based on single parameter, λ . • Simple for the designer ,Widely accepted rule. • Provide feature size independent way of setting out mask. • If design rules are obeyed, masks will produce working circuits . • Minimum feature size is defined as “2 λ”. • All paths in all layers will be mentioned in “λ” units. • Used to preserve topological features on a chip • Prevents shorting, opens, contacts from slipping out of area to be contacted DR.HBB notes VLSI DESIGN 29
- 30. Design rules for the diffusion layers and metal layers DR.HBB notes VLSI DESIGN 30
- 31. Design rules for transistors DR.HBB notes VLSI DESIGN 31
- 32. Contacts (nmos & CMOS) DR.HBB notes VLSI DESIGN 32
- 33. Contact cuts: assignments for students 3.3.2 ,3.3.3,3.3.4 • When contacts are made b/w polysilicon and diffusion in ckts, we have 2 approaches. Buried contact and butting contact Buried contact: no metal cap should be used to establish the contact. Butting contact : Metallization is used to establish contact b/e the two. DR.HBB notes VLSI DESIGN 33
- 34. What is Via? It is used to connect higher level metals from metal1 connection. The design rule for contact is minimum 2x2 and same is applicable for a Via. DR.HBB notes VLSI DESIGN 34