Lecture 1 Digital Systems and Number SystemsMatthew Shuma.docx

Lecture 1: Digital Systems and Number Systems
Matthew Shuman
Contents
1 The Digital Abstraction — 1.3 in Text 3
1.1 Analog Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 3
1.2 Digital Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 3
1.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 3
2 Number Systems — 1.4 in Text 4
2.1 Decimal Numbers — 1.4.1 in Text . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 4
2.2 Binary Numbers — 1.4.2 in Text . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 4
3 Octal and Hexadecimal Number Systems — 1.4.3 in Text 5
4 Converting Between Bases — Not in Text 6
4.1 Converting Any Base to Decimal . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 6
4.2 Converting Decimal to Any Base . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 7
4.2.1 Successive Quotients . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 7
4.2.2 Successive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 7

4.3 Quickly Converting Between Binary and Hexadecimal —
1.4.4 in Text . . . . . . . . 8
5 Complements — Not really in Text 9
5.1 Diminished Radix Complement . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 9
5.1.1 9’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 9
5.1.2 1’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 9
5.2 Radix Complement — 1.4.6 in Text . . . . . . . . . . . . . . . . . .
. . . . . . . . . 9
5.2.1 10’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 10
5.2.2 2’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 10
6 Subtracting by Adding — 1.4.6 in Text 10
7 Logic Gates — 1.5 in Text 10
7.1 Logic Gate Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 10
8 Beneath the Digital Abstraction — 1.6 in Text 11
8.1 Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 11
9 Building Gates — 1.7 in Text 11
9.1 NMOS, PMOS, and CMOS . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 11
1

10 Boolean Equations — 2.2 in Text 14
10.1 Order of Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 14
10.2 Canonical and Standard Forms . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 15
11 Boolean Algebra — 2.3 in Text 17
12 Multilevel Combinational Logic — 2.5 in Text 17
12.1 Nand And Nor Implementation . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 17
13 Logic Minimization — 2.7 in Text 18
13.1 Karnaugh Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 18
14 Combinational Logic Blocks — 2.8 in Text 21
14.1 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 21
14.2 Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 22
14.3 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 22
15 Logic Gate Timing — 2.9 in Text 23
16 Logic Block Timing — 2.9 in Text 25
17 Introduction — 3.1 in Text 25
18 Sequential Circuits — 3.1 in Text 26
19 Latches — 3.2 in Text 28

20 Flip-Flops — 3.2 in Text 29
ECE 271 Notes
1 The Digital Abstraction — 1.3 in Text
1.1 Analog Systems
Analog systems are continuous. Look at the analog clock in
figure 1. The second hand on the clock
rotates continuously around on the clock. Notice how the
fraction of a second can be estimated by
the distance of the hand between the second divisions. The
fractional value is an indicator that the
system is analog. What is the limiting factor of how precise an
analog system can be read?
Figure 1: This is a typical analog clock.
1.2 Digital Systems
Digital systems are discrete. Look at the digital clock in figure
2. The second digit moves instantly
from a 1 to a 2. There is no partial value for seconds and no
way to zoom in to gain more precision.
Precision could be increased by adding fractional digits that
measure smaller amounts of time
(tenths or hundredths of seconds).
1.3 Examples
Are for following items digital or analog?
1. The clock in the classroom?

2. The number of people in a room?
3. The voltage of a AA battery?
4. The DMM (Digital Multi Meter) measured voltage of a AA
battery?
5. The time it takes to read this question?
6. The measured time it takes to read the previous question?
ECE 271 Notes
Figure 2: This is a typical digital clock.
These examples should show that the physical properties
(distance, time, voltage, and many others)
are analog in nature, but after being measured they become
digital information. The precision of
this digital information depends directly on the quality of the
measurement device.
2 Number Systems — 1.4 in Text
2.1 Decimal Numbers — 1.4.1 in Text
The standard numbers used in the US are base ten, this is the
decimal number system. This system
uses ten different symbols to represent numbers. These symbols
are 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
Each digit in a decimal number has a specific value. The
number 1982 is represented by 1 thousand,
9 hundreds, 8 tens, and 2 ones.

2.2 Binary Numbers — 1.4.2 in Text
The number system typically used in digital logic will be base
2, this is the binary number system.
This system uses two different symbols to represent numbers, 0
and 1.
The table below shows how the binary system progresses to
more than three digits to represent
even one decimal digit.
ECE 271 Notes
Number System Decimal Binary
Zero 0 0
One 1 1
Two 2 10
Three 3 11
Four 4 100
Five 5 101
Six 6 110
Seven 7 111
Eight 8 1000
Nine 9 1001
Ten 10 1010
The standard notation to avoid confusion of 10 in decimal with
10 in binary is to add the base of
the system being used as a subscript.
(10)2 indicates two, while (10)10 indicates ten.

If no subscript is included then the number is assumed to be
decimal.
3 Octal and Hexadecimal Number Systems — 1.4.3 in Text
Other useful number systems used in digital logic are octal and
hexadecimal.
Octal uses 8 symbols to represent numbers. These symbols are
0, 1, 2, 3, 4, 5, 6, and 7.
Hexadecimal uses 16 symbols to represent numbers. These
symbols are 0, 1, 2, 3, 4, 5, 6, 7,
8, 9, A, B, C, D, E, and F.
Octal is not used very frequently, but hexadecimal is very
useful. It can be hard to read 8 bits
of binary. The 1’s and 0’s tend to blend together and it can
cause mistakes. The main use of
hexadecimal is to condense long binary strings into shorter
hexadecimal values. The table below
shows the progression used for octal and hexadecimal.
ECE 271 Notes
Number System Decimal Binary Octal Hexidecimal
Zero 0 0 0 0
One 1 1 1 1
Two 2 10 2 2
Three 3 11 3 3
Four 4 100 4 4
Five 5 101 5 5

Six 6 110 6 6
Seven 7 111 7 7
Eight 8 1000 10 8
Nine 9 1001 11 9
Ten 10 1010 12 A
Eleven 11 1011 13 B
Twelve 12 1100 14 C
Thirteen 13 1101 15 D
Fourteen 14 1110 16 E
Fifteen 15 1111 17 F
Sixteen 16 10000 20 10
The standard notation of using the subscript to indicate the base
of the number still applies.
(10)8 indicates eight, while (10)16 indicates sixteen.
4 Converting Between Bases — Not in Text
Converting between bases is initially easy, but it can quickly
become confusing when using uncom-
mon bases. The main source of confusion is when the
conversion requires math in different bases
an example of this is below.
(10)7 + (6)8 = (1101)2
This demonstrates the difficulty of even adding two small
numbers when using different bases.
A useful method is to convert the entire problem to base 10, and
after the answer has been found,
convert the answer to the desired base.

4.1 Converting Any Base to Decimal
A useful word to describe the base of a number system is radix.
The radix of a decimal number is
ten, and the radix of a binary number is two.
In order to understand how to convert numbers to base ten is it
helpful to understand how decimal
numbers are really organized. The number 365.24 is elaborated
in the equation below.
365.2410 = 3 ∗ 100 + 6 ∗ 10 + 5 ∗ 1 + 2 ∗ .1 + 4 ∗ .01
ECE 271 Notes
This progression leads to the more general equation listed
below.
365.2410 = 3 ∗ 102 + 6 ∗ 101 + 5 ∗ 100 + 2 ∗ 10−1 + 4 ∗
10−2
This form shows each digit has a different value. The 3 is in the
100’s place and the 6 is in the 10’s
place.
The following equation converts a binary number into a decimal
number.
101.1012 = 1 ∗ 22 + 0 ∗ 21 + 1 ∗ 20 + 1 ∗ 2−1 + 0 ∗ 2−2 + 1
∗ 2−3 = 4 + 1 + .5 + .125 = 5.625
The final generalized form for this equation is shown below.
d2d1d0.d−1r = d2 ∗ r
2 + d1 ∗ r1 ∗ d0 ∗ r0 + d−1 ∗ r−1 = DecimalV alue

4.2 Converting Decimal to Any Base
4.2.1 Successive Quotients
The method used to convert a decimal integer number to any
other radix is called Successive
Quotients. This method uses a recursive algorithm. Consider the
example of conversion to binary
below.
Integer Quotient Remainder
(13)10 −
(6)10 1
(3)10 0
(1)10 1
(0)10 1
1310 → 11012
The integer column begins with the decimal number being
converted. The second row is the first
row divided by the radix, the quotient on the left and the
remainder on the right. This pattern is
continued until the quotient returns 0. The conversion is read
least significant bit, LSB on the top.
The algorithm for this process is itemized below.
1. Divide the initial decimal number by the radix.
2. Place the remainder into the LSB (Least Significant Bit) digit
of the converted result.
3. Divide the current quotient by the radix.
4. Place the remainder into the next LSB digit of the converted

result.
5. Repeat Step 3 and 4 until the quotient is 0.
4.2.2 Successive Products
The process of converting decimal fractions is a similar
recursive algorithm process. Consider the
example of converting .375 into binary.
ECE 271 Notes
Fractional Product IntegerComponent
(.375)10 −
(.750)10 0
(.5)10 1
(0)10 1
.37510 → .0112
Below is the summary of this recursive process.
1. Multiply the initial decimal fraction by the radix.
2. Place the integer into the MSB (Most Significant Bit) digit of
the converted result.
3. Multiply the current fraction by the radix.
4. Place the integer into the next MSB digit of the converted
result.
5. Repeat Step 3 and 4 until the fraction is 0 or the required
number of bits have been converted.

It is important to note that some common decimal numbers can
not be represented in binary. Look
at the example converting .6 to 8 bits below.
Fractional Product IntegerComponent
(.6)10 −
(.2)10 1
(.4)10 0
(.8)10 0
(.6)10 1
(.2)10 0
(.4)10 0
(.8)10 0
(.6)10 1
(.2)10 0
.610 → .1001000102
4.3 Quickly Converting Between Binary and Hexadecimal —
1.4.4 in
Text
Binary and hexadecimal numbers are often used in digital logic
or in computer programming. It
would be possible to convert between these two bases by using
a decimal number as an intermediate
step, but there is a faster and easier method. This method uses
nibbles to divide a larger binary
or hexadecimal into smaller conversions. There are some
examples below:
Binary → Hexidecimal
(1001 1100)2 → 9 C16
(0101 1010)2 → 5 A16
(1010 1011 0111)2 → A B 716

Each group of 4 binary digits is called a nibble and can be
represented by one hexadecimal digit.
This method only works when the bases in the conversion are a
power of each other, in this instance
24 = 16 so it is valid to use the nibble short cut. It also works
for binary to octal, 23 = 8.
ECE 271 Notes
5 Complements — Not really in Text
The meaning of complement is something required to make a
thing complete. For example, salsa
complements tortilla chips, beer complements pizza, an ice
cream cone complements a hot summer
day, and apple sauce complements pork chops. A key concept to
explore is how two things com-
plement each other. For example, when a piece of pizza is
removed from a whole pizza the piece
complements what is left behind and vice versa. Each of the 4
following complements use the same
concept except in different bases and what is considered a
complete number in that base.
5.1 Diminished Radix Complement
The diminished radix complements are called by the radix − 1.
The diminished complement for a
decimal number is the 9’s complement and 1’s complement for a
binary number.
5.1.1 9’s Complement
The 9’s complement finds whatever is needed to make an entire

set of 9’s. This is shown in the
example below.
Finding the 5 digit 9’s complement of 1357
All 9′s 99999
Initial V alue −01357
−−−−
9′s Complement 98642
The 5 digit 9’s complement of 1357 is 98642
The 1’s complement finds whatever is needed to make an entire
set of 1’s. This is shown in the
example below.
All 1′s 11111111
−−−−−−−
5.2 Radix Complement — 1.4.6 in Text
The radix complements are called by their radix. The radix
complement for a decimal number is
the 10’s complement and 2’s complement for a binary number.
The value that is considered the
whole part is radixdigit.
ECE 271 Notes

radix5 100000
−−−−
radix8 100000000
−−−−−−
6 Subtracting by Adding — 1.4.6 in Text
A key use of complements is to do subtraction. Building an
adder in hardware is fairly easy, but
a subtracter is much more difficult. Using the following
mathematical property subtraction can be
avoided. A − B = A + (−B) The following example shows how
adding the radix complement can
give an identical result as subtraction.
Showing how to do 72532 - 3250 Normal Way Using
Complements
Initial Value 72532 72532
Adding a 10’s complement −3250 +96750

−−−−−− −−−−−−
Difference 69282 169282
Note the answer has a positive carry out. This means that the
difference is positive. If the carry
out was 0, then the difference would be a negative number.
Taking the radix complement of this
negative number indicates the magnitude of the negative
number.
7 Logic Gates — 1.5 in Text
This section covers the background information necessary to
understand how binary values and
functions are represented and some information about the
analog traits of a digital signal.
7.1 Logic Gate Symbols
Figure 4 shows more logic gates. Circles on the inputs or
outputs represent inverters attached to
the gates. Gates can also be built with multiple inputs, up to 8.
ECE 271 Notes
Figure 3: Here are the three fundamental logic gates, with slight
variations below them.
Figure 4: Examples of commonly used logic gates.
8 Beneath the Digital Abstraction — 1.6 in Text
8.1 Threshold Voltages

The voltage being read into a gate is an analog signal, but the
gate acts in a digital manner. This
is accomplished by using thresholds to compare the incoming
signal. Higher than a threshold is
considered a high voltage and is assigned to a 12. Lower than a
voltage is considered a low voltage
and assigned to a 02. If there is a voltage between the two
thresholds then it is considered a
metastable input and the uncertain input is assigned an ’X’. The
images in figure 5 are all from the
74HC08 Quad 2-Input And Gate.
9 Building Gates — 1.7 in Text
9.1 NMOS, PMOS, and CMOS
The PMOS and NMOS transistor are the two transitors that will
be further explored in ECE 322,
ECE 323, and other advanced courses. In ECE 271 they are
simplified to be either a short or open,
as shown in figure 6 and figure 7. Inputting a logic zero into a
PMOS will connect (short) the
source to the drain, but inputting a logic zero into the gate of an
NMOS will disconnect (open) the
source from the drain.
ECE 271 Notes
Figure 5: This table shows threshold voltages for the a discrete
quad AND gate IC.
Figure 6: PMOS transistor and 2 modes of operation.
Figure 7: NMOS transistor and 2 modes of operation.

CMOS is a technique used to build logic gates from PMOS and
NMOS transistors. PMOS transis-
tors are always located between VDD and the output, while
NMOS transistors are always located
between the output and ground. A NOT gate is built using
CMOS in figure 8 where A is the input
and Z is the output.
Figure 9 and 10 show how gates can be constructed in
integrated circuits.
RTL (Resistor Transistor Logic) is another method of making
logic gates where the PMOS is replace
with a resistor. This resistor always conducts, but can be
overpowered by the NMOS gates. When
the NMOS turn on the output is grounded to zero, but when the
NMOS turn off the resistor pulls
the output to VDD. Figure 9 shows the RTL schematic of a NOT
gate that is driving a capacitor.
ECE 271 Notes
Figure 8: Building a NOT gate using CMOS.
Figure 9: Example RTL schematic of a NOT gate. The 1 pf
capacitor is not shown in the schematic.
Figure 10 shows how a logic gate is formed inside of an IC. The
tutorial that describes the layout
tool is located here:
http://web.engr.oregonstate.edu/~moon/ece423/cadence/example
2.html
ECE 271 Notes

http://web.engr.oregonstate.edu/~moon/ece423/cadence/example
2.html
Figure 10: Example layout of a NOT gate.
10 Boolean Equations — 2.2 in Text
10.1 Order of Operations
The order of operations for standard algebra is listed below:
1. Parenthesis
2. Exponents
3. Multiplication
4. Division
5. Addition
ECE 271 Notes
6. Subtraction
A well know mnemonic for this list is ”Please Excuse My Dear
Aunt Sally”
The order of operations for Boolean algebra is listed below:
1. Parenthesis
2. Not

3. And
4. Or
What is a mnemonic for this list?
Draw the gates for the following expressions:
1. Z = AB′C + A′ ∗ C
2. Y = A + B′ + C ∗ (A′ + C)
3. X = ABC + A′ ∗ C
4. W = A + B + C + A′ ∗ C
10.2 Canonical and Standard Forms
The word canonical can be defined as being reduced to the
simplest and most significant form
possible without loss of generality. The Boolean expression Z =
A ∗ B is shown in the truth table
below. Both of these forms are complete solutions, but they are
not the simplest form.
A B Z
0 0 0
0 1 0
1 0 0
1 1 1
A simpler form to describe Z is the canonical form. There are
two canonical forms for Z. The first
form, uses Σ , is called the Sum of Products. The second form,
uses Π , is called the Product of
Sums.

1. Z(A, B) = Σ(3)
2. Z(A, B) = Π(0, 1, 2).
Canonical forms are useful for quickly communicating how a
block of digital logic operates, but
there are also standard forms for how digital logic blocks can be
constructed using logic gates.
Each canonical form has a standard form. Y = CDE′ + E is used
for the following example.
ECE 271 Notes
1. Truth Table
C D E Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
2. Canonical Forms
Y (C, D, E) = Σ(1, 3, 5, 6, 7)
Y (C, D, E) = Π(0, 2, 4)
3. Standard Forms
Figure 11: Product of Sums standard form for Y .

ECE 271 Notes
Figure 12: Sum of Products standard form for Y .
11 Boolean Algebra — 2.3 in Text
Below is a summary of the simplifications that can be done
through Boolean algebra. These should
be intuitive or memorized by the midterm.
OR Operator AND Operator
a + 0 = a a∗ 1 = x
a + a′ = 1 a∗ a′ = 0
a + a = a a∗ a = a
a + 1 = 1 a∗ 0 = 0
(a′)′ = a
a + b = b + a a∗ b = b∗ a
a + (b + c) = (a + b) + c a∗ (b∗ c) = (a∗ b) ∗ c
a∗ (b + c) = (a∗ b) + (a∗ c) a + (b∗ c) = (a + b) ∗ (a + c)
12 Multilevel Combinational Logic — 2.5 in Text
12.1 Nand And Nor Implementation
Gates can be fabricated using many different technologies. A
common technology is CMOS (Com-
plementary Metal Oxide Semiconductor). This technology uses
two transistors to make an inverter,
and four transistors to make a two-input nand or nor gate (two
transistors per input). A two input
and gate is then built using a nand gate and an inverter. It

makes sense to learn how to build logic
gates using only nand or nor gates (as well as inverters). The
sequence of figures 13, 14, and 15.
ECE 271 Notes
Figure 13: Traditional product of sums implementation using
both or and and gates.
Figure 14: DeMorgan transformation of and gate into NorB3
gate.
13 Logic Minimization — 2.7 in Text
13.1 Karnaugh Maps
Y = CDE′+E is used for the following example, which uses
standard forms to represent the digital
logic expression Y . Take special notice in how many gates are
used in figure 26 and 27.
ECE 271 Notes
Figure 15: New logic implementation using only nor gates.
1. Truth Table
C D E Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0

1 0 1 1
1 1 0 1
1 1 1 1
2. Canonical Forms
Y (C, D, E) = Π(0, 2, 4)
Y (C, D, E) = Σ(1, 3, 5, 6, 7)
3. Standard Forms
The Boolean expression for the example only uses two gates,
but figure 26 uses four gates, and
figure 27 uses six gates. A rule of thumb is that every input to
an and gate or an or gate makes
the gate bigger and slower. Every gate in the standard form has
three inputs. Standard forms
are not efficient. It would be possible to use material from
lecture three or four to minimize logic
using Boolean algebra. Boolean algebra minimizations are
tough, and there is an easier method.
Karnaugh maps minimize digital logic using a simple visual
table. Figure 18 shows a basic two
variable Karnaugh map.
There are four main rules for making minimization selections
within a Karnaugh map.
1. Selection dimensions must be a power of 2 (i.e. 1,2,4,8).
2. Selections may wrap around any edge.
3. Make the largest selections possible.
ECE 271 Notes

4. Use the fewest number of selections.
The selections in figure 19 visually indicate how to make an
optimally minimized logic block.
ECE 271 Notes
Y(c,d,e): = Σ(1,3,5,6,7)
0
0
1
1
0
2
1
3
0
4

1
5
1
6
1
7
c
d
e
Figure 18: 3 variable Karnaugh map for Y(c,d,e).
'
&
$
%
#
"
!
Y(c, d, e): = Σ(1,3,5,6,7)

0
0
1
1
0
2
1
3
0
4
1
5
1
6
1
7
c
d

e
Figure 19: 3 variable Karnaugh map with simplifications
circled. The minimization is that Y =
E + CD. The term for the selection is a minterm.
14 Combinational Logic Blocks — 2.8 in Text
14.1 Decoders
A binary decoder takes in a binary value and uses that value to
turn on a bit. The 1st output
would be turned on when 0b001 is input, and the 5th output
would be turned on when 0b101 is
input into a three bit decoder.
ECE 271 Notes
X(a,b,c): = Σ(1,5,7)
0
0
1
1
0
2
0

3
0
4
1
5
-
6
1
7
a
b
c
Figure 20: 3 variable Karnaugh map for X(a,b,c).
Figure 21: Symbol for two decoders.
14.2 Encoders
A binary encoder has many inputs and outputs a binary value
based on which input is high. The
output would be 0b001 when the 1st input is high, and the
output value would be 0b101 when the
5th input is high into the three bit encoder.

14.3 Multiplexers
A multiplexer acts like a digital switch. When the select bits are
0b01 the 1st input is forwarded
to the output and when the select bits are 0b11 the 3rd input is
forwarded to the output.
ECE 271 Notes
Figure 22: A basic two input multiplexer is on the left, and a
more complex 4 input multiplexer
with enable is on the right.
15 Logic Gate Timing — 2.9 in Text
The contamination delay, tcd, is the fastest that the logic gate
will change output after an input
changes. The propagation delay, tpd, is the slowest that the
logic gate will change output after an
input changes. For example, in the figure below the output of a
NOT gate will change between 10
ps and 15 ps after the input changes.
Figure 23: Timing diagram for a logic gate.
ECE 271 Notes
Logic Gate tpd(picoseconds) tcd(picoseconds)
NOT 15 10
2-input NAND 20 15
3-input NAND 30 25

2-input NOR 30 25
3-input NOR 45 35
2-input AND 30 25
3-input AND 40 30
2-input OR 40 30
3-input OR 55 45
2-input XOR 60 40
The images in figure 24 and 25 give examples of the
propagation delays from the 74HC08 Quad
2-Input AND gate used in ECE 272. Notice that the delays
depend on VCC and temperature.
Figure 24: This table shows propagation delays for a same IC in
figure 5
ECE 271 Notes
Figure 25: Chart depicting how the table in figure 24 is
measured.
16 Logic Block Timing — 2.9 in Text
The critical path is the longest delay path through the logic
block.
The short path is the shortest delay path through the logic
block.
Use the contamination delays and the short path to find the
contamination delay of the entire logic
block.
Use the propagation delays and the critical path to find the
propagation delay of the entire logic
block.

Calculate the timing of these standard form circuits used during
lecture 4.
Use logic minimization techniques to optimize the speed of both
of these options.
17 Introduction — 3.1 in Text
Every circuit has so far been purely combinational in ECE 271.
At any given the outputs are
only determined by the current inputs. This chapter explores the
design and construction of state
machines. Counters, stoplights, and stepper motor drivers are all
examples of these state machines.
ECE 271 Notes
18 Sequential Circuits — 3.1 in Text
Sequential circuits depend on both the current inputs and the
current state of the circuit. This
means if there are 2 inputs and 3 state bits that the
combinational logic has 5 inputs, a 5 input
karnaugh map would be needed to minimize this logic. The
outputs could turn on LEDs or control
motors. There would also be 3 outputs to the memory to control
what the next state would be.
ECE 271 Notes

This whole process is pictured in figure 28.
Figure 28: General structure for a sequential circuit
ECE 271 Notes
19 Latches — 3.2 in Text
Latches are the fundamental storage unit of memory. There are
3 basic latches below in figure 29,
30, and 31.
Figure 29: Active high SR latch
Figure 30: Active low SR latch
Figure 31: Active high SR latch with an enable input
ECE 271 Notes
Figure 32: When Enable is high the DataInput is copied to Q in
a D Latch
Figure 33: Xilinx Information Sheet on the D Latch
20 Flip-Flops — 3.2 in Text
Flip-flops are the most commonly used storage unit in digital
logic. They are more usable than

latches, because they only change at a transition of the clock,
either rising or falling edge. There
are three different types of flip flops shown in figures 34, 36,
35.
Figure 34: On the rising edge, D is copied to Q in a D Flip Flop.
ECE 271 Notes
Figure 35: A T Flip Flop toggles the output whenever T is high.
Figure 36: A JK Flip Flop can set, reset, toggle, or not toggle
the outputs, based off of the JK
inputs.
ECE 271 Notes
The Digital Abstraction — 1.3 in TextAnalog SystemsDigital
SystemsExamplesNumber Systems — 1.4 in TextDecimal
Numbers — 1.4.1 in TextBinary Numbers — 1.4.2 in TextOctal
and Hexadecimal Number Systems — 1.4.3 in TextConverting
Between Bases — Not in TextConverting Any Base to
DecimalConverting Decimal to Any BaseSuccessive
QuotientsSuccessive ProductsQuickly Converting Between
Binary and Hexadecimal — 1.4.4 in TextComplements — Not
really in TextDiminished Radix Complement9's Complement1's
ComplementRadix Complement — 1.4.6 in Text10's
Complement2's ComplementSubtracting by Adding — 1.4.6 in
TextLogic Gates — 1.5 in TextLogic Gate SymbolsBeneath the
Digital Abstraction — 1.6 in TextThreshold VoltagesBuilding
Gates — 1.7 in TextNMOS, PMOS, and CMOSBoolean
Equations — 2.2 in TextOrder of OperationsCanonical and
Standard FormsBoolean Algebra — 2.3 in TextMultilevel
Combinational Logic — 2.5 in TextNand And Nor
ImplementationLogic Minimization — 2.7 in TextKarnaugh

MapsCombinational Logic Blocks — 2.8 in
TextDecodersEncodersMultiplexersLogic Gate Timing — 2.9 in
TextLogic Block Timing — 2.9 in TextIntroduction — 3.1 in
TextSequential Circuits — 3.1 in TextLatches — 3.2 in
TextFlip-Flops — 3.2 in Text
Chapter 3 <1>
Digital Design and Computer Architecture, 2nd Edition
Chapter 3
David Money Harris and Sarah L. Harris
Chapter 3 <2>
Chapter 3 :: Topics
• Introduction
• Latches and Flip-Flops
• Synchronous Logic Design
• Finite State Machines
• Timing of Sequential Logic
• Parallelism
Chapter 3 <3>
• Outputs of sequential logic depend on current
and prior input values – it has memory.

• Some definitions:
– State: all the information about a circuit necessary
to explain its future behavior
– Latches and flip-flops: state elements that store
one bit of state
– Synchronous sequential circuits: combinational
logic followed by a bank of flip-flops
Introduction
Chapter 3 <4>
• Give sequence to events
• Have memory (short-term)
• Use feedback from output to input to store
information
Sequential Circuits
Chapter 3 <5>
• The state of a circuit influences its future
behavior
• State elements store state
– Bistable circuit
– SR Latch
– D Latch

– D Flip-flop
State Elements
Chapter 3 <6>
QQ Q
Q
I1
I2
I2 I1
• Fundamental building block of other state
elements
• Two outputs: Q, Q
• No inputs
Bistable Circuit
Chapter 3 <7>
Q
Q
I1

I2
0
1
1
0
Q
Q
I1
I2
1
0
0
1
• Consider the two possible cases:
– Q = 0:
then Q = 1, Q = 0 (consistent)
– Q = 1:
then Q = 0, Q = 1 (consistent)
• Stores 1 bit of state in the state variable, Q (or Q)
• But there are no inputs to control the state

Bistable Circuit Analysis
Chapter 3 <8>
R
S
Q
Q
N1
N2
• SR Latch
• Consider the four possible cases:
– S = 1, R = 0
– S = 0, R = 1
– S = 0, R = 0
– S = 1, R = 1
SR (Set/Reset) Latch
Chapter 3 <9>
– S = 1, R = 0:
then Q = 1 and Q = 0

– S = 0, R = 1:
then Q = 1 and Q = 0
SR Latch Analysis
R
S
Q
Q
N1
N2
0
1
1
00
0
R
S
Q
Q
N1

N2
1
0
0
10
1
Chapter 3 <10>
R
S
Q
Q
N1
N2
0
0
R
S

Q
Q
N1
N2
0
0
0
Qprev = 0 Qprev = 1
1
– S = 0, R = 0:
then Q = Qprev
– S = 1, R = 1:
then Q = 0, Q = 0
SR Latch Analysis
R
S
Q
Q
N1

N2
1
1
0
00
0
Chapter 3 <11>
R
S
Q
Q
N1
N2
0
0
R
S

Q
Q
N1
N2
0
0
0
Qprev = 0 Qprev = 1– S = 0, R = 0:
then Q = Qprev
– Memory!
– S = 1, R = 1:
then Q = 0, Q = 0
– Invalid State
Q ≠ NOT Q
SR Latch Analysis
R
S
Q
Q

N1
N2
1
1
0
00
0
Chapter 3 <12>
S
R Q
Q
SR Latch
Symbol
• SR stands for Set/Reset Latch
– Stores one bit of state (Q)
• Control what value is being stored with S, R
inputs
– Set: Make the output 1
(S = 1, R = 0, Q = 1)
– Reset: Make the output 0

(S = 0, R = 1, Q = 0)
SR Latch Symbol
Chapter 3 <13>
D Latch
Symbol
CLK
D Q
Q
• Two inputs: CLK, D
– CLK: controls when the output changes
– D (the data input): controls what the output changes to
• Function
– When CLK = 1,
D passes through to Q (transparent)
– When CLK = 0,
Q holds its previous value (opaque)
• Avoids invalid case when
Q ≠ NOT Q
D Latch

Chapter 3 <14>
S
R Q
Q
Q
QD
CLK
D
R
S
CLK
D Q
Q
S R Q QCLK D
0 X
1 0
1 1
D
D Latch Internal Circuit

Chapter 3 <15>
S
R Q
Q
Q
QD
CLK
D
R
S
CLK
D Q
Q
S R Q
0 0 Qprev
0 1 0
1 0 1
Q
1
0

CLK D
0 X
1 0
1 1
D
X
1
0
Qprev
D Latch Internal Circuit
Chapter 3 <16>
D Flip-Flop
Symbols
D Q
Q
• Inputs: CLK, D
• Function
– Samples D on rising edge of CLK
• When CLK rises from 0 to 1, D
passes through to Q
• Otherwise, Q holds its previous
value

– Q changes only on rising edge of
CLK
• Called edge-triggered
• Activated on the clock edge
D Flip-Flop
Chapter 3 <17>
CLK
D Q
Q
CLK
D Q
Q
Q
Q
D N1
CLK
L1 L2
• Two back-to-back latches (L1 and L2) controlled by

complementary clocks
• When CLK = 0
– L1 is transparent
– L2 is opaque
– D passes through to N1
• When CLK = 1
– L2 is transparent
– L1 is opaque
– N1 passes through to Q
• Thus, on the edge of the clock (when CLK rises from 0 1)
– D passes through to Q
D Flip-Flop Internal Circuit
Chapter 3 <18>
CLK
D Q
Q
D Q
Q
CLK
D
Q (latch)

Q (flop)
D Latch vs. D Flip-Flop
Chapter 3 <19>
CLK
D
Q (latch)
Q (flop)
D Latch vs. D Flip-Flop
CLK
D Q
Q
D Q
Q
Chapter 3 <20>
CLK
D Q
D Q

D Q
D Q
D0
D1
D2
D3
Q0
Q1
Q2
Q3
D3:0
4 4
CLK
Q3:0
Registers
Chapter 3 <21>
Internal
Circuit

D Q
CLKEN
D
Q
0
1
D Q
EN
Symbol
• Inputs: CLK, D, EN
– The enable input (EN) controls when new data (D) is stored
• Function
– EN = 1: D passes through to Q on the clock edge
– EN = 0: the flip-flop retains its previous state
Enabled Flip-Flops
Chapter 3 <22>
Symbols
D Q
Reset
r

• Inputs: CLK, D, Reset
• Function:
– Reset = 1: Q is forced to 0
– Reset = 0: flip-flop behaves as ordinary D flip-flop
Resettable Flip-Flops
Chapter 3 <23>
• Two types:
– Synchronous: resets at the clock edge only
– Asynchronous: resets immediately when Reset = 1
• Asynchronously resettable flip-flop requires
changing the internal circuitry of the flip-flop
• Synchronously resettable flip-flop?
Chapter 3 <24>
• Two types:
– Synchronous: resets at the clock edge only
– Asynchronous: resets immediately when Reset = 1
• Asynchronously resettable flip-flop requires
changing the internal circuitry of the flip-flop
• Synchronously resettable flip-flop?

Internal
Circuit
D Q
CLK
D QReset
Chapter 3 <25>
Symbols
D Q
Set
s
• Inputs: CLK, D, Set
• Function:
– Set = 1: Q is set to 1
– Set = 0: the flip-flop behaves as ordinary D flip-flop
Settable Flip-Flops
Chapter 3 <26>
X

Y
Z
time (ns)0 1 2 3 4 5 6 7 8
X Y Z
• Sequential circuits: all circuits that aren’t
combinational
• A problematic circuit:
Sequential Logic
Chapter 3 <27>
X Y Z
• Sequential circuits: all circuits that aren’t
combinational
• A problematic circuit:
• No inputs and 1-3 outputs
• Astable circuit, oscillates
• Period depends on inverter delay
• It has a cyclic path: output fed back to input
Sequential Logic
X
Y

Z
time (ns)0 1 2 3 4 5 6 7 8
Chapter 3 <28>
• Breaks cyclic paths by inserting registers
• Registers contain state of the system
• State changes at clock edge: system synchronized to the
clock
• Rules of synchronous sequential circuit composition:
– Every circuit element is either a register or a combinational
circuit
– At least one circuit element is a register
– All registers receive the same clock signal
– Every cyclic path contains at least one register
• Two common synchronous sequential circuits
– Finite State Machines (FSMs)
– Pipelines
Synchronous Sequential Logic Design
Chapter 3 <29>
Next
State
Current

State
S’ S
CLK
CL
Next State
Logic
Next
State CL
Output
Logic
Outputs
• Consists of:
– State register
• Stores current state
• Loads next state at clock edge
– Combinational logic
• Computes the next state
• Computes the outputs
Finite State Machine (FSM)
Chapter 3 <30>
CLK

M Nk knext
state
logic
output
logic
Moore FSM
CLK
M Nk knext
state
logic
output
logic
inputs
inputs
outputs
outputsstate
state
next
state
next
state
Mealy FSM

• Next state determined by current state and inputs
• Two types of finite state machines differ in output logic:
– Moore FSM: outputs depend only on current state
– Mealy FSM: outputs depend on current state and inputs
Finite State Machines (FSMs)
Chapter 3 <31>
TA
LA
TA
LB
TB
TB
LA
LB
Academic Ave.
B
ravado
B
lvd.

Dorms
Fields
Dining
Hall
Labs
• Traffic light controller
– Traffic sensors: TA, TB (TRUE when there’s traffic)
– Lights: LA, LB
FSM Example
Chapter 3 <32>
TA
TB
LA
LB
CLK
Reset
Traffic
Light
Controller

• Inputs: CLK, Reset, TA, TB
• Outputs: LA, LB
FSM Black Box
Chapter 3 <33>
S0
LA: green
LB: red
Reset
• Moore FSM: outputs labeled in each state
• States: Circles
• Transitions: Arcs
FSM State Transition Diagram
Chapter 3 <34>
• Moore FSM: outputs labeled in each state
• States: Circles
• Transitions: Arcs
FSM State Transition Diagram
S0
LA: green
LB: red
S1

LA: yellow
LB: red
S3
LA: red
LB: yellow
S2
LA: red
LB: green
TA
TA
TB
TB
Reset
Chapter 3 <35>
Current
State Inputs
Next
State
S TA TB S'
S0 0 X
S0 1 X

S1 X X
S2 X 0
S2 X 1
S3 X X
FSM State Transition Table
Chapter 3 <36>
Current
State Inputs
Next
State
S TA TB S'
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S2 X 1 S2
S3 X X S0
FSM State Transition Table
Chapter 3 <37>
Current State Inputs Next State
S1 S0 TA TB S'1 S'0
0 0 0 X
0 0 1 X
0 1 X X

1 0 X 0
1 0 X 1
1 1 X X
State Encoding
S0 00
S1 01
S2 10
S3 11
FSM Encoded State Transition Table
Chapter 3 <38>
Current State Inputs Next State
S1 S0 TA TB S'1 S'0
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
1 0 X 1 1 0
1 1 X X 0 0
State Encoding
S0 00
S1 01
S2 10

S3 11
S'1 = S1 ⊕ S0
S'0 = S1S0TA + S1S0TB
FSM Encoded State Transition Table
Chapter 3 <39>
Current State Outputs
S1 S0 LA1 LA0 LB1 LB0
0 0
0 1
1 0
1 1
Output Encoding
green 00
yellow 01
red 10
FSM Output Table
Chapter 3 <40>
Current State Outputs
S1 S0 LA1 LA0 LB1 LB0
0 0 0 0 1 0

0 1 0 1 1 0
1 0 1 0 0 0
1 1 1 0 0 1
Output Encoding
green 00
yellow 01
red 10
LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
FSM Output Table
Chapter 3 <41>
S1
S0
S'1
S'0
CLK
state register
Reset

r
FSM Schematic: State Register
Chapter 3 <42>
S1
S0
S'1
S'0
CLK
next state logic state register
Reset
TA
TB
inputs
S1 S0
r
FSM Schematic: Next State Logic

Chapter 3 <43>
S1
S0
S'1
S'0
CLK
next state logic output logicstate register
Reset
LA1
LB1
LB0
LA0
TA
TB
inputs outputs
S1 S0
r
FSM Schematic: Output Logic

Chapter 3 <44>
CLK
Reset
TA
TB
S'1:0
S1:0
LA1:0
LB1:0
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle
8 Cycle 9 Cycle 10
S1 (01) S2 (10) S3 (11) S0 (00)
t (sec)
??
??
S0 (00)
S0 (00) S1 (01) S2 (10) S3 (11) S1 (01)

??
??
0 5 10 15 20 25 30 35 40 45
Green (00)
Red (10)
S0 (00)
Yellow (01) Red (10) Green (00)
Green (00) Red (10)Yellow (01)
S0
LA: green
LB: red
S1
LA: yellow
LB: red
S3
LA: red
LB: yellow
S2
LA: red
LB: green
TA

TA
TB
TB
Reset
FSM Timing Diagram
Chapter 3 <45>
• Binary encoding:
– i.e., for four states, 00, 01, 10, 11
• One-hot encoding
– One state bit per state
– Only one state bit HIGH at once
– i.e., for 4 states, 0001, 0010, 0100, 1000
– Requires more flip-flops
– Often next state and output logic is simpler
FSM State Encoding
Chapter 3 <46>
• Alyssa P. Hacker has a snail that crawls down a paper tape
with 1’s and 0’s on it. The snail smiles whenever the last two
digits it has crawled over are 01. Design Moore and Mealy
FSMs of the snail’s brain.
Moore vs. Mealy FSM

Chapter 3 <47>
Mealy FSM: arcs indicate input/output
State Transition Diagrams
Moore FSM
Reset
S0
0
S1
0
S2
1
0
0 1
1 0
1
Reset
S0 S1
1/1
0/0

1/0 0/0
Mealy FSM
Chapter 3 <48>
Current
State Inputs Next State
S1 S0 A S'1 S'0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
State Encoding
S0 00
S1 01
S2 10
Moore FSM State Transition Table
Chapter 3 <49>
Current

State Inputs Next State
S1 S0 A S'1 S'0
0 0 0 0 1
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
State Encoding
S0 00
S1 01
S2 10
Moore FSM State Transition Table
S1’ = S0A
S0’ = A
Chapter 3 <50>
Current State Output
S1 S0 Y
0 0
0 1
1 0
Y = S1

Moore FSM Output Table
Chapter 3 <51>
Current State Output
S1 S0 Y
0 0 0
0 1 0
1 0 1
Y = S1
Moore FSM Output Table
Chapter 3 <52>
Current
State Input
Next
State Output
S0 A S'0 Y
0 0
0 1
1 0
1 1
State Encoding
S0 00

S1 01
Mealy FSM State Transition & Output Table
Chapter 3 <53>
Current
State Input
Next
State Output
S0 A S'0 Y
0 0 1 0
0 1 0 0
1 0 1 0
1 1 0 1
State Encoding
S0 00
S1 01
Mealy FSM State Transition & Output Table
Chapter 3 <54>
Moore FSM Schematic
Y

CLK
Reset
A
r
S'0 S0
S'1 S1
Chapter 3 <55>
Mealy FSM Schematic
S'0 Y
CLK
Reset
A
r
S0
Chapter 3 <56>
Moore & Mealy Timing Diagram

Mealy Machine
Moore Machine
CLK
Reset
A
S
Y
S
Y
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle
8 Cycle 9 Cycle 10
S0 S2?? S2 S2S0 S1
1 0 1 1 0 1 1 10
S1
S0 S0?? S0 S1 S0S1
S1 S0
S1
Cycle 11

Chapter 3 <57>
• Break complex FSMs into smaller interacting
FSMs
• Example: Modify traffic light controller to have
Parade Mode.
– Two more inputs: P, R
– When P = 1, enter Parade Mode & Bravado Blvd
light stays green
– When R = 1, leave Parade Mode
Factoring State Machines
Chapter 3 <58>
Unfactored FSM
Factored FSM
Controller
FSMTA
TB
LA
LB
P
R

Mode
FSM
Lights
FSM
P
M
Controller
FSM
TA
TB
LA
LB
R
Parade FSM
Chapter 3 <59>
S0
LA: green
LB: red
S1
LA: yellow

LB: red
S3
LA: red
LB: yellow
S2
LA: red
LB: green
TA
TA
TB
TB
Reset
S4
LA: green
LB: red
S5
LA: yellow
LB: red
S7
LA: red
LB: yellow

S6
LA: red
LB: green
TA
TA
P
P P
P
P
P
R
R
R
R
R
P
R
P
TAP

TAP
P
TAR
TAR
R
TBR
TBR
Unfactored FSM
Chapter 3 <60>
S0
LA: green
LB: red
S1
LA: yellow
LB: red
S3
LA: red
LB: yellow
S2
LA: red

LB: green
TA
TA
M + TB
MTB
Reset
Lights FSM
S0
M: 0
S1
M: 1
P
Reset P
Mode FSM
R
R
Factored FSM
Chapter 3 <61>
• Identify inputs and outputs
• Sketch state transition diagram

• Write state transition table
• Select state encodings
• For Moore machine:
– Rewrite state transition table with state encodings
– Write output table
• For a Mealy machine:
– Rewrite combined state transition and output table with state
encodings
• Write Boolean equations for next state and output logic
• Sketch the circuit schematic
FSM Design Procedure
Chapter 3 <62>
• Flip-flop samples D at clock edge
• D must be stable when sampled
• Similar to a photograph, D must be stable
around clock edge
• If not, metastability can occur
Timing
Chapter 3 <63>
CLK

tsetup
D
thold
ta
• Setup time: tsetup = time before clock edge data must be
stable (i.e. not changing)
• Hold time: thold = time after clock edge data must be stable
• Aperture time: ta = time around clock edge data must be
stable (ta = tsetup + thold)
Input Timing Constraints
Chapter 3 <64>
CLK
tccq
tpcq
Q
• Propagation delay: tpcq = time after clock edge that the
output Q is guaranteed to be stable (i.e., to stop changing)
• Contamination delay: tccq = time after clock edge that Q
might be unstable (i.e., start changing)
Output Timing Constraints

Chapter 3 <65>
• Synchronous sequential circuit inputs must be
stable during aperture (setup and hold) time
around clock edge
• Specifically, inputs must be stable
– at least tsetup before the clock edge
– at least until thold after the clock edge
Dynamic Discipline
Chapter 3 <66>
• The delay between registers has a
minimum and maximum delay, dependent
on the delays of the circuit elements
CL
CLKCLK
R1 R2
Q1 D2
(a)
CLK
Q1

D2
(b)
Tc
Dynamic Discipline
Chapter 3 <67>
• Depends on the maximum delay from register R1
through combinational logic to R2
• The input to register R2 must be stable at least tsetup
before clock edge
CLK
Q1
D2
Tc
tpcq tpd tsetup
CL
CLKCLK
Q1 D2
R1 R2
Tc ≥

Setup Time Constraint
Chapter 3 <68>
before clock edge
CLK
Q1
D2
Tc
tpcq tpd tsetup
CL
CLKCLK
Q1 D2
R1 R2
Tc ≥ tpcq + tpd + tsetup
tpd ≤

Chapter 3 <69>
before clock edge
CLK
Q1
D2
Tc
tpcq tpd tsetup
CL
CLKCLK
Q1 D2
R1 R2
Tc ≥ tpcq + tpd + tsetup
tpd ≤ Tc – (tpcq + tsetup)
Chapter 3 <70>
• Depends on the minimum delay from register R1

through the combinational logic to R2
• The input to register R2 must be stable for at least
thold after the clock edge
CLK
Q1
D2
tccq tcd
thold
CL
CLKCLK
Q1 D2
R1 R2
thold <
Hold Time Constraint
Chapter 3 <71>
CLK

Q1
D2
tccq tcd
thold
CL
CLKCLK
Q1 D2
R1 R2
thold < tccq + tcd
tcd >
Chapter 3 <72>
CLK
Q1
D2

tccq tcd
thold
CL
CLKCLK
Q1 D2
R1 R2
thold < tccq + tcd
tcd > thold - tccq
Chapter 3 <73>
CLK CLK
A
B
C
D
X'
Y'
X
Y

pe
r
ga
te
Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
thold = 70 ps
tpd = 35 ps
tcd = 25 ps
tpd =
tcd =
Setup time constraint:
Tc ≥
fc =
Hold time constraint:
tccq + tcd > thold ?
Timing Analysis

Chapter 3 <74>
CLK CLK
A
B
C
D
X'
Y'
X
Y
pe
r
ga
te
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
thold = 70 ps

tpd = 35 ps
tcd = 25 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
Tc ≥ (50 + 105 + 60) ps = 215 ps
fc = 1/Tc = 4.65 GHz
(30 + 25) ps > 70 ps ? No!
Timing Analysis
Chapter 3 <75>
pe
r
ga
te
tccq = 30 ps
tpcq = 50 ps

tsetup = 60 ps
thold = 70 ps
tpd = 35 ps
tcd = 25 ps
tpd =
tcd =
Tc ≥
fc =
Timing Analysis
CLK CLK
A
B
C
D
X'
Y'

X
Y
Add buffers to the short paths:
Chapter 3 <76>
pe
r
ga
te
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
thold = 70 ps
tpd = 35 ps
tcd = 25 ps
tpd = 3 x 35 ps = 105 ps
tcd = 2 x 25 ps = 50 ps
Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz
(30 + 50) ps > 70 ps ? Yes!
Timing Analysis
CLK CLK
A
B
C
D
X'
Y'
X
Y
Add buffers to the short paths:
Chapter 3 <77>
• The clock doesn’t arrive at all registers at same time

• Skew: difference between two clock edges
• Perform worst case analysis to guarantee dynamic
discipline is not violated for any register – many
registers in a system!
t skew
CLK1
CLK2
CL
CLK2CLK1
R1 R2
Q1 D2
CLKdelay
CLK
Clock Skew
Chapter 3 <78>
• In the worst case, CLK2 is earlier than CLK1
CLK1
Q1

D2
Tc
tpcq tpd tsetuptskew
CL
CLK2CLK1
R1 R2
Q1 D2
CLK2
Tc ≥
Setup Time Constraint with Skew
Chapter 3 <79>
CLK1
Q1
D2
Tc
CL

CLK2CLK1
R1 R2
Q1 D2
CLK2
Tc ≥ tpcq + tpd + tsetup + tskew
tpd ≤
Chapter 3 <80>
CLK1
Q1
D2
Tc
CL
CLK2CLK1
R1 R2
Q1 D2

CLK2
Tc ≥ tpcq + tpd + tsetup + tskew
tpd ≤ Tc – (tpcq + tsetup + tskew)
Chapter 3 <81>
• In the worst case, CLK2 is later than CLK1
tccq tcd
thold
Q1
D2
tskew
CL
CLK2CLK1
R1 R2
Q1 D2
CLK2
CLK1
tccq + tcd >

Hold Time Constraint with Skew
Chapter 3 <82>
tccq tcd
thold
Q1
D2
tskew
CL
CLK2CLK1
R1 R2
Q1 D2
CLK2
CLK1
tccq + tcd > thold + tskew
tcd >

Chapter 3 <83>
tccq tcd
thold
Q1
D2
tskew
CL
CLK2CLK1
R1 R2
Q1 D2
CLK2
CLK1
tccq + tcd > thold + tskew
tcd > thold + tskew – tccq
Chapter 3 <84>
CLK

tsetup thold
taperture
D
Q
D
Q
D
Q ???
C
as
e
I
C
as
e
II
C
as
e
III
D Q

CLK
bu
tto
n
• Asynchronous (for example, user)
inputs might violate the dynamic
discipline
Violating the Dynamic Discipline
Chapter 3 <85>
metastable
stablestable
• Bistable devices: two stable states, and a metastable
state between them
• Flip-flop: two stable states (1 and 0) and one
metastable state
• If flip-flop lands in metastable state, could stay there
for an undetermined amount of time
Metastability
Chapter 3 <86>
R

S
Q
Q
N1
N2
• Flip-flop has feedback: if Q is somewhere between
1 and 0, cross-coupled gates drive output to either
rail (1 or 0)
• Metastable signal: if it hasn’t resolved to 1 or 0
• If flip-flop input changes at random time, probability
that output Q is metastable after waiting some time, t:
P(tres > t) = (T0/Tc ) e-t/τ
tres : time to resolve to 1 or 0
T0, τ : properties of the circuit
Flip-Flop Internals
Chapter 3 <87>
• Intuitively:
– T0/Tc: probability input changes at a bad time (during
aperture)

– τ: time constant for how fast flip-flop moves away from
metastability
• In short, if flip-flop samples metastable input, if you wait
long enough (t), the output will have resolved to 1 or 0
with high probability.
Metastability
Chapter 3 <88>
D Q
CLK
S
Y
N
C
• Asynchronous inputs are inevitable (user interfaces,
systems with different clocks interacting, etc.)
• Synchronizer goal: make the probability of failure (the
output Q still being metastable) low
• Synchronizer cannot make the probability of failure 0
Synchronizers

Chapter 3 <89>
D
Q
D2 Q
D2
Tc
tsetup tpcq
CLK CLK
CLK
tres
metastable
F1 F2
• Synchronizer: built with two back-to-back flip-flops
• Suppose D is transitioning when sampled by F1
• Internal signal D2 has (Tc - tsetup) time to resolve to 1
or 0
Synchronizer Internals
Chapter 3 <90>

D
Q
D2 Q
D2
Tc
tsetup tpcq
CLK CLK
CLK
tres
metastable
F1 F2
For each sample, probability of failure is:
P(failure) = (T0/Tc ) e-(Tc - tsetup)/τ
Synchronizer Probability of Failure
Chapter 3 <91>
• If asynchronous input changes once per second,
probability of failure per second is P(failure).

• If input changes N times per second, probability of failure
per second is:
P(failure)/second = (NT0/Tc) e-(Tc - tsetup)/τ
• Synchronizer fails, on average, 1/[P(failure)/second]
• Called mean time between failures, MTBF:
MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc - tsetup)/τ
Synchronizer Mean Time Between Failures
Chapter 3 <92>
D D2 Q
CLK CLK
F1 F2
• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps
T0 = 150 ps tsetup = 100 ps
N = 1 events per second
• What is the probability of failure? MTBF?
Example Synchronizer
Chapter 3 <93>
D D2 Q

CLK CLK
F1 F2
• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps
T0 = 150 ps tsetup = 100 ps
N = 1 events per second
• What is the probability of failure? MTBF?
P(failure) = (150 ps/2 ns) e-(1.9 ns)/200 ps
= 5.6 × 10-6
P(failure)/second = 10 × (5.6 × 10-6 )
= 5.6 × 10-5 / second
MTBF = 1/[P(failure)/second] ≈ 5 hours
Example Synchronizer
Chapter 3 <94>
• Two types of parallelism:
– Spatial parallelism
• duplicate hardware performs multiple tasks at once
– Temporal parallelism
• task is broken into multiple stages
• also called pipelining
• for example, an assembly line
Parallelism

Chapter 3 <95>
• Token: Group of inputs processed to produce
group of outputs
• Latency: Time for one token to pass from
start to end
• Throughput: Number of tokens produced
per unit time
Parallelism increases throughput
Parallelism Definitions
Chapter 3 <96>
• Ben Bitdiddle bakes cookies to celebrate traffic light
controller installation
• 5 minutes to roll cookies
• 15 minutes to bake
• What is the latency and throughput without parallelism?
Parallelism Example
Chapter 3 <97>
• Ben Bitdiddle bakes cookies to celebrate traffic light
controller installation

• 5 minutes to roll cookies
• 15 minutes to bake
• What is the latency and throughput without parallelism?
Latency = 5 + 15 = 20 minutes = 1/3 hour
Throughput = 1 tray/ 1/3 hour = 3 trays/hour
Parallelism Example
Chapter 3 <98>
• What is the latency and throughput if Ben
uses parallelism?
– Spatial parallelism: Ben asks Allysa P. Hacker to
help, using her own oven
– Temporal parallelism:
• two stages: rolling and baking
• He uses two trays
• While first batch is baking, he rolls the
second batch, etc.
Parallelism Example
Chapter 3 <99>
Latency = ?
Throughput = ?

Spatial Parallelism
S
pa
tia
l
P
ar
al
le
lis
m Roll
Bake
Ben 1 Ben 1
Alyssa 1 Alyssa 1
Ben 2 Ben 2
Alyssa 2 Alyssa 2
Time
0 5 10 15 20 25 30 35 40 45 50
Tray 1
Tray 2
Tray 3

Tray 4
Latency:
time to
first tray
Legend
Chapter 3 <100>
Throughput = 2 trays/ 1/3 hour = 6 trays/hour
Spatial Parallelism
S
pa
tia
l
P
ar
al
le
lis
m Roll
Bake

Ben 1 Ben 1
Alyssa 1 Alyssa 1
Ben 2 Ben 2
Alyssa 2 Alyssa 2
Time
0 5 10 15 20 25 30 35 40 45 50
Tray 1
Tray 2
Tray 3
Tray 4
Latency:
time to
first tray
Legend
Chapter 3 <101>
Te
m
po
ra

l
P
ar
al
le
lis
m Ben 1 Ben 1
Ben 2 Ben 2
Ben 3 Ben 3
Time
0 5 10 15 20 25 30 35 40 45 50
Latency:
time to
first tray
Tray 1
Tray 2
Tray 3
Latency = ?
Throughput = ?
Temporal Parallelism

Chapter 3 <102>
Te
m
po
ra
l
P
ar
al
le
lis
m Ben 1 Ben 1
Ben 2 Ben 2
Ben 3 Ben 3
Time
0 5 10 15 20 25 30 35 40 45 50
Latency:
time to
first tray
Tray 1

Tray 2
Tray 3
Throughput = 1 trays/ 1/4 hour = 4 trays/hour
Using both techniques, the throughput would be 8 trays/hour
Temporal Parallelism
Slide Number 1Slide Number 2Slide Number 3Slide Number
4Slide Number 5Slide Number 6Slide Number 7Slide Number
8Slide Number 9Slide Number 10Slide Number 11Slide Number
12Slide Number 13Slide Number 14Slide Number 15Slide
Number 16Slide Number 17Slide Number 18Slide Number

Number 100Slide Number 101Slide Number 102
ECE271, Chapter 1 Reading Report
Matthew Shuman
October 3, 2017
For this and all homework assignments, you should show
enough work that the assignment
is self supporting. Write out the problem, explain any
researched information needed to solve
the problem, and show your work in an organized manner. I
encourage you as students to post
questions onto Canvas concerning this assignment. Debate and
discuss these questions in a manner
that helps you learn this material.
1 Chapter Outline
Chapter 1 addresses a broad range of topics, but all of these
concepts form the foundation for
understanding the rest of this textbook.
1. The Game Plan
Digital logic is the foundation for some of the largest
companies in Oregon and the United
States. Digital systems are simple and operate on zeros and
ones.
2. The Art of Managing Complexity

Discipline, modularity, and the three Y’s make it possible for
the mass production of complex
items. Abstraction is the concept of hiding details, for example
a complex set of planets
revolving around the sun can be abstracted as 8 smaller balls
rotating around a larger yellow
ball. Discipline is the concept of carefully and purposefully
restricting your models to only
include necessary features, maximizing the benefits of
abstraction. For example, modeling
the Earth as a pale blue dot[1] enables a more efficient model of
our solar system. Hierarchy,
Modularity, and Regularity are the three Y’s and are critical
concepts that get leveraged in
chapters 2-5 in the textbook.
3. The Digital Abstraction
A digital bit stores either a 1 or a 0, regardless of the actual
mechanism used to store this
data. A 1 could represent a voltage above 3 volts and 0 be a
voltage below 2 volts, a 1 could
represent a mechanical switch that has been flipped to the left
and a 0 to the right, or a 1
could represent a powered block of redstone from Minecraft[2]
while a 0 represents an idle
redstone block.
4. Number Systems
There are four main sections in this section of the Chapter.
Number systems are introduced,
number systems are converted, number systems are added, and
then number systems are
complemented to represent negative numbers.

5. Logic Gates
There are four main gates discussed in this section: NOT, AND,
OR, and XOR. Their
negated counterparts are BUFFER, NAND, NOR, and XNOR.
6. Beneath the Digital Abstraction
Analog voltages range between 0 volts and the supply voltage,
VCC, as a continuous spec-
trum. This range is divided into specific regions based on four
specified voltages limits,
VIL, VIH, VOL, andVOH.
1
7. CMOS Transistors Transistors are the fundamental building
blocks for logic gates. They are
semiconductor devices, similar to a diode. A diode is a PN
junction, whereas a transistor
is a npn or a pnp transistor. nMOS and pMOS transistors
connect their drain and source
terminals, based on the voltage applied to their gate input.
Logic gates, such as the AND
and OR gates can be constructed by using PMOS transistors as a
pull-up network coupled
with nMOS transistors as a pull-down network.
8. Power Consumption
There are two components to power consumption, static and
dynamic power.
Pstatic = IDDVDD (1)

IDD is the leakage current through the digital logic and VDD is
the supply voltage powering
the digital logic.
Pdynamic =
1
2
CV 2DDf (2)
C is the capacitance of the digital logic, relating to the number
of logic gates used in the
design. f is the clock frequency of the digital logic.
9. Summary and Look Ahead
Best joke of the chapter: "There are 10 kinds of people in this
world: those who can count
in binary and those who can’t."
The summary provides information reviewing the prior 8
sections of chapter 1. It then relates
this content to the remainder of the textbook, with chapters 2
through 5 being the study of
digital logic.
2 Grey Box Exploration
1. The first blurb is on page 20, where According to Larry Wall,
inventor of the Perl program-
ming language, "the three principal virtues of a programmer are
Laziness, Impatience, and
Hubris". Larry wall is an interesting fellow, who was born on
September 27th 1949. He also
created the Perl programming language and has two critical
rules for his guidance of the
direction and functionality of Perl.

(a) Larry is always by definition right about how Perl should
behave. This means he has
final veto power on the core functionality.
(b) Larry is allowed to change his mind about any matter at a
later date, regardless of
whether he previously invoked Rule 1.
Larry is always right, even when contradicting his prior
decisions[3]. He was featured in a
Big Think video where he talked 5 programming languages
everyone should know:
(a) Javascript
(b) Java
(c) Haskell
(d) C
(e) Scripting (Python, Perl, Ruby)
2. The second blurb is on page 13, where processor and
microprocessor are described as, A
microprocessor is a processor built on a single chip. Until the
1970’s, processors were too
complicated to fit on one chip, so mainframe processors were
built from boards containing
many chips. Intel introduced the first 4-bit microprocessor, call
the 4004, in 1971. Now, even
the most sophisticated supercomputers are built using are built
using microprocessors. We will
use the terms microprocessor and processor interchangeably
throughout this book. Intel is the
largest private employer in the state of Oregon. They directly
employ 16,500 people in the
state of Oregon and can be indirectly attributed with the 67,579.
These jobs attributed to
Intel pay almost $80,000, which is almost twice the average

personal income of an Oregonian,
$43,000[4].
2
3 Figures
Two figures were selected from this chapter for special
recognition. Figure 1.11 was selected for
the effectiveness in showing how different number systems have
specific ranges for the same binary
values. Unsigned numbers can only be positive, while 2’s
complement and Sign/Magnitude can
represent negative numbers at a cost of increased range.
Figure 1: Different number systems and their respective values.
Figure 1.31 was selected for highlighting the opposing nature of
pMOS and nMOS transistors. A
zero input on the gate will connect a pMOS transistor, but it
would disconnect a nMOS transistor.
Figure 2: nMOS and pMOS transition tables.
4 Example Problems
This section is attached to the assignment submission in a
separate PDF of scanned work done
neatly on engineering paper.
5 Glossary
All definitions were found from the Google search engine,
typing "define analog" for the first item.
1. Analog:

adjective: relating to or using signals or information represented
by a continuously variable
physical quantity such as spatial position or voltage.
noun: a person or thing seen as comparable to another.
2. Discrete:
adjective: individually separate and distinct.
3
3. Discreet:
adjective: careful and circumspect in one’s speech or actions,
especially in order to avoid
causing offense or to gain an advantage.
4. Compliment:
noun: a polite expression of praise or admiration.
verb: politely congratulate or praise (someone) for something.
5. Complement
noun:
1. a thing that completes or brings to perfection. "the libretto
proved a perfect comple-
ment to the music" synonyms: accompaniment, companion,
addition, supplement, accessory,
trimming "the perfect complement to the food"

2. a number or quantity of something required to make a group
complete.
6. nibble
verb:
1. take small bites out of. "he sat nibbling a cookie"
2. show cautious interest in a project or proposal. "there’s a
New York agent nibbling"
noun:
1. an instance of nibbling something. synonyms: bite, gnaw,
chew; taste "the fish enjoyed a
nibble on the lettuce"
2. an expression of cautious interest in a project or proposal.
"now and then she gets a
nibble, but no one will commit to an interview"
6 Interview Question
Figure 3: A king counts his money.
The obvious answer being asked from the concepts covered in
the textbook would be 6, because
26 is 64. This calculation would be applicable if you split the
money into two piles, weighed them,
and then took the lighter side. 64 becomes 32 with one weighing
of the scale. The progression
would be 64 to 32 to 16 to 8 to 4 to 2 to 1, yielding 6
measurements of the scale. But this is a
non-ideal answer.

It would be possible to divide the money into three piles,
weighing 2 piles, and leaving the 3rd
one aside. In the event of a tie, the omitted pile would contain
the counterfeit. Dividing the piles
into thirds would be impossible, because 64 divides unevenly. I
propose initial piles of 27, 27, and
10. Assuming the worst case, the counterfeit would be in a pile
of 27, which would be divided into
3. The progression for the worst case would be 64 to 27 to 9 to
3 to 1, yielding an answer in just
4 measurements. This saves the king drastic amounts of time.
The real challenge was presented by Captain Holt of Brooklyn
99[5].
7 Reflection
I found that this chapter covered a broad array of concepts and
ideas. The lack of focus is because
this chapter provides many fundamental concepts to support
digital design. Digital abstractions,
number systems, and logic gates provide a theoretical
foundation for digital logic. Voltages, tran-
sistors, and power analysis explore the hardware concepts for
digital design. The easiest part of
4
this chapter was doing binary to decimal conversions, because I
did that in a prior course. The
hardest part to understand was CMOS, because I’ve never seen
a circuit before.
I’m eager to see how these topics will be explored in lecture,
and to have a chance to ask some

questions and solve some example problems.
8 Questions for Lecture
1. Is there an easier way to convert octal numbers into
hexadecimal numbers?
2. How are CMOS circuits developed for gates besides the AND
and OR standard gates?
3. I understand nMOS and pMOS transistors and drew the
schematic for 1.87, but I get confused
with the 8 different transistors. How do I start analyzing this
circuit?
References
[1] o. b. o. C. S. Ken Takahashi, “Pale blue dot video.”
https://www.youtube.com/watch?v=
XH7ZRF6zNoc.
[2] gamepedia, “Redstone.”
http://minecraft.gamepedia.com/Redstone_circuit.
[3] Wiki, “Larry hall.”
https://en.wikipedia.org/wiki/Larry_Wall.
[4] C. Batten, “Economic impact of intel’s 2012 oregon
operations.” http:
//www.intel.com/content/dam/www/public/us/en/documents/rep
orts/
intel-oregon-economic-impact-report.pdf.
[5] FOX, “12 islanders video.”
https://www.youtube.com/watch?v=Cs-TGLxQfBM.
5

https://www.youtube.com/watch?v=XH7ZRF6zNoc
https://www.youtube.com/watch?v=XH7ZRF6zNoc
http://minecraft.gamepedia.com/Redstone_circuit
https://en.wikipedia.org/wiki/Larry_Wall
http://www.intel.com/content/dam/www/public/us/en/documents
/reports/intel-oregon-economic-impact-report.pdf
https://www.youtube.com/watch?v=Cs-TGLxQfBMChapter
OutlineGrey Box ExplorationFiguresExample
ProblemsGlossaryInterview QuestionReflectionQuestions for
Lecture

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