Design of New Single-phase Multilevel Voltage Source Inverter

International Journal of Power Electronics and Drive System (IJPEDS)
Vol. 5, No. 1, July 2014, pp. 45~55
ISSN: 2088-8694  45
Journal homepage: http://iaesjournal.com/online/index.php/IJPEDS
Design of New Single-phase Multilevel Voltage Source
Inverter
Rasoul Shalchi Alishah*, Daryoosh Nazarpour*, Seyyed Hossein Hosseini**, Mehran Sabahi**
* Departement of Electrical and Computer Engineering, Urmia University, Iran
** Departement of Electrical Engineering, Tabriz Universitu, Iran
Article Info ABSTRACT
Article history:
Received Mar 1, 2014
Revised May 4, 2014
Accepted May 20, 2014
Multilevel inverters with more number of levels can produce high quality
voltage waveforms. In this paper, a new single-phase structure for multilevel
voltage source inverter is proposed which can generate a large number of levels
with reduced number of IGBTs, gate driver circuits and diodes. Three
algorithms for determination of dc voltage sources’ magnitudes are presented
which provide odd and even levels at the output voltage waveform. A
comparison is presented between proposed multilevel inverter and conventional
cascade topology. The proposed topology is analyzed by the experimental and
simulation results.
Keyword:
Asymmetric
Cascade
Full-bridge converter
Multilevel inverter
Symmetric Copyright © 2014 Institute of Advanced Engineering and Science.
All rights reserved.
Corresponding Author:
Rasoul Shalchi Alishah,
Departement of Electrical and Computer Engineering,
Urmia University,
Iran.
Email: Rasoul.shalchi@gmail.com
1. INTRODUCTION
Multilevel inverters are power electronic systems which produce a suitable AC output voltage
waveform from several dc voltages as inputs [1]. In recent years, Multilevel inverters have been utilized in
medium and high power applications such as flexible AC transmission system (FACTS) [2], industrial motor
drives [3], traction electric vehicle applications, drive systems [4], [5] and so on.
Multilevel inverters in comparison with the traditional two-level voltage inverter have advantages
such as smaller output voltage level, better electromagnetic compatibility, lower harmonic components and
lower switching losses [6], [7]. There are three renowned kinds of multilevel inverter which have been called
classical multilevel inverter topologies. These are Neutral-Point Clamped (NPC), Flying capacitor (FC) and
Conventional cascade H-bridge inverter (CHB) [8]-[10].
Conventional cascade topology is the most important topology among classical topologies. Because
this topology needs the least number of power electronic devices and can produce many levels at output
voltage [11], [12]. A cascade multilevel inverter consists of a number of H-bridge converter units with
separate dc source for each unit and it is connected in cascade or series [13]. In symmetric cascade multilevel
inverter, DC voltage sources of similar cells are the same. For the same number of power electronic
components, asymmetric cascade multilevel topologies significantly increase the number of level at output
voltage waveforms. In these topologies, DC voltage sources of different cells are non-equal [14], [15].
However, this structure requires to a large number of unidirectional switches. The most important Part in
multilevel inverters is switches which increase the cost and control complexity and tend to reduce the overall
reliability and efficiency [16], [17].
In this paper, a new structure for multilevel voltage source inverter is presented which can generate

 ISSN: 2088-8694
IJPEDS Vol. 5, No. 1, July 2014 : 45 – 55
46
many levels with minimum number of IGBTs, gate driver circuits and diodes.
2. THE STRUCTURE OF CONVENTIONAL CASCADE MULTILEVEL INVERTER
The structure of conventional cascade multilevel inverter is shown in Figure 1. The output voltage
of cascade inverter is obtained by summing the output voltages of full-bridges and is obtained by the
following relationship:
…     (1)
Figure 1. The structure of conventional cascade multilevel inverter
In this structure, each switch consists of an IGBT and one diode (or anti-parallel diode). If all dc
voltage sources in Figure 1 are the same, the inverter is known as symmetric multilevel inverter. To provide a
large number of output levels without increasing the number of power electronic elements, asymmetric
multilevel inverters can be used. In [16], [17], the dc voltages sources are proposed to be chosen according to
a geometric progression with a factor of two or three, which are called binary and trinary configurations. In
symmetric, binary and trinary configurations, the magnitudes of dc voltage sources are selected by the
following equations:
For symmetric configuration:
⋯             (2)
For mth full-bridge converter in binary configuration:
2            1,2, … ,    (3)
For mth full-bridge converter in trinary configuration:
3             1,2, … ,      (4)
Where V represents the magnitude of voltage of the first full-bridge converter. Table 1 shows the number of
IGBTs, levels, maximum output voltage and the relation between the number of IGBTs and levels in
symmetric and asymmetric configurations.

IJPEDS ISSN: 2088-8694 
Design of New Single-phase Multilevel Voltage Source Inverter (Rasoul Shalchi Alishah)
47
Table 1. Power component requirments in conventional cascade inverter
Symmetric
Structure
Asymmetric Structure
Binary
configuration
Trinary
configuration
Number of IGBTs 4n 4n 4n
Voltage levels 2n+1 (2 -1 3
maximum output voltage n×V (2 1 V
3 1 V
2
Relation between the number of
IGBTs and levels
2 N 1 4 1 4
ln N
ln 3
Where n represents the number of dc voltage sources. It is important to note that in all configurations, the
numbers of IGBTs, gate driver circuits and diodes (or anti-parallel diodes) are the same.
3. PROPOSED MULTILEVEL INVERTER
Figure 2 shows the basic unit topology for proposed multilevel inverter, which consists of a diode,
an IGBT and a dc voltage source. In this circuit, when the Sswitch is turned off, the output voltage will be
zero, but when the Sswitch is turned on, the diode is reverse biased and the output voltage will be V. Hence,
by the use of this method the output voltage is controlled. This method is the basic of proposed multilevel
inverter.
Figure 2. The basic unit of proposed multilevel
inverter
Figure 3. Proposed single-phase multilevel voltage
source inverter topology
The proposed basic unit shown in Figure 2 can be extended as shown in Figure 3, which is called
Multiple Basic Unit (MBU). The MBU can increase the possible values of V́o. The MBU generates a
staircase voltage waveform ( ´ with positive polarity (0, , , , … , .The MBU is connected to a full-
bridge converter, which particularly alternates the input voltage polarity and generates positive or negative
staircase waveform ( at the output 0, , , … , . The proposed single-phase multilevel voltage

 ISSN: 2088-8694
48
source inverter topology, which is based on the combination of MBU and a full-bridge converter, is shown in
Figure 3.
Table 2 Shows the ON switches look-up table for proposed single-phase multilevel inverter
topology.
Table 2. Magnitudes of ´ and for different states of switches in proposed structurs
In the proposed inverter, the number of IGBTs can be determined by (5):

(5)
In the proposed structure, the switches are unidirectional. Each unidirectional switch consists of an
IGBT and an anti-parallel diode. In the recommended structure,the number of diodes is given by following
equation:
     (6)
4. DETERMINATION OF THE DC VOLTAGE SOURCES MAGNITUDES
In this section, three algorithms for determination of the dc voltage sources magnitudes are
proposed.
a) First algorithm:
In this algorithm, the values of dc sources are the same. Hence, we have:
⋯            (7)
This structure is called symmetric topology. Using this algorithm, the number of output voltage
levels and maximum output voltage are given by (8) and (9), respectively:
2 1    (8)
(9)
Using (5) and (8), the relation between the number of IGBTs and levels is obtained as follows:
(10)

49
From (6) and (8), the relation between the number of power diodes and output levels is calculated by
following equation:
3          (11)
b) Second algorithm:
In this algorithm, the dc source magnitudes are chosen according the following equations:
        (12)
= 2V       2, 3, 4, … ,    (13)
In the proposed algorithm, the number of levels and maximum output voltage are given as follows:
4 1    (14)
2 1     (15)
Considering (5) and (14), we have:
(16)
Using (6) and (14), it is obvious that we have:
(17)
c) Third algorithm:
In this algorithm, the values of dc sources are proposed to be chosen according to the following
equations:
     (18)
2          2, 3,4, … , (19)
For this method, the number of levels and the peak output voltage are calculated using the following
relationships, respectively:
2 1     (20)
2 1        (21)
The third algorithm for the determination of values of dc sources is in binary fashion, which results
in an exponential increase in the number of overall output voltage levels.
In above equations n represents the number of dc voltage sources. From (5) and (20), we have:
3       (22)
Also, considering (6) and (20), it is clear that we have
2 2    (23)
The second and third algorithms are called asymmetric topologies. The proposed multilevel voltage
source inverter could be a suitable power converter candidate in unidirectional power flow applications such
as wind turbine with permanent magnet (PM) or Synchronous Generator (SG) and photovoltaic systems
application and so on.

 ISSN: 2088-8694
50
5. COMPARISON OF PROPOSED STRUCTURE WITH CONVENTIONAL CASCADE
STRUCTURE
Power IGBTs are the most important element in multilevel inverter structures which define the
circuit size, reliability, cost, control complexity and installation area. Figure 4 compares the number of
IGBTs versus the number of levels for the first recommended structure (or symmetric structure) with
symmetric conventional cascade topology. It is obvious that the proposed symmetric topology needs fewer
IGBTs to realize for output voltage waveform.
Figure 4. Comparison of for the first recommended structure with symmetric conventional cascade
Figure 5 shows the number of IGBTs versus the number of output levels for the asymmetric
recommended structures (the second and third algorithms) with binary and trinary conventional cascade
inverter structures. This figure shows the third proposed algorithm requires less number of IGBTs than other
structures to realize N for .
Figure 5. Comparison of for the asymmetrical recommended structures with binary and trinary
conventional cascade
It is important to note that in proposed topology, the number of IGBTs and gate driver circuits are
the same. Hence, the third suggested topology requires minimum number of gate drivers. The gate driver
circuits are the electronic part of the circuit and increasing the number of gate driver circuits is a considerable
deﬁciency. Because increasing gate driver cause increasing costs and control complexity.
Figure 6 compares the number of diodes versus the number of levels in the symmetric proposed
topology and symmetric conventional cascade inverter. As shown in this figure, the proposed symmetric
topology requires fewer numbers of diodes than symmetric cascade topology.

51
Figure 6. Comparison of to realize voltages in the proposed symmetric topology and symmetric
conventional cascade
Figure 7 shows the number of diodes versus the number of output voltage levels in the asymmetric
proposed topologies and conventional cascade inverter. This figure shows that the number of diodes in
thirdalgorithm of proposed topology is lower than other topologies.
Figure 7. Comparison of N to realize voltages in the proposed asymmetric topologies and
asymmetric conventional cascade
6. EXPERIMENTAL AND SIMULATION RESULTS
Figure 8. Proposed 15-level asymmetric inverter
according to the second algorithm
Figure 9. Photo of the archetype

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In this section, the simulation and experimental results for the 15-level asymmetric topology
(according to the second algorithm) is studied. The MATLAB software is utilized for simulation. Figure 8
shows 15-level asymmetric inverter structure based on the second proposed algorithm. Figure 9 shows photo
of the archetype.
The inverter consists of four DC voltage sources with magnitudes of 30V and 60V. A test has been
made on the R-L load (R = 140Ω and L = 40mH).The switches are IRFP450 MOSFET’s with internal anti-
parallel diodes. The gate drivers are TLP250 and diodes are MUR460.
The total harmonic distortion (THD) evaluates the quantity of harmonic contents in the output
waveform and is a popular performance index for power converters. Several modulation techniques have
been introduced for multilevel inverters such as sinusoidal PWM, space vector PWM, selective harmonic
elimination, fundamental frequency-switching and others [18]-[24].
In this paper, the fundamental frequency-switching strategy has been used. The beneﬁt of the
fundamental frequency-switching technique is its low switching frequency compared to other control
strategies [25]. It is noticeable that the calculation of the optimal switching angles for different objective such
as the elimination of selected harmonics and minimizing the total harmonic distortion is not the objective of
this paper. Table 3 shows the magnitude of output voltage for various states of switches in suggested 15-level
asymmetric structure.
Table 3. Switches states for 15-level asymmetric topology
Figure 10 shows the control block diagram for proposed topology.
Figure 10. Control block diagram for proposed topology
The simulation and measurement results are shown in Figure 11. According to the simulations,
THDs of the output voltage and current are 3.83% and 1.17%, respectively. This figuresshows that the
simulationsand experimental results have a good agreement to each other.To generate a desired output with
high power quality, the number of voltage levels should be increased.

53
(a) (b)
1A
(c) (d)
Figure 11. Simulation and measurement results (Time/div =2 ms) and (Voltage/div =10 V by1:10probe): (a)
Experimental output voltage;(b) Simulation output voltage and harmonic spectrum (THD=3.83%); (c)
Experimental output current; (d)Simulationoutput current and harmonic spectrum (THD= 1.17%).
7. CONCLUSION
In this paper, a new multilevel voltage source inverter has been proposed. For proposed structure,
three algorithms have been presented for determination of dc sources values. These algorithms can generate
all levels (odd and even) at the output voltage waveform. The comparison between the proposed topology
and the conventional cascade topology has been presented. It was shown that the third algorithm required
minimum number of IGBTs, gate drivers and diodes.The simulation and experimental results have been
presented for a 15-level inverter based on the second algorithm to validate the ability of the proposed
topology in generating of desired output voltage.
REFERENCES
[1] JN Chiasson, LM Tolbert, KJ McKenzie, Z Du. Control of Multilevel converter Using Resultant Theory. IEEE
Trans. On Cont. Sys. Tech., 2003; 11(3): 345-354.
[2] NH Kim. Rotor fault detection system for inverter driven induction motor using current signals and an Encoder.
Journal of Power Electronics. 2007; 7(4): 271-277.
[3] MF Aiello, PW Hammond, M Rastogi. Modular Multi-Level Adjustable Supply with Parallel Connected Active
Inputs. U.S. Patent. 2001.
[4] LM Tolbert, FZ Peng, TG Habetler. Multilevel Inverters for Electric Vehicle Applications. IEEE Workshop on
Power Electronics in Transportation. 1998; 1424-1431.
[5] MN Abdul Kadir, S Mekhilef, HW Ping. Dual vector control strategy for a three –stage hybrid cascaded multilevel
inverter. Journal of power Electronic. 2010; 10(2): 155-164.
[6] JH Kim, SK Sul, PN Enjeti. A carrier-based PWM method with optimal switching sequence for a multilevel four-leg
voltage-source inverter. IEEE Trans. Ind. Appl., 2008; 44(4): 1239-1248.

 ISSN: 2088-8694
54
[7] LM Tolbert, FZ Peng, T Cunnyngham, JN Chiasson. Charge Balance Control Schemes for Cascade Multilevel
Converter in Hybrid Electric Vehicles. IEEE Trans. Industrial Electronics, Vol. 49, No. 5, pp. 1058-1064, Oct.
2002.
[8] A Nami, F Zare, A Ghosh, F Blaabjerg. A hybrid cascade converter topology with series-connected symmetrical and
asymmetrical diode-clamped H-bridge cells. IEEE Trans. Power Electron., 2011; 26(1): 51–64.
[9] J Li, S Bhattacharya, AQ Huang. A new nine-level active NPC (ANPC) converter for grid connection of large wind
turbines for distributed generation. IEEE Trans. Power Electron., 2010; 26(3): 961–972.
[10] J Ebrahimi, E Babaei, Goverg B Gharehpetian. A New Multilevel Converter Topology With Reduced number of
Power Electronic Components. IEEE Trans. on Ind. Elec., 2012; 59(2): 655-667.
[11] E Babaei, SH Hosseini. New cascaded multilevel inverter topology with minimum number of switches. Elsevier J.
Energy Convers.Manage., 2009; 50(11): 2761–2767.
[12] E Babaei, SH Hosseini, GB Gharehpetian, M Tarafdar Haque, M Sabahi. Reduction of dc voltage sources and
switches in asymmetrical multilevel converters using a novel topology. Elsevier J. Electric Power Syst. Res., 2007;
77(8): 1073–1085.
[13] E Babaei. A cascade multilevel converter topology with reduced numberof switches. IEEE Trans. Power Electron.
2008; 23(6): 2657–2664.
[14] E Babaei, MS Moeinian. Asymmetric cascaded multilevel inverter with charge balance control of a low resolution
symmetric subsystem. J. Energy Convers. Manag., 2010; 51(11): 2272–2278.
[15] RA Ahmed, S Mekhilef, HW Ping. New multilevel inverter topology with reduced number of Switches. Proc.
International Middle East Power Systems Conf., 2010; 565-570.
[16] Manjrekar M, Lipo TA. A hybrid multilevel inverter topology for drive application. Proc. of the APECp. 1998; 523–
529.
[17] Rufer A, Veenstra M, Gopakumar A. Asymmetric multilevel converter for high resolution voltage phasor
generation. European conference on power electronics and applications, Switzerland. 1999.
[18] D Sasi, J Kuruvilla, A Gopinath. Generalized SVPWM Algorithm for Two Legged Three Phase Multilevel
Inverter. International Journal of Power Electronics and Drive Systems (IJPEDS), 2013; 3(3): 279-286.
[19] S Mekhilef, MN Abdul Kadir. Novel vector control method for three-stage hybrid cascaded multilevel inverter.
IEEE Trans. on Ind. Elec., 2010; 1339-1349.
[20] MG Hosseini Aghdam, SH Fathi, GB Gharehpetian. Analysis of Multi-Carrier PWM Methods for Asymmetric
Multi-Level Inverter. IEEE Conf. on Ind. Elect. and Appl., 2008; 2057-2062.
[21] Shantanu Chatterjee. A Multilevel Inverter Based on SVPWM Technique for Photovoltaic Application.
International Journal of Power Electronics and Drive Systems (IJPEDS), 2013: 3(1): 62-73.
[22] R Shalchi Alishah, D Nazarpour, SH Hosseini, M Sabahi. Switched-diode structure for multilevel converter with
reduced number of power electronic devices. IET Power Electron., 2014; 7(3): 648 – 656.
[23] E Villanueva, P Correa, J Rodriguez, M Pacas. Control of a single-phase cascaded H-bridge multilevel inverter for
grid-connected photo-voltaic systems. IEEE Trans. Ind. Electron., 2009; 56(11): 4399-4406.
[24] R Shalchi Alishah, D Nazarpour, SH Hosseini, M Sabahi. New hybrid structure for multilevel inverter with fewer
number of components for high-voltage levels. IET Power Electron., 2014; 7(1): 96–104.
[25] R Shalchi Alishah, D Nazarpour, SH Hosseini, M Sabahi. Novel Topologies for Symmetric, Asymmetric and
Cascade Switched-Diode Multilevel Converter with Minimum Number of Power Electronic Components. IEEE
Trans. Ind. Electron., 2014; 61(10):5300-5310.
BIOGRAPHIES OF AUTHORS
Rasoul Shalchi Alishah was born in Alishah, Iran, in1989. He received the B.Sc. degree in Power
electrical engineering from the Azad University of Tabriz, Tabriz, Iran, in 2011and the M.Sc.
degree in power electrical engineering from Urmia University, Urmia, Iran, in 2013.
His current research interests include power electronic converters, multilevel converters, Z-source
and matrix converters, Application of Power Electronics in Renewable Energy Systems, Harmonics
and Power Quality. Since 2014, he has been a member of the Iran Elites National Foundation. He is
the author of more than 20 journal and conference papers. Also, he is a reviewer and Editorial
Board member of several international journals.
Daryoosh Nazarpour was born in Urmia, Iran in1958. He received his B.Sc. degree from Iran
University of Science and Technology, Tehran, Iran in 1982 and the M.Sc. degree from Faculty of
Engineering, University of Tabriz, Tabriz, Iran in 1988. He received the Ph.D. degree from Tabriz
University, in 2005 in Electrical Power Engineering. He is now an Assistant Professor inUrmia
University, Iran. His research interests include power electronics, and flexible ACtransmission
system (FACTS).

55
Seyed Hossein Hosseini was born in Marand,Iran, in 1953. He received the M.S. degree from
theFaculty of EngineeringUniversity of Tabriz, Iran in1976, the DEA degree from INPL, France, in
1978and the Ph.D. degree from INPL, France, in 1981 all in electrical engineering.
In 1982, he joined theUniversity of Tabriz, Iran, asanAssistant Professor in the Department of
ElectricalEngineer. From 1990 to 1995, he was an AssociateProfessor in the University of Tabriz.
Since 1995, hehas been Professor in the Department of ElectricalEngineer, University of Tabriz.
From Sept. 1990 to Sept. 1991, he was visitingprofessor in the University of Queensland, Australia.
From Sept. 1996 to Sept.In 1997, he was visiting professor in the University of Western Ontario,
Canada.
His research interests include Power Electronic Converters, Matrix Converters, Active&Hybrid
Filters, Application of Power Electronics in Renewable EnergySystems and Electriﬁed Railway
Systems, Reactive Power Control, Harmonics and Power Quality Compensation Systems such as
SVC, UPQC, FACTSdevices.
Mehran Sabahi was born in Tabriz, Iran, in 1968. He received the B.Sc. degree in electronic
engineering from the University of Tabriz, the M.Sc. degree in electrical engineering from
TehranUniversity, Tehran, Iran, and the Ph.D. degree in electrical engineering from the University
of Tabriz, in 1991, 1994, and 2009, respectively. In 2009, he joined the Faculty of electrical and
computer engineering, University of Tabriz, where he has been an assistant professor since 2009.
His current research interests include power electronic converters and renewable energy systems.

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