Lecture6 Chapter4- Design Magnitude Comparator Circuit, Introduction to Decoders.pdf
- 1. Chapter4: Combinational Logic Lecture6- Design Comparator Circuit, Introduction to Decoders Engr. Arshad Nazir, Asst Prof Dept of Electrical Engineering SEECS 1 Fall 2022
- 2. Objectives • Design Magnitude Comparator • Introduction to Decoders 2 Fall 2022
- 3. Magnitude Comparator • The comparison of two numbers is an operation that determines if one number is greater than, less than or equal to the other number • A magnitude comparator is a combinational circuit that compares two numbers, A and B and determines their relative magnitudes • The outcome of the comparison is specified by three binary variables that indicates whether A>B, A=B or A<B 3 Fall 2022
- 4. Magnitude Comparator • If we follow the traditional design approach of truth table then comparing two n-bit numbers will have 22n entries in the truth table and becomes too complicated for large values of n. • However, a comparator circuit possess a certain amount of regularity. Digital functions that possess an inherent well defined regularity can usually be designed by means of algorithmic procedure. This reduce design efforts and reduce human errors • An algorithm is a procedure that specifies a finite set of steps, if followed, give the solution to a problem. The algorithm is direct application of the procedure a person uses to compare the relative magnitude of two numbers 4 Fall 2022
- 5. Developing Algorithm • Consider the two numbers A and B, with four digits each, the coefficients of numbers with descending significance can be written as: A = A3A2A1A0 and B = B3B2B1B0 • The two numbers are equal if all pairs of significant digits are equal: A=B if A3=B3, A2=B2, A1=B1and A0=B0 • For binary (either 1 or 0) digits the equality relation of each pair of bits can be expressed logically with exclusive-NOR function to test if Ai = Bi as xi = (Ai Bi)' = (AiBi'+Ai'Bi)' = AiBi+Ai'Bi' for i = 0,1,2,3 xi = 1 only if the pair of bits in position i are equal otherwise xi = 0 • Therefore we can check if A = B by (A=B) = x3x2x1x0 • The symbol (A=B) is binary output variable that is equal to 1 only if all pair of digits of the two numbers are equal 5 Fall 2022
- 6. Developing Algorithm • To determine if A>B or A<B, we inspect the relative magnitudes of pairs of significant digits starting from the most significant position. If the two digits are equal, we compare the next lower significant pair of digits. This comparison continues until a pair of unequal digits is reached • If the corresponding digit of A is 1 and that of B is 0, we conclude that A>B. If the corresponding digit of A is 0 and that of B is 1, we conclude that A<B • The sequential comparison can be expressed logically by the two Boolean functions (A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0' (A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0 • The symbols (A>B) and (A<B) are binary output variables that are equal to 1when A>B or A<B respectively 6 Fall 2022
- 7. Developing Algorithm • The gate implementation for a magnitude comparator involves a certain amount of repetition so it is simpler than it seems. • The unequal outputs can use the same gates that are needed to generate the equal output • The logic diagram of the 4-bit magnitude comparator is shown in Figure 4 – 17 • The four x outputs are generated with exclusive-NOR circuits and applied to an AND gate to give the output binary variable (A=B) • The other two outputs use the x variable to generate the Boolean functions • The procedure for obtaining magnitude comparator circuits for binary numbers with more than four bits is obvious from the above steps 7 Fall 2022
- 8. Decides if A3=B3 x3 = (A3B3'+A3'B3)' =(A3 B3)' x3A2'B2 = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0' = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0 8 Fall 2022
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- 10. Decoders • A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. Only one output can be active (high) at any time. • Decoders are a class of combinational logic circuits that convert a set of input variables representing a code into a set of output variables representing a different code. The relationship between the input and output codes can be expressed in a truth table i.e 4-to-10-lines decoder circuit. • If the n-bit coded information has unused combinations, the decoder has fewer than 2n outputs 10 Fall 2022
- 11. Decoder Applications • Generate minterms/complement of minterms and are used for functions implementation. • Memory addressing- Decoders are widely used in the memory system of a computer where they respond to the address code generated by the central processor to activate a particular memory location. • Code Conversion. Example is BCD-to-7-segment decoder. • DeMUX function. • Used in conjunction with counters to decode (detect) counter states and provide timing or sequencing signals. • Provide enabling inputs when used in the design of MUXs with tri-state gates. • Computers communicate with peripheral devices (printers, modems, scanners, keyboards, video monitors, external disk drives and other computers) by sending and/or receiving data through I/O ports. Decoders are used to select I/O as determined by the computer to receive or send data. 11 Fall 2022
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- 13. Implementation of Full Adder with a Decoder • There are three inputs and eight outputs so we need 3-to-8-line decoder • Two OR gates are required for logical sum of the desired minterms 13 Fall 2022
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- 15. Decoder Example (Code Converter) • BCD-to-seven-segment display converter is one common example of code converters, which converts one BCD digit into information suitable for driving a digit-oriented display. 15 Fall 2022
- 16. Demultiplexer • A decoder with an enable input (Figure 4-19) can function as demultiplexer (1-to-4-line demultiplexer) E is taken as data input line and A and B are takes as selection inputs 16 Fall 2022
- 17. • Counters may be used to generate timing signals to control the sequence of operations in a digital system. 2n timing signals can be generated using an n-bit binary counter together with an n-to- 2n-line decoder Timing Signals Generation using Counters 17 Fall 2022
- 18. MUX Design using Tri-State gates and Decoders 18 Fall 2022