12-Bit 1MSps SAR ADC For System-On-Chip

시-비 - 지팓2.0
팓 팓 팓 팓 팓 팓
l 팓 물 팓 , , 송, 시, 팓 팓 송 팓 팓 .
팓 팓 팓 팓 :
l , 팓 물 팓 팓 팓 , 팓 물 팓 팓
팓 팓 타 팓 .
l 터팓 팓 팓 팓 팓 팓 지팓 .
팓 팓 팓 팓 팓 팓 팓 팓 지팓 .
팓 (Legal Code) 팓 팓 팓 팓 .
Disclaimer
시. 팓 팓 시 팓 .
비 . 팓 팓 물 팓 팓 팓 팓 팓 .
지. 팓 팓 물 팓 , 팓또 팓 팓 팓 .

Thesis for the Degree of Master of Engineering
12-bit 1MSps SAR ADC for
System-on-Chip
by
Murod Kurbanov
Department of Information and Communications Engineering
The Graduation School
Pukyong National University
February, 2017

Thesis for the Degree of Master of Engineering
System-on-Chip
시스템-온-칩을 위한 12 비트 1MSps SAR ADC
Advisor: Professor. Jee-Youl Ryu
by
Murod Kurbanov
Pukyong National University
Department of Information and Communications Engineering
February, 2017

i
CONTENT
Abstract
1. Introduction 1
2. ADC operation principles and basic concepts 4
2.1 Structure and operating principle of ADC 4
2.2 The main performance indices and formulas of ADC 7
2.3 SAR ADC structure and operation principle 9
3. The proposed SAR ADC circuit and analysis 16
3.1 Sample-and-Hold stage 17
3.2 Capacitor array network stage 20
3.3 Comparator stage 26
3.4 SAR control logic stage 28
3.5 DAC control logic stage 30
3.6 DAC stage 31

ii
3.7 SAR ADC 33
4. Results and Analysis 36
4.1 SAR ADC simulation results 36
4.2 SAR ADC implementation and performance evaluation 46
5. Conclusions 48
References 49

iii
Figure List
Figure 2.1 ADC symbol 4
Figure 2.2 Conventional ADC system block diagram 5
Figure 2.3 Typical ADC with various bits and sampling rates 7
Figure 2.4 DNL and INL characteristics of ADC 8
Figure 2.5 General SAR ADC 10
Figure 2.6 Code decision procedure of 3-bit SAR ADC 12
Figure 2.7 12-bit charge-redistribution SAR ADC 15
Figure 3.1 The proposed SAR ADC 16
Figure 3.2 Schematic of sample-and-hold stage 18
Figure 3.3 Sample-and-hold stage layout 19
Figure 3.4 Capacitor array network of proposed SAR ADC 21
Figure 3.5 Comparison of SAR ADC capacitor array network stage 23
Figure 3.6 Layout of capacitor array network stage 25
Figure 3.7 Comparator stage 28
Figure 3.8 SAR control logic stage 30

iv
Figure 3.9 DAC control logic stage 31
Figure 3.10 DAC stage 32
Figure 3.11 DAC stage layout 33
Figure 3.12 Symbol block diagram of SAR ADC 34
Figure 3.13 Layout of SAR ADC 35
Figure 4.1 Simulation results of sample-and-hold 37
Figure 4.2 Input(T1, T2) and output waveform(TN, TP) of pre-
amplifier 38
Figure 4.3 Simulation results of comparator 40
Figure 4.4 Clock timing diagram of SAR control logic 41
Figure 4.5 Simulation results of DAC control logic 43
Figure 4.6 Simulation results of 12-bit DAC stage 45
Figure 4.7 FFT result of SAR ADC 46

v
Table List
Table 4.1 Summary and comparison of SAR ADC performance 47

vi
12-bit 1MSps SAR ADC for System-on-Chip
Abstract
Over the past ten years, as integrated circuits became increasingly more complex and
expensive, the industry began to embrace new design and to reuse methodologies that are
collectively referred to as System-on-Chip (SoC) design. To solve these problems,
analog-to-digital converter (ADC) is required in SoC.
This thesis focuses on the design of successive approximation register (SAR) ADC for
SoC. The proposed of SAR ADC contains Sample-and-Hold stage, capacitor array, SAR
control logic stage, comparator stage, DAC stage, and DAC control logic stage. This
SAR ADC is designed to have performance of 12-bit resolution. The proposed circuit is
designed using Magnachip/SK Hynix 0.18μm CMOS 1Poly-6Metal process, and it is
powered by 1.5V supply. To reduce chip area and power consumption, we minimized
unit capacitor area and number of the total capacitors, and designed the circuit
optimization as compared to conventional circuits. The proposed circuit in this thesis
showed high signal-to-noise distortion ratio (SNDR) of 71.18dB, and excellent effective
number of bit (ENOB) 11.53-bit as compared to conventional research results. The
designed circuit also showed very low power consumption of 1.95mW, and small chip
area of 0.54mm². The proposed ADC is applicable for the signal conversion of the
industry system application.

1
1 Introduction
Significant resources have been used with the vast performance. The design
tasks have interlinked with scheming between the edifice blocks of circuits and
the gathering of sufficient supporting circuit logic to comprehend a system-on-
chips (SoCs). Soc is the integrated system which integrates all of the system
circuits on a single chip. It is the most advanced form which uses powerful
processors and various peripherals for running Windows and Linux. SoC consists
of the embedded hardware and software which controls processors, controllers
and other peripherals [1-3].
Most ADC applications can be classified into four broad market segments such
as data acquisition, precision industrial measurement, voice band and audio and
high speed system with sampling rates of greater than 5 MSps (5 Mega Sampling
per second). A very large percentage of these applications can be filled by
successive-approximation register (SAR) ADCs, sigma-delta (Σ-Δ) ADCs, and
pipelined ADCs. A basic understanding for the three most popular ADC
architectures and their relationship to the market segments is a useful to
supplement the selection guides and search engines. The 10-bit flash ADC is
mainly the fastest ADC among all the ADC types. In flash ADC of n-bit in size,

2
(2n
-1) comparators and 2n
registers are needed. It is very fast as mentioned but it
requires for example, many parts of 1023 comparators for 10-bit ADC, lower
resolution, expensive cost and large power consumption. Pipeline ADC with a
resolution of less than 16 bits has fast sampling rate of tens KHz ~ hundreds MHz
but it also has a disadvantage in power consumption. Further, SAR ADC has a
resolution similar to the pipelined ADC, and its sampling rate (speed) is a
relatively low. However, the SAR ADC has the advantage of reducing the area of
the design because of the blocks of the internal recycle. Therefore, the SAR ADC
is suitable to have a low power and low area, for designing a 12-bit ADC with a
proper resolution. As it can be seen in previous studies, ADC requires
development with a low-power and low-area domain consistent with the
particular application [4-12].
In this thesis, we propose a SAR ADC with low power and low area. The
capacitor array and switched capacitor used in the general structure of the SAR
ADC, may occupy a large area. To solve this problem, the capacitor array and
sample-and-hold stage with a bootstrap switch are proposed by structural change
to reduce the number of capacitors. It is possible to reduce the power
consumption due to the reduced capacitor.

3
In Chapter 2 of this thesis, we explain the basic concept of a common ADC,
and describe the operating principle of SAR ADC. Chapter 3 describes the
proposed SAR ADC circuit of each stage, for its interpretation. Chapter 4
analyzes the results and performance analysis through implementation and
evaluation of the proposed SAR ADC. Chapter 5 finally concludes the result and
performance summary of this thesis.

4
2 ADC operation principles and basic concepts
In this chapter, we describe the concept and operating principle of a typical
ADC, and describe the performance and characterization of the ADC.
2.1 Structure and operating principle of the ADC
Figure 2.1 shows the typical ADC symbol. In electronics, an ADC is a system
that converts an analog input signal into a digital output signal, and it is widely
used in various industries such as information communication field, the video
signal field, medical devices, and the computer filed.
Figure 2.1 ADC symbol

5
Figure 2.2 is conventional ADC system block diagram. When the analog signal
is input and the inserted signal is sampled by the sample-and-hold stage for
digital encoding, ADC stage receives the sampled signal from sample-and-hold
stage, and it provides the digital data to the output latch stage. Output latch part is
inserted to solve the problem of the interface and the digital circuit, since the
output of the ADC is connected to the data bus, such as a microprocessor. The
architectures such as flash ADC, sigma-delta ADC, and SAR ADC are widely
used. Each of the ADC may have different suitable structure for the sampling rate
and the number of bits.
Figure 2.3 shows typical ADC with various number of bits and sampling rates.
Figure 2.2 Conventional ADC system block diagram

6
As shown in Figure 2.3 sigma-delta (Σ-Δ) ADC is 16-bit resolution, for high
resolution application, but hundreds of KHz sampling rate of the ADC is not
suitable for the SoC. Flash ADC is mainly used in low resolution of less than 10
bits, and the operation speed is fast, but its power consumption is high. Pipeline
ADC with a resolution of less than 16 bits, can have a fast sampling rate of tens
KHz to hundreds MHz, but its power consumption is also high. The SAR ADC
and pipeline ADC have a similar resolution and their sampling rates are relatively
low because of recycling the drawbacks of the inner block with low area.
Therefore, the SAR ADC is suitable to apply a low power and low-area
application for a 12-bit ADC with a proper resolution.

7
Figure 2.3 Typical ADC with various bits and sampling rates
2.2 The main performance indices and formulas of the ADC
The important performances of the ADC contain the differential non-linearity
(DNL) error, integral non-linearity, (INL) error, signal-to-noise ratio distortion
(SNDR), and effective number of bits, (ENOB).
DNL error as shown in Figure 2.4 indicates difference between an ideal step
width and the ideal value. For example, if the input voltage width is 1LSB and if
the measured voltage width is 1.2LSB, it provides DNL of -0.2 LSB.

8
INL error in Figure 2.4 is the maximum deviation between the ideal output of a
ADC and the actual output level (after offset and gain errors have been removed).
Since these errors are closely related to the linearity of the ADC, small errors
provide excellent linearity.
Figure 2.4 DNL and INL characteristics of ADC
Equation (2.1) shows signal to noise ratio, SNR.
= 6. + . (2.1)
where N is the number of bits of resolution of the converter.
SNDR is a measurement of the purity of signal. It is typically used in data

9
converter specifications. Equation (2.2) expresses ENOB. ENOB is a measure of
the dynamic range of an ADC and its associated circuit. ENOB is also used as a
quality measure for other blocks such as sample-and-hold stage.
� =
� − .
.
(2.2)
As can be seen from the equation (2.2), ENOB is used as the most important
performance of the ADC.
2.3 SAR ADC structure and operation principle
Figure 2.5 shows a block diagram of a general SAR ADC. The SAR ADC
consists of sample-and-hold stage, capacitor array network stage, comparator
stage, SAR logic stage, control logic stage and the DAC stage. The SAR ADC is
a type of ADC that converts a continuous analog waveform into a discrete digital
representation via a binary search through all possible quantization levels before

10
finally converging upon a digital output for each conversion. The sample-and-
hold (S/H) is an analog circuit that samples (captures, grabs) the voltage of a
continuously varying analog signal and holds its value at a constant level for a
specified minimum period of time. Successive approximation procedure to
perform the charge redistribution operating in the capacitor array network stage is
compared with reference voltage at the comparator. The output signal of the
comparator is transmitted to the SAR logic using a successive approximation
algorithm to determine a digital code of the analog input.
Figure 2.5 General SAR ADC

11
Figure 2.6 shows code decision procedure of 3-bit SAR ADC. The first step
converts a digital code to a medium value with the most significant bits (MSB)
‘1’, and less significant bits (LSB) ‘0’ to be transmitted to the DAC. The DAC
corresponding to this digital code VDAC using the analog input signal VA is applied
to the comparator. At this time, when the analog input signal VA is greater than the
VDAC, MSB sets to ‘0’. If the analog input signal VA is smaller than the VDAC,MSB
remains ‘1’. When the algorithm this step it provides binary codes that
corresponds to the input voltage. This process is referred to as successive
approximation. The produced code results in a readable data form.

12
Figure 2.7 shows 3 modes of typical 12-bit charge redistribution SAR ADC. In
sample mode of the first step as shown in Figure 2.7(a), since switch SA is ‘on’
status, the top plates of the capacitors are short-circuited are connected to ground,
Figure 2.6 Code decision procedure of 3-bit SAR ADC

13
and the bottom plates of the all capacitors are connected to the analog input VA.
Therefore, the top plates of all capacitors store which are proportional to VA.
Equation (2.3) represents QX store in all capacitors.
� = � �� = �� (2.3)
where Ctot is the sum of total capacitors.
In the hold mode, the switch SA is opened, the switch SB is connected to the
reference voltage Vref and, bottom plates of all capacitors are connected to ground
as shown in Figure 2.7(b). At this point since charges charged in the capacitor
store their values, top plate voltage VX provides -VA.
In the redistribution mode, it performs a process of successive approximation as
shown in Figure 2.7(c). First switch S1 for the most significant bit (MSB) is
connected to the reference voltage Vref, and other switches (S2~S13) the ground. At
this point the capacitor voltage VX is increased from -VA to Vref/2. This status is
expressed by Equations (2.4a), (2.4b) and (2.5). When Qi is the initial charge in
the sample mode, and charge after the switch S1 is connected to the reference
voltage Vref Qf, it is expressed by Equations (2.4a) and (2.4b). Let’s consider Qi =
Qf. Thus we can get Equation (2.5)

14
� = − �� (2.4a)
= �� + �� − �� (2.4b)
�� = −�� +
��
(2.5)
From Equation (2.5), when the value of VA has a value of greater than Vref /2, VX
has a negative value, and so the output of the comparator is a 'Low' status, and
thus the switch S1 remains state connected to Vref. In this case MSB determines
code ‘1’. On the other hand, when the VX has a positive value for VA of less than
Vref/2, the switch S1 is replaced by a connection from reference voltage Vref to a
ground. In such case, the code value of the MSB is determined as ‘0’ status.
Therefore this code status procedure is repeatedly performed from switch, S2 to
switch S12 providing the least significant bit (LSB). In this case the switch S13 still
remains the ground during the redistribution process.

15
(a) Sample mode
(b) Hold mode
(c) Redistribution mode
Figure 2.7 12-bit charge-redistribution SAR ADC

16
3 The proposed SAR ADC circuit and analysis
This chapter describes each stage of the circuit and the role of SAR ADC.
Figures 3.1 illustrates the block diagram of a SAR ADC including a
sample-and-hold, control logic stage, capacitor array network stage, the
comparator stage, DAC stage, output latch and SAR logic stage. The proposed
SAR ADC includes a sample-and-hold stage and the control logic stage as
compared to general SAR ADC.
The circuit design and the role of each stage will be described in the following.
Figure 3.1 The proposed SAR ADC

17
3.1 Sample-and-Hold stage
Sample-and-hold stage is an analog device that samples the voltage of a
continuously varying analog signal and holds its value at a constant level for a
specified minimum period of time, and it sends the sampled signal to the
capacitor array network stage. Sample-and-hold stage holds the sampled signal at
the sampling rate of 1MSps for the sampling of two analog input signals with the
phase difference of 180°. Figure 3.2 illustrates schematic of sample-and-hold
stage. The input signals contain an analog input signal of ‘VINT’ and two control
clock signals of ‘Clks’ and ‘Clksb’. ‘V+’ signal represents the output signal of the
sample-and-hold stage, it has a sampling rate of 1MSps. ‘V+’ signal is transmitted
to the capacitor array network stage. As shown in Figure 3.2, the gate-source
voltage of M7 is fixed to the supply voltage VDD to improve the linearity of the
switch due to the low on-resistance. When the clock control signal Clks is ‘Low’
status and the switch M7 is “off” status, the gates of M8 and M9 are discharge to
ground, and so the VDD is applied to the C1 by the M10 and M2. C1 is a
rechargeable battery role in the “turn-on” state of the switch, M3 and M6
disconnect between C1 and M7 during the charging. When the clock control signal
Clks, is ‘High’ switch M7 is ‘on’ status applied to only the voltage VDD at the gate

18
and the source. Therefore gate voltage V+G of M6 provides Equation (3.1).
��+ = �� + 1
1+ �
� (3.1)
where is the total parasitic capacitance.
Figure 3.2 Schematic of sample-and-hold stage

19
Figure 3.3 shows the layout of the sample-and-hold stage. Using Cadence
Virtuoso program we followed the layout rules of Magnachip/SK Hynix’s 1-Poly
6-Metal 0.18μm CMOS process. The proposed sample-and-hold stage showed
small area of 85μm × 45μm.
Figure 3.3 Sample-and-hold stage layout

20
3.2 Capacitor array network stage
The capacitor array network stage plays role in performing charge
redistribution for the sampling and hold to a digital signal of 12 bits signal from
the sample-and-hold stage.
Figure 3.4 shows the capacitor array network stage, this stage performs charge
redistribution that connects one input of differential inputs applied from the
sample-and-hold stage in parallel with the capacitor array of 12 sets. It is
composed of two capacitor arrays due to the differential structure, and so it has
capacitors of 24 sets. This capacitor array network transfers redistributed signal to
comparator stage which will be mentioned in Section 2.

21
Figure 3.4 Capacitor array network of proposed SAR ADC
Figure 3.5 shows a comparison of the structure proposed in this research
and the typical structure for a SAR ADC capacitor array network stage. General
the SAR ADC capacitor array network of N-bit configures to two arrays with
each array per (N + 1) of capacitors configured to connect each network stage in

22
parallel. In other words, to provide capacitor array with 12-bit resolution, it
contains 26 capacitors. The general case as shown in Figure 3.5(a) connects a
common-mode voltage ‘VCM’ on the top plate of the capacitor in charge
redistribution and signal applied from the sample-and-hold stage is connected to
the bottom plate of the capacitor array. On the other hand, the proposed capacitor
array network as shown in Figure 3.5(b) writhes with bootstrap switches of
sample-and-hold stage in Figure 3.2.

23
(a) General structure
(b) Proposed structure
Figure 3.5 Comparison of SAR ADC capacitor array network stage

24
Equation (3.2) describes average switching energy consumption of a
general capacitor array network, and Equation (3.3) shows average switching
energy consumption of the proposed structure.
�� = ∑ + − �
( �
− ) ��
�= (3.2)
�� = ∑ − −�
��
−
�= (3.3)
Let’s consider 12-bit SAR ADC. The general structure has the average
switching energy consumption of 1023.5 �� , expressed in Equation (3.2). The
proposed ADC has average switching energy consumption of 457.3 �� by
Equation (3.3). Therefore, the proposed ADC has power consumption saving
effect of about 55%. Figure 3.6 shows layout of the capacitor array network stage.
Figure 3.6(a) shows the general structure of the capacitor array network stage
with the length of about 1113.40μm, but the proposed structure provides the
length of 615μm as shown in Figure 3.6(b). Therefore, the proposed structure has
an area reduction of about 45%.

25
(a) the general structure
(b) the proposed structure
Figure 3.6 Layout of capacitor array network stage

26
3.3 Comparator stage
The comparator stage requires pre-amplifier stage for high resolution of 12
bits to decrease latch offset and increase accuracy.
The comparator is a device that compares two voltage or currents and
outputs a digital signal indicating which is larger. Figure 3.7 shows comparator
stage with the latch and a buffer stage send compared result to the input of the
SAR control logic stage and the DAC control logic stage. The output of the
comparator stage holds successively information of 12 sets signal corresponding
to the 12 bits from the MSB to LSB. Figure 3.7 is to propose a comparator stage
it shows the pre-amplifier stage with the latch, and a buffer stage. Figure 3.7(a)
shows circuit schematic of pre-amplifier with M1~M8 and Figure 3.7(b) shows the
latch (ML1 ~ ML9) and the buffer stage (MB1 ~ MB8). The capacitor array network
stage is applied to the pre-amplifier stage of the fully differential architecture
through the T1 and T2 in Figure 3.7(a). Pre-amplifier amplifies the differential
input voltage by a gain. T1 and T2 are applied to a bias voltage through the
NMOS connected to the gate. TP and TN are amplified in the pre-amplifier, and
output port is transferred to the latch stage. The differential output signal
amplified by the pre-amplifier stage is passed through the latch and a buffer stage

27
to maximize the amplitude as shown in Figure 3.7(b). When the latch enters into
equilibrium state enters (Reset), LN and LP wait the input signal for pre-charged
VDD.
ML9 of the latch turns on ‘High’ status before clock ‘Clks’ of sample-and-
hold stage is ‘Low’ status. At this time since ML1 and ML2 turn off, the latch
detects the difference between the input signals of the gates of ML3 and ML4. This
input difference is applied to the logic level on the LP and LN terminals through a
feedback loop M5 ~ M8. These logic level signals are applied to comparator stage
using VOUTT and VOUTC through the buffer consisting of MB1 and MB9. Since the
buffer is connected in series with a latch, it provides a voltage level of comparator
from the power supply voltage level to the ground level.

28
(a) Circuit schematic of preamp (b) Latch and buffer stage
Figure 3.7 Comparator stage
3.4 SAR control logic stage
SAR control logic stage receives from the comparison information signal from
comparator stage, and it generates sequential control signals of 12 numbers using 12-bit
digital signal. Sequential control signals created by the SAR control logic stage are
transferred to the DAC control logic stage in the form of a clock signal. Figure 3.8 shows
proposed SAR control logic stage. Output signals VOUTT and VOUTC of the comparator are

29
applied to the input of the SAR control logic stage. The clock ‘Clks’ is realized by ‘High’
reset status of SAR logic in ‘Low’ status (hold status). SAR logic output signal ‘Clk_Out’
is used to the 'LATCH' control clock of the comparator. SAR control logic output stage of
Clk1 ~ Clk12 sample digital output code in association with the output signal of the
comparator, as sequential control clock signal sampling and it is used as a control signal
for carrying out switching process of the capacitor array. SAR control logic stage
generates a control clock signal consisting of several gates and D flip-flop of 12 sets. In
Figure 3.8 SAR control logic stage generates clock signal of 12 sets. Binary code of 12
bits generated using a clock signal of 12 starts to ‘100000000000’. Create when first
comparator result is ‘1(High)’ from SAR control logic stage in conjunction to DAC
control logic stage, it provides ‘010000000000’. On the other hand, if the result of the
comparator is ‘0(Low)’, the output is ‘110000000000’, and so the output repeated
determines the binary code of the final 12 bits.

30
Figure 3.8 SAR control logic stage
3.5 DAC control logic stage
Figure 3.9 shows DAC control logic stage, and this stage is composed of D flip-
flops, the delay buffer, the logic gate and the inverter. DAC control logic stage
compares the information signal VOUTT with control clock signal Clki (i=1~12),
since Vref and GND are connected to the input capacitor bottom plate composed of
a total of four inputs. Output for the switching state at the bottom plate of the
capacitor is Vpi, and B_pi port exports information bit which is sequentially
determined by V+ from capacitor top plate to the DAC stage.

31
Figure 3.9 DAC control logic stage
In the DAC control logic stage delay buffer triggers between Clki and AND
gate. In addition, to control the switching process of the stage capacitor array
network it is designed using an AND gate and an inverter switch buffer.
3.6 DAC stage
The DAC stage under the control of the DAC control logic stage
converts the digital signal into an analog signal, and then it sends signals to
the input of the comparator. This output signal of the DAC is inserted to the
input signal of the comparator to perform the successive approximation
process.

32
Figure 3.10 shows DAC stage with 12 parallel control signal inputs from
the DAC control logic stage. This stage contains one output port to send
digital-to-analog signal through the capacitor array network. The proposed
DAC is connected to the Op-amp for the capacitor array network consisting
of 12 capacitors 10 with 12-bit resolution, as shown in Figure 3.
Figure 3.10 DAC stage
Figure 3.11 shows layout of DAC stage with capacitor array network. This
layout is suitable for low-area applications because of recycling the blocks.
It showed small area of 48μm × 39μm.

33
Figure 3.11 DAC stage layout
3.7 SAR ADC
Figure 3.12 shows total block diagram of SAR ADC, and Figure 3.13
shows layout of the SAR ADC. As shown in Figure 3.12 and Figure 3.13 it
contains S/H stage, capacitor array stage, comparator stage, SAR control
logic stage, DAC stage and DAC control logic stage. The proposed SAR
ADC also showed small effective chip area of 0.54mm².

34
Figure 3.12 Symbol block diagram of SAR ADC

35
Figure 3.13 Layout of SAR ADC

36
4 Results and Analysis
All simulations are performed by the power supply of 1.5V at room
temperature of 25℃, and the ADC has the input bias voltage of 0.8V. It is also
simulated at the input frequency of 80 kHz so that the output signal for the
applications has the frequency of less than 80 kHz.
4.1 SAR ADC simulation results
Figure 4.1 shows simulation results of sample-and-hold stage. Figure 4.1(a)
shows the simulation results for the sampling at the gate output VG+ of M7 of the
sample-and-hold stage in Figure 3.2 as according to analog input voltage (VINT).
Figure 4.1(b) shows the simulation result for the relationship between the Input
signal (VINT) and sampling signal (T1). The results of analog input signal are
sampled at a sampling rate of 1MSps. This output signal is transmitted to the
input of the capacitor array network stage.

37
(a) Input signal (VINT) and M7 gate signal.
(b) Input signal (VINT) and sampling signal (T1).
Figure 4.1 Simulation results of sample-and-hold stage

38
Figure 4.2 shows the simulation result of the pre-amplifier stage of the
comparator. Figure 4.2(a) is the input signal of the pre-amplifier stage. Small
input signals of 5mV are applied to the pre-amplifier stage, and it is designed to
amplify 5 times. As shown in Figure 4.2(b), the pre-amplifier stage showed
output of approximately 25mV.
(a) Pre-amplifier input.
(b) Pre-amplifier output.
Figure 4.2 Input(T1, T2) and output waveform(TN, TP) of pre-amplifier

39
Figure 4.3 shows simulation results of the comparator. As shown in
Figure 4.3(c) and Figure 4.3(e), when the latch clock is ‘Low’, LN and LP are
pre-charged to ‘High’, and when the latch clock is ‘High’, the LN and LP ‘High’
or ‘Low’ are opposite to each other. Figure 4.3(d) and Figure 4.3(f) show the final
output of the latch. When the output is changed as the change of the latch, so it
provides VOUTT and VOUTC in ‘High’ status. These values are transmitted to SAR
control logic stage is transmitted to the DAC control logic stage.
Figure 4.4 shows simulation result for clock timing diagram of the SAR
control logic stage. As we can see in Figure 4.4, the reset signal Clks sequentially
provides control signals of the 12 clock to control the capacitor array network. In
addition, the ends of the control switch to the reference voltage of 12 clocks per
one period are all ‘Low’.

40
(a) Input clock (b) Comparator output
(c) Latch output LN (d) Output OUTC
(e) Latch output LP (f) Output OUTT
Figure 4.3 Simulation result of comparator

41
Figure 4.4 Clock timing diagram of SAR control logic.

42
Figure 4.5 shows the simulation result of the DAC control logic stage. As
shown in Figure 4.5(a) and Figure 4.5(b), D flip-flop is to sample the comparator
output on the rising edge of the clock signal Clki. In this case, as shown in Figure
4.5(b) when comparator output VOUTT is ‘High’ the reference voltage Vref is
switched to the ground. When the comparator output is ‘Low’, it is connected to
the reference voltage. However, the falling edge of Clki is always connected to
the reference voltage as shown in Figure 4.5(c).
(a) D flip-flop signal and the clock signal

43
(b) D flip-flop signal and the comparator output signal
(c) Output signal of DAC control logic stage.
Figure 4.5 Simulation results of DAC control logic

44
Figure 4.6 shows the simulation result of the 12-bit DAC stage. After the
ramp input signal is converted into digital signal of 12 bits as shown in Figure
4.6(a), the DAC stage simulates the process to be re-converted into a ramp signal
as shown in Figure 4.6(b). As can be seen from Figure 4.6, the digital input of 12-
bit through DAC stage is converted into the ramp waveform.

45
(a) 12-bit input signal of DAC stage
(b) Ramp input signal and output signal of DAC stage.
Figure 4.6 (a) and (b) Simulation results of 12-bit DAC stage

46
4.2 SAR ADC implementation and performance evaluation
Figure 4.7 shows the result of Fast Fourier Transform (FFT) for the input
signal of 80 kHz. The proposed ADC showed high signal-to-noise distortion ratio
(SNDR) of 71.18dB, and excellent effective number of bit (ENOB) of 11.53-bit
as compared to current research results.
Figure 4.7 FFT result of SAR ADC

47
Table 4.1 compares the results of proposed SAR ADC as compared to current
research results. The effective number of bits (ENOB) and signal-to-noise
distortion ratio (SNDR) represent excellent characteristics to larger values and,
the power consumption and the chip area represent more excellent properties to
smaller values. As we can see from Table 4.1, the proposed SAR ADC showed
very low power consumption of 1.95mW in a supply voltage of 1.5V and small
chip area of only 0.54mm2
.
Table 4.1 Summary and comparison of SAR ADC performance
In this
work
[9] [10] [11] [12]
Performances SAR SAR SAR SAR SAR
Technology(μm) 0.18 0.6 0.18 0.18 0.18
Conversion Speed(Sps) 1M 1M 1M 1M 1M
ENOB(bit) 11.53 11.3 10.5 11.34 10.8
SNDR(dB) 71.18 69.79 64.97 70.03 66.78
Power Consumption(mW) 1.95 15 2 3.24 1.5
Supply Voltage(V) 1.5 3.0-5.5 1.8 1.8 1.8
Effective chip area(mm2
) 0.54 1.5 1 0.56 0.64
Resolution(bit) 12 12 12 12 12

48
5 Conclusions
In this thesis, a 12-bit successive approximation register type 1MSps analog-
to-digital converter is proposed. It contained sample-and-hold stage, capacitor
array, SAR control logic stage, DAC stage, and DAC control logic stage. This
SAR ADC is designed to have performance of 12-bit resolution and.
The SAR ADC was verified by simulating the performance using the
Advanced Design System (ADS) tool, and the Magnachip/SK Hynix’s 1-Poly 6-
Metal 0.18μm CMOS process was used for Cadence's Virtuoso layout tools.
The proposed circuit in this thesis showed high signal-to-noise distortion ratio
(SNDR) of 71.18dB, and excellent effective number of bit (ENOB) 11.53-bit as
compared to conventional research results. The designed circuit also showed very
low power consumption of 1.95mW, in a supply voltage of 1.5V and small chip
area of 0.54mm².

49
References
[1] M. U. Seong, Murod Kurbanov and J. Y. Ryu, “A 12bit 1MSps SAR ADC for
System-on-Chip”, Proceedings of Conference on Information and
Communication Engineering, June 2016.
[2] A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline
Analog-to-Digital Converter", IEEE Journal of Solid-State Circuits, Vol. 34,
No. 5, pp. 599-606, May 1999.
[3] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, "A 10-bit 50-MS/s SAR
ADC With a Monotonic Capacitor Switching Procedure", IEEE Journal of
Solid-State Circuits, Vol. 45, No 4, pp. 731-740, April 2010.
[4] J. McCreary and P. R. Gray, "All-MOS Charge Redistribution Analog-to-
Digital Conversion Techniques Part I", IEEE Journal of Solid-State Circuits,
Vol. 10, No. 6, pp. 371-379, Dec. 1975.
[5] R. E. Suarez, P. R. Gray, and D. A. Hodges, "All-MOS Charge Redistribution
Analog-to-Digital Conversion Techniques Part II", IEEE Journal of Solid-
State Circuits, Vol. 10, No. 6, pp. 379-385, Dec. 1975.
[6] S. K. Choi, S. W. Kim, M. U. Seong, and J. Y. Ryu, "A 12bit 1MSps CMOS
SAR ADC Design", Proceedings of Conference on Information and

50
Communication Engineering, Vol. 17, No. 1, pp. 352-353, May 2013.
[7] M. U. Seong, S. K. Choi, S. W. Kim, S. G. Kim, J. S. Lee, S. M. Oh, M. S.
Seo, and J. Y. Ryu, "Design of a 12-bit 1MSps SAR ADC using 0.18㎛
CMOS Process", Proceedings of Conference on Information and
Communication Engineering, Vol. 17, No. 2, pp. 365-367, Oct. 2013.
[8] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, John
Wiley & Sons, 1983.
[9] B. Razavi, Pinciples of Data Conversion System Design, IEEE Press, 1995.
[10] S. -H. Cho, T. -J. An, Y. -M. Kim, J. -H. Roh, M. -K. Lee, S. -P. Nah, and S.
-H. Lee, "12bit 100MS/s 1.1V 0.43mm² ADC optimized in a 45nm CMOS
technology", ITC-CSCC, vol. 28, pp. 180-183, June 2013.
[11] G. Promitzer, “12 bit low power fully differential switched capacitor non-
calibrating successive approximation ADC with 1MS/s”, Proceedings of the
26th
European Solid-State Circuits Conference, vol. 26, No. 1, pp. 176-179,
Sep. 2000.

51
[12] C. Shan, T. Xingyuan, C. Naiqiong, and Y. Yintang, “ A 12 bit Non-
calibrating SAR A/D Converter based on 90nm CMOS Process”,
Proceeding of International Conference on Machine Vision and Human-
machine Interface, pp. 748-787, Sep. 2000.

52
[Appendix]
Publication Paper List
(1) Journal
Paper Title Date Journal Title
24GHz CMOS Power Amplifier for
Automotive Radar
January 2017
International Journal of
Control and Automation
(SCOPUS)
Design of Low-Power 24GHz Voltage-
Controlled Oscillator
December 2016 AETA (SCOPUS)
A 12-bit 1MSps SAR ADC with High
ENOB
August 2016
International Journal of
Applied Engineering
Research (SCOPUS)
(2) Conference
Paper Title Date Conference Title
Design of Low-Power 24GHz
Voltage-Controlled Oscillator
December 2016
The International Conference
on Advanced Engineering-
Theory and Applications 2016
Design of Digital FIR Filters for Noise
Cancellation
October 2016
Proceedings of Conference on
Information and
Communication Engineering
Low-Power 24-GHz CMOS Low
Noise Amplifier
October 2016
Information and
A low power 12-bit 1MSps SAR ADC
with capacitor array network
October 2016
2016 년도
한국멀티미디어학회
추계학술발표대회 논문집
제 19 권 2 호
An Ultra-Low Power 24GHz CMOS
LC VCO
October 2016
2016 년도
한국멀티미디어학회
추계학술발표대회 논문집

53
제 19 권 2 호
System-on-Chip
June 2016
대한전자공학회 전자·통신
학술대회
Automotive Radar Frontend Circuit in
0.13μm CMOS
June 2016
학술대회
Design of a Low Area 12-bit SAR
ADC using MOS Capacitor
June 2016
학술대회
Development automobile engine
measurement device using a laser and
a CCD linear sensor.
June 2016
학술대회
FPGA implementation of
programmable FIR/IIR filter
June 2016
International Conference on
Future Information and
5.25-GHz BiCMOS Low Noise
Amplifier
May 2016
Information and
Design of Bias Circuit for GHz
BiCMOS Low Noise Amplifier
May 2016
Information and
High Gain 24-GHz CMOS Low Noise
Amplifier
May 2016
Information and
Development of DPSD(Digital
Position Scanning Device) Using
Laser and Linear CCD Sensor
December 2015
한국통신학회 학술심포지움
논문집
The Low Area 12-bit SAR ADC using
CMOS Process
December 2015
한국통신학회 학술심포지움
논문집
Development of Low-Power CMOS
Programmable Gain Amplifier
October 2015
ISAE 2015
International Symposium on
Advanced Engineering
The High-Linearity CMOS LNA using
Modified DS Linearization Technique
October 2015
ISAE 2015
Fabrication of a Low-Cost Wafer-
Level Packaging for RF Devices
October 2015
ISAE 2015
Design of power Amplifier for 24- October 2015 ISAE 2015

54
Applications International Symposium on
Design of Low-Power Voltage-
Controlled Oscillator for 24-GHz
Applications
October 2015
Information and
Implementation of Vehicle Collision
Avoidance Algorithm for Automotive
Radar Sensor
October 2015
Information and
The Low Area 12-bit SAR ADC October 2015
Information and
77-GHz 저전력 전압제어발진기
설계
October 2015
2015 한국정보기술학회 ICT
논문 경진 대회 논문집
Design of 24-GHz/77-GHz Dual Band
CMOS Low Noise Amplifier
May 2015
Information and
Design of 77-GHz CMOS Power
Amplifier
May 2015
Information and

55
Acknowledgments
First of all, I would like to express my gratitude to all those who helped me during
the writing of my thesis. I gratefully acknowledge the help of my supervisor, Prof. Jee-
Youl Ryu, for his valuable guidance and everlasting support during my MS. He spent
enormous amount of time with me to discuss valuable items such as my research, my
classes and my life in general. I have learned so much from him and I feel that I am well
prepared to face the real world challenges. He has also been very inspirational on my
research work by telling me how to do research with motivation. My personal experience
with him will never be forgotten. I would like to thank many friends and to all SoC lab
members, whom too many to mention here for giving me a chance to work, paly and rest
while I was doing my MS. I also wish to thank Prof. X. K. Aripov at Tashkent University
of Information Technologies.
Finally, I wish to thank my parents in Samarkand Uzbekistan for allowing me to
come to Busan South Korea. They provided me with support and encouragement.
Murod Kurbanov
February, 2017, Pukyong National University, Busan

56
Keywords
ADC-Analog to Digital Conversion
DAC-Digital to Analog Conversion
SAR-Successive Approximation Register
SoC-System on Chip
CMOS- Complementary Metal Oxide Semiconductor
ENOB-Effective Number of Bits
SNDR-Signal to Noise Distortion Re Ratio
SNR-Signal to Noise Ratio
S/H-Sample and Hold
INL-Integral non-Linearity
DNL-Differential non-Linearity
LSB- Less Significant Bits
MSB-Most Significant Bits
MSps-Mega Sampling per second
(Σ-Δ)-Sigma-Delta
FFT-Fast Fourier Transform

12-Bit 1MSps SAR ADC For System-On-Chip

More Related Content

Similar to 12-Bit 1MSps SAR ADC For System-On-Chip (20)

More from Sheila Sinclair (20)

Recently uploaded (20)

12-Bit 1MSps SAR ADC For System-On-Chip