![` Malachy Devlin Robin Bruce, Stephen Marshall Submission 186 m.devlin@nallatech.com, robin.bruce@sli-institute.ac.uk & stephen.marshall@eee.strath.ac.uk High-Level Implementation of VSIPL on FPGA-based Reconfigurable Computers VSIPL: The Vector, Signal and Image API This poster examines architectures for FPGA-based high level language implementations of the Vector, Signal and Image Processing Library (VSIPL). VSIPL has been defined by a consortium of industry, government and academic representatives. It has become a de facto standard in the embedded signal processing world. VSIPL is a C-based application programming interface (API) and was initially targeted at a single microprocessor. The scope of the full API is extensive, offering a vast array of signal processing and linear algebra functionality for many data types. VSIPL implementations are generally a reduced subset or profile of the full API. The purpose of VSIPL is to provide developers with a standard, portable application development environment. Successful VSIPL implementations can have radically different underlying hardware and memory management systems and still allow applications to be ported between them with minimal modification of the code. Implementing the VSIPL API on FPGA fabric FPGA Floating Point Comes of Age Architectural Possibilities Developing an FPGA-based implementation of VSIPL offers as many exciting possibilities as it presents challenges. The VSIPL specification has in no way been developed with FPGAs in mind. This research is being carried out in the expectation that it shall one day comply to a set of rules for VISPL that consider the advantages and limitations of FPGAs. Over the course of this research we expect to find solutions to several key difficulties that impede the development of FPGA VSIPL, paying particular attention to: 1.) Finite size of hardware-implemented algorithms vs. conceptually boundless vectors. 2.) Runtime reconfiguration options offered by microprocessor VSIPL. 3.) Vast scope of VSIPL API vs. limited fabric resource. 4.) Communication bottleneck arising from software-hardware partition. 5.) Difficulty in leveraging parallelism inherent in expressions presented as discrete operations. As well as the technical challenges this research poses there is a great logistical challenge. In the absence of a large research team, the sheer quantity of functions requiring hardware implementation seems overwhelming. In order to succeed this project has as a secondary research goal the development of an environment that allows for rapid development and deployment of signal processing algorithms in FPGA fabric. Implementation of a Single-Precision Floating-Point Boundless Convolver VSIPL is fundamentally based around floating-point arithmetic and offers no fixed-point support. Both single-precision and double-precision floating-point arithmetic is available in the full API. Any viable VSIPL implementation must guarantee the user the dynamic range and precision that floating-point offers for repeatability of results. FPGAs have in recent times rivalled microprocessors when used to implement bit-level and integer-based algorithms. Many techniques have been developed that enable hardware developers to attain the performance levels of floating-point arithmetic. Through careful fixed-point design the same results can be obtained using a fraction of the hardware that would be necessary for a floating-point implementation. Floating-point implementations are seen as bloated; a waste of valuable resource. Nevertheless, as the reconfigurable-computing user base grows, the same pressures that led to floating-point arithmetic logic units (ALUs) becoming standard in the microprocessor world are now being felt in the field of programmable logic design. Floating-point performance in FPGAs now rivals that of microprocessors; certainly in the case of single-precision and with double-precision gaining ground. Up to 25 GigaFLOPS/s are possible with single precision for the latest generation of FPGAs. Approximately a quarter of this figure is possible for double precision. Unlike CPUs, FPGAs are limited by peak FLOPS for many key applications and not memory bandwidth. Fully floating-point implemented design solutions offer invaluable benefits to an enlarged reconfigurable-computing market. Reduced design time and far simplified verification are just two of the benefits that go a long way to addressing the issues of ever-decreasing design time and an increasing FPGA design skills shortage. All implementations presented here are single-precision floating-point. Fig.4. System Diagram of Convolver System Results & Conclusions The floating point convolver was clocked at 120MHz and to perform a 16k by 32k convolution took 16.96Mcycles , or 0.14 seconds to complete. Due to the compute intensity of this operation, host-fabric data transfer time is negligible. There is a 10x speed increase on the 1.4 seconds the same operation took in software alone. FPGA-based VSIPL would offer significant performance benefits over processor-based implementations. It has been shown how the boundless nature of VSIPL vectors can be overcome through a combination of fabric and software-managed reuse of pipelined fabric-implemented kernels. The resource demands of floating-point implemented algorithms have been highlighted and the need for resource re-use or even run-time fabric reconfiguration is stressed. The foundations have been laid for the development environment that will allow for all VSIPL functions, as well as custom user algorithms, to be implemented. Architecture Models Hardware Development Platform Figure 2 DIMETalk Network Figure 1 Nallatech ‘BenNUEY’ PCI Motherboard Figure 3 BenNUEY System Diagram The inner convolution kernel convolves the input vector A with 32 coefficients taken from the input vector B. The results are added to the relevant entry of the temporary result blockRAM (initialised to zero). This kernel is re-used as many times as is necessary to convolve all of the 32-word chunks of input vector B with the entire vector A. The fabric convolver carries out the largest convolution possible with the memory resources available on the device, a 16k by 32k convolution producing a 48k word result. This fabric convolver can be re-used by a C program on the host as many times as is necessary to realise the convolver or FIR operation of the desired dimensions. This is all wrapped up in a single C-function that is indistinguishable to the user from a fully software-implemented function FPGA Fabric Convolver implemented in C The inner pipelined kernel and its reuse at the fabric level consist of a C-to-VHDL generated component created using a floating point C compiler tool from Nallatech. The “C” code used to describe the necessary algorithms is a true subset of C and any code that compiles in the C-to-VHDL compiler can be compiled using any ANSI-compatible C compiler without modification. The design was implemented on the user FPGA of a BenNUEY motherboard (figures 1 and 3). Host-fabric communication was handled by a packet-based DIMETalk network (figure 2) providing scalability over multi-FPGAs. SRAM storage took place using two banks of ZBT RAM. The FPGA on which the design was implemented was a Xillinx Virtex-II XC2V6000. The design used: 144 16k BlockRAMS (100%), 25679 Slices (75%) and 128 18x18 Multipliers (88%). The pipelined inner kernel of the convolver, as seen in figure 7, is implemented using 32 floating-point multipliers and 31 floating-point adders. These are Nallatech single-precision cores which are assembled from a C description of the algorithm using a C-to-VHDL converter. The C function call arguments and return values are managed over the DIMEtalk FPGA communications infrastructure. To provide an example of how the VSIPL constraints that allow for unlimited input and output vector lengths can be met, a boundless convolver is presented. Suitable for 1D convolution and FIR filtering this component is implemented using single-precision floating-point arithmetic throughout. Figure 7 Boundless Convolver System In implementing VSIPL FPGAs there are several potential architectures that are being explored. The three primary architectures are as follows, in increasing order of potential performance and design complexity: 1.) Function ‘stubs’: Each function selected for implementation on the fabric transfers data from the host to the FPGA before each operation of the function and brings it back again to the host before the next operation. This model (figure 4) is the simplest to implement, but excessive data transfer greatly hinders performance. The work presented here is based on this first model. 2.) Full Application Algorithm Implementation: Rather than utilising the FPGA to process functions separately and independently, we can utilise high level compilers to implement the application’s complete algorithm in C making calls to FPGA VSIPL C Functions. This can significantly reduce the overhead of data communications, FPGA configuration and cross function optimizations. 3.) FPGA Master Implementation: Traditional systems are considered to be processor centric, however FPGAs now have enough capability to create FPGA centric systems. In this approach the complete application can reside on the FPGA, including program initialisation and VSIPL application algorithm. Depending on the rest of the system architecture, the FPGA VSIPL-based application can use the host computer as a I/O engine, or alternatively the FPGA can have direct I/O attachments thus bypassing operating system latencies. Initialisation Function 1 Stub Function 2 Stub Function 3 Stub Termination Function 1 Function 2 Function 3 Host Fabric Figure 4 Functional ‘Stubs’ Implementation Host Fabric Figure 5 Full Application Algorithm Implementation Figure 6 FPGA Master Implementation Initialisation Data Transfer Data Transfer Termination Function 1 Function 2 Function 3 Data Data Host Fabric Pipelined Convolution Kernel Fabric-Level Reuse of Pipelined Kernel C_storage[32] Registers Temp_res[48k] BlockRAM InputA[32k] SRAM Output[48k] SRAM InputB[16k] BlockRAM DIMETalk Network Xilinx Virtex-II XC2V6000 FPGA on ‘BenNUEY’ Motherboard Host PC Software Reuse of Fabric Convolver PCI Host-Fabric Communcation Data IO Data IO Initialisation Function 1 Function 2 Function 3 Termination](https://image.slidesharecdn.com/186devlinp-poster2-110127110746-phpapp02/85/186-devlin-p-poster-2-1-320.jpg)
186 devlin p-poster(2)
- 1. ` Malachy Devlin Robin Bruce, Stephen Marshall Submission 186 m.devlin@nallatech.com, robin.bruce@sli-institute.ac.uk & stephen.marshall@eee.strath.ac.uk High-Level Implementation of VSIPL on FPGA-based Reconfigurable Computers VSIPL: The Vector, Signal and Image API This poster examines architectures for FPGA-based high level language implementations of the Vector, Signal and Image Processing Library (VSIPL). VSIPL has been defined by a consortium of industry, government and academic representatives. It has become a de facto standard in the embedded signal processing world. VSIPL is a C-based application programming interface (API) and was initially targeted at a single microprocessor. The scope of the full API is extensive, offering a vast array of signal processing and linear algebra functionality for many data types. VSIPL implementations are generally a reduced subset or profile of the full API. The purpose of VSIPL is to provide developers with a standard, portable application development environment. Successful VSIPL implementations can have radically different underlying hardware and memory management systems and still allow applications to be ported between them with minimal modification of the code. Implementing the VSIPL API on FPGA fabric FPGA Floating Point Comes of Age Architectural Possibilities Developing an FPGA-based implementation of VSIPL offers as many exciting possibilities as it presents challenges. The VSIPL specification has in no way been developed with FPGAs in mind. This research is being carried out in the expectation that it shall one day comply to a set of rules for VISPL that consider the advantages and limitations of FPGAs. Over the course of this research we expect to find solutions to several key difficulties that impede the development of FPGA VSIPL, paying particular attention to: 1.) Finite size of hardware-implemented algorithms vs. conceptually boundless vectors. 2.) Runtime reconfiguration options offered by microprocessor VSIPL. 3.) Vast scope of VSIPL API vs. limited fabric resource. 4.) Communication bottleneck arising from software-hardware partition. 5.) Difficulty in leveraging parallelism inherent in expressions presented as discrete operations. As well as the technical challenges this research poses there is a great logistical challenge. In the absence of a large research team, the sheer quantity of functions requiring hardware implementation seems overwhelming. In order to succeed this project has as a secondary research goal the development of an environment that allows for rapid development and deployment of signal processing algorithms in FPGA fabric. Implementation of a Single-Precision Floating-Point Boundless Convolver VSIPL is fundamentally based around floating-point arithmetic and offers no fixed-point support. Both single-precision and double-precision floating-point arithmetic is available in the full API. Any viable VSIPL implementation must guarantee the user the dynamic range and precision that floating-point offers for repeatability of results. FPGAs have in recent times rivalled microprocessors when used to implement bit-level and integer-based algorithms. Many techniques have been developed that enable hardware developers to attain the performance levels of floating-point arithmetic. Through careful fixed-point design the same results can be obtained using a fraction of the hardware that would be necessary for a floating-point implementation. Floating-point implementations are seen as bloated; a waste of valuable resource. Nevertheless, as the reconfigurable-computing user base grows, the same pressures that led to floating-point arithmetic logic units (ALUs) becoming standard in the microprocessor world are now being felt in the field of programmable logic design. Floating-point performance in FPGAs now rivals that of microprocessors; certainly in the case of single-precision and with double-precision gaining ground. Up to 25 GigaFLOPS/s are possible with single precision for the latest generation of FPGAs. Approximately a quarter of this figure is possible for double precision. Unlike CPUs, FPGAs are limited by peak FLOPS for many key applications and not memory bandwidth. Fully floating-point implemented design solutions offer invaluable benefits to an enlarged reconfigurable-computing market. Reduced design time and far simplified verification are just two of the benefits that go a long way to addressing the issues of ever-decreasing design time and an increasing FPGA design skills shortage. All implementations presented here are single-precision floating-point. Fig.4. System Diagram of Convolver System Results & Conclusions The floating point convolver was clocked at 120MHz and to perform a 16k by 32k convolution took 16.96Mcycles , or 0.14 seconds to complete. Due to the compute intensity of this operation, host-fabric data transfer time is negligible. There is a 10x speed increase on the 1.4 seconds the same operation took in software alone. FPGA-based VSIPL would offer significant performance benefits over processor-based implementations. It has been shown how the boundless nature of VSIPL vectors can be overcome through a combination of fabric and software-managed reuse of pipelined fabric-implemented kernels. The resource demands of floating-point implemented algorithms have been highlighted and the need for resource re-use or even run-time fabric reconfiguration is stressed. The foundations have been laid for the development environment that will allow for all VSIPL functions, as well as custom user algorithms, to be implemented. Architecture Models Hardware Development Platform Figure 2 DIMETalk Network Figure 1 Nallatech ‘BenNUEY’ PCI Motherboard Figure 3 BenNUEY System Diagram The inner convolution kernel convolves the input vector A with 32 coefficients taken from the input vector B. The results are added to the relevant entry of the temporary result blockRAM (initialised to zero). This kernel is re-used as many times as is necessary to convolve all of the 32-word chunks of input vector B with the entire vector A. The fabric convolver carries out the largest convolution possible with the memory resources available on the device, a 16k by 32k convolution producing a 48k word result. This fabric convolver can be re-used by a C program on the host as many times as is necessary to realise the convolver or FIR operation of the desired dimensions. This is all wrapped up in a single C-function that is indistinguishable to the user from a fully software-implemented function FPGA Fabric Convolver implemented in C The inner pipelined kernel and its reuse at the fabric level consist of a C-to-VHDL generated component created using a floating point C compiler tool from Nallatech. The “C” code used to describe the necessary algorithms is a true subset of C and any code that compiles in the C-to-VHDL compiler can be compiled using any ANSI-compatible C compiler without modification. The design was implemented on the user FPGA of a BenNUEY motherboard (figures 1 and 3). Host-fabric communication was handled by a packet-based DIMETalk network (figure 2) providing scalability over multi-FPGAs. SRAM storage took place using two banks of ZBT RAM. The FPGA on which the design was implemented was a Xillinx Virtex-II XC2V6000. The design used: 144 16k BlockRAMS (100%), 25679 Slices (75%) and 128 18x18 Multipliers (88%). The pipelined inner kernel of the convolver, as seen in figure 7, is implemented using 32 floating-point multipliers and 31 floating-point adders. These are Nallatech single-precision cores which are assembled from a C description of the algorithm using a C-to-VHDL converter. The C function call arguments and return values are managed over the DIMEtalk FPGA communications infrastructure. To provide an example of how the VSIPL constraints that allow for unlimited input and output vector lengths can be met, a boundless convolver is presented. Suitable for 1D convolution and FIR filtering this component is implemented using single-precision floating-point arithmetic throughout. Figure 7 Boundless Convolver System In implementing VSIPL FPGAs there are several potential architectures that are being explored. The three primary architectures are as follows, in increasing order of potential performance and design complexity: 1.) Function ‘stubs’: Each function selected for implementation on the fabric transfers data from the host to the FPGA before each operation of the function and brings it back again to the host before the next operation. This model (figure 4) is the simplest to implement, but excessive data transfer greatly hinders performance. The work presented here is based on this first model. 2.) Full Application Algorithm Implementation: Rather than utilising the FPGA to process functions separately and independently, we can utilise high level compilers to implement the application’s complete algorithm in C making calls to FPGA VSIPL C Functions. This can significantly reduce the overhead of data communications, FPGA configuration and cross function optimizations. 3.) FPGA Master Implementation: Traditional systems are considered to be processor centric, however FPGAs now have enough capability to create FPGA centric systems. In this approach the complete application can reside on the FPGA, including program initialisation and VSIPL application algorithm. Depending on the rest of the system architecture, the FPGA VSIPL-based application can use the host computer as a I/O engine, or alternatively the FPGA can have direct I/O attachments thus bypassing operating system latencies. Initialisation Function 1 Stub Function 2 Stub Function 3 Stub Termination Function 1 Function 2 Function 3 Host Fabric Figure 4 Functional ‘Stubs’ Implementation Host Fabric Figure 5 Full Application Algorithm Implementation Figure 6 FPGA Master Implementation Initialisation Data Transfer Data Transfer Termination Function 1 Function 2 Function 3 Data Data Host Fabric Pipelined Convolution Kernel Fabric-Level Reuse of Pipelined Kernel C_storage[32] Registers Temp_res[48k] BlockRAM InputA[32k] SRAM Output[48k] SRAM InputB[16k] BlockRAM DIMETalk Network Xilinx Virtex-II XC2V6000 FPGA on ‘BenNUEY’ Motherboard Host PC Software Reuse of Fabric Convolver PCI Host-Fabric Communcation Data IO Data IO Initialisation Function 1 Function 2 Function 3 Termination