28 c64a mimemory
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The document describes the features and specifications of the Microchip Technology Inc. 28C64A 64K non-volatile electrically erasable PROM. Key points include: - It is a CMOS 64K EEPROM that can be accessed like static RAM without external components. - It has a fast read access time of 150ns, low power dissipation of 30mA active and 100uA standby, and high endurance of minimum 100,000 erase/write cycles. - It has an internal control timer that automatically clears and writes latched data following a write cycle initiation, with the user able to monitor completion via the ready/busy pin or data polling.
28 c64a mimemory
- 1. 2004 Microchip Technology Inc. DS11109K-page 1 FEATURES • Fast Read Access Time—150 ns • CMOS Technology for Low Power Dissipation - 30 mA Active - 100 µA Standby • Fast Byte Write Time—200 µs or 1 ms • Data Retention >200 years • High Endurance - Minimum 100,000 Erase/Write Cycles • Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches • Data Polling • Ready/Busy • Chip Clear Operation • Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit • Electronic Signature for Device Identification • 5-Volt-Only Operation • Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin PLCC Package - 28-pin SOIC Package • Available for Extended Temperature Ranges: - Commercial: 0°C to +70°C - Industrial: -40°C to +85°C DESCRIPTION The Microchip Technology Inc. 28C64A is a CMOS 64K non- volatile electrically Erasable PROM. The 28C64A is accessed like a static RAM for the read or write cycles with- out the need of external components. During a “byte write”, the address and data are latched internally, freeing the micro- processor address and data bus for other operations. Fol- lowing the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wired- or systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is com- plete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reli- ability are required. A complete family of packages is offered to provide the utmost flexibility in applications. PACKAGE TYPES BLOCK DIAGRAM • Pin 1 indicator on PLCC on top of package • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RDY/BSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 V Vcc WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3SS A6 A5 A4 A3 A2 A1 A0 NC I/O0 A8 A9 A11 NC OE A10 CE I/O7 I/O6 A7 A12 RDY/BSY NU Vcc WE NC I/O1 I/O2 Vss NU I/O3 I/O4 I/O5 14 15 16 17 18 19 20 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 DIP/SOIC PLCC I/O0 I/O7 Input/Output Buffers Chip Enable/ Output Enable Control Logic CE OE Data Protection Circuitry A12 Y Gating 16K bit Cell Matrix X Decoder Y Decoder A0 Data Poll Auto Erase/Write Timing VCC VSS WE L a t c h e s Program Voltage Generation Rdy/ Busy 28C64A 64K (8K x 8) CMOS EEPROM Obsolete Device
- 2. 28C64A DS11109K-page 2 2004 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS 1.1 MAXIMUM RATINGS* VCC and input voltages w.r.t. VSS....... -0.6V to + 6.25V Voltage on OE w.r.t. VSS......................-0.6V to +13.5V Voltage on A9 w.r.t. VSS ......................-0.6V to +13.5V Output Voltage w.r.t. VSS.................-0.6V to VCC+0.6V Storage temperature ..........................-65°C to +125°C Ambient temp. with power applied .......-50°C to +95°C *Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating con- ditions for extended periods may affect device reliability. TABLE 1-1: PIN FUNCTION TABLE Name Function A0 - A12 Address Inputs CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs RDY/Busy Ready/Busy VCC +5V Power Supply VSS Ground NC No Connect; No Internal Connection NU Not Used; No External Connection is Allowed TABLE 1-2: READ/WRITE OPERATION DC CHARACTERISTIC VCC = +5V ±10% Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Parameter Status Symbol Min Max Units Conditions Input Voltages Logic ‘1’ Logic ‘0’ VIH VIL 2.0 -0.1 Vcc+1 0.8 V V Input Leakage — ILI -10 10 µA VIN = -0.1V to Vcc +1 Input Capacitance — CIN — 10 pF VIN = 0V; Tamb = 25°C; f = 1 MHz (Note 2) Output Voltages Logic ‘1’ Logic ‘0’ VOH VOL 2.4 0.45 V V IOH = -400 µA IOL = 2.1 mA Output Leakage — ILO -10 10 µA VOUT = -0.1V to Vcc +0.1V Output Capacitance — COUT — 12 pF VIN = 0V; Tamb = 25°C; f = 1 MHz (Note 2) Power Supply Current, Active TTL input ICC — 30 mA f = 5 MHz (Note 1) VCC = 5.5V Power Supply Current, Standby TTL input TTL input CMOS input ICC(S)TTL ICC(S)TTL ICC(S)CMOS — 2 3 100 mA mA µA CE = VIH (0°C to +70°C) CE = VIH (-40°C to +85°C) CE = VCC-0.3 to Vcc +1 OE = WE = Vcc All other inputs equal VCC or VSS Note 1: AC power supply current above 5MHz: 2mA/MHz. 2: Not 100% tested.
- 3. 2004 Microchip Technology Inc. DS11109K-page 3 28C64A TABLE 1-3: READ OPERATION AC CHARACTERISTICS FIGURE 1-1: READ WAVEFORMS AC Testing Waveform: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V Output Load: 1 TTL Load + 100 pF Input Rise and Fall Times: 20 ns Ambient Temperature: Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Parameter Symbol 28C64A-15 28C64A-20 28C64A-25 Units Conditions Min Max Min Max Min Max Address to Output Delay tACC — 150 — 200 — 250 ns OE = CE = VIL CE to Output Delay tCE — 150 — 200 — 250 ns OE = VIL OE to Output Delay tOE — 70 — 80 — 100 ns CE = VIL CE or OE High to Output Float tOFF 0 50 0 55 0 70 ns (Note 1) Output Hold from Address, CE or OE, whichever occurs first. tOH 0 — 0 — 0 — ns (Note 1) Endurance — 1M — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block Mode (Note 2) Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli- cation, please consult the Total Endurance Model which can be obtained on our BBS or website. Address CE VIH VIL VIH VIL VIH VIL OE Data WE VOH VOL VIH VIL Address Valid High Z Valid Output tACC (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE (3) This parameter is sampled and is not 100% tested High Z tOH tOFF(1,3) Notes: tOE(2) tCE(2)
- 4. 28C64A DS11109K-page 4 2004 Microchip Technology Inc. TABLE 1-4: BYTE WRITE AC CHARACTERISTICS FIGURE 1-2: PROGRAMMING WAVEFORMS AC Testing Waveform: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V Output Load: 1 TTL Load + 100 pF Input Rise/Fall Times: 20 ns Ambient Temperature: Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Parameter Symbol Min Max Units Remarks Address Set-Up Time tAS 10 — ns Address Hold Time tAH 50 — ns Data Set-Up Time tDS 50 — ns Data Hold Time tDH 10 — ns Write Pulse Width tWPL 100 — ns Note 1 Write Pulse High Time tWPH 50 — ns OE Hold Time tOEH 10 — ns OE Set-Up Time tOES 10 — ns Data Valid Time tDV — 1000 ns Note 2 Time to Device Busy tDB 2 50 ns Write Cycle Time (28C64A) tWC — 1 ms 0.5 ms typical Write Cycle Time (28C64AF) tWC — 200 µs 100 µs typical Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the pos- itive edge WE, whichever occurs first. 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after the positive edge of WE or CE, whichever occurs first. tAS tAH tWPL tDS tDH tOES tOEH tWC Address CE, WE Data In OE VIH VIL VIH VIL VIH VIL VIH VIL Rdy/Busy VOH VOL tDB tDV Busy Ready
- 5. 2004 Microchip Technology Inc. DS11109K-page 5 28C64A FIGURE 1-3: DATA POLLING WAVEFORMS FIGURE 1-4: CHIP CLEAR WAVEFORMS TABLE 1-5: SUPPLEMENTARY CONTROL Mode CE OE WE A9 VCC I/OI Chip Clear VIL VIH VIL X VCC Extra Row Read VIL VIL VIH A9 = VH VCC Data Out Extra Row Write * VIH * A9 = VH VCC Data In Note: VH = 12.0V±0.5V. *Pulsed per programming waveforms. Address Valid Last Written Address Valid t ACC tCE tWPL t WPH tDV tWC tOE True Data OutData In Valid VIH VIL Data OE WE CE Address I/O7 Out VIH VIL VIH VIL VIH VIL VIH VIL VH VIH CE OE WE tS tH tW tS = = 1µstH = 10ms tW VIH VIL VIH VIL = 12.0V ±0.5VVH
- 6. 28C64A DS11109K-page 6 2004 Microchip Technology Inc. 2.0 DEVICE OPERATION The Microchip Technology Inc. 28C64A has four basic modes of operation—read, standby, write inhibit, and byte write—as outlined in the following table. 2.1 Read Mode The 28C64A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and is used to gate data to the output pins independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the output tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC-tOE. 2.2 Standby Mode The 28C64A is placed in the standby mode by applying a high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, inde- pendent of the OE input. 2.3 Data Protection In order to ensure data integrity, especially during criti- cal power-up and power-down transitions, the following enhanced data protection circuits are incorporated: First, an internal VCC detect (3.3 volts typical) will inhibit the initiation of non-volatile programming operation when VCC is less than the VCC detect circuit trip. Second, there is a WE filtering circuit that prevents WE pulses of less than 10 ns duration from initiating a write cycle. Third, holding WE or CE high or OE low, inhibits a write cycle during power-on and power-off (VCC). Operation Mode CE OE WE I/O Rdy/Busy (1) Read L L H DOUT H Standby H X X High Z H Write Inhibit H X X High Z H Write Inhibit X L X High Z H Write Inhibit X X H High Z H Byte Write L H L DIN L Byte Clear Automatic Before Each “Write” Note 1: Open drain output. 2: X = Any TTL level. 2.4 Write Mode The 28C64A has a write cycle similar to that of a Static RAM. The write cycle is completely self-timed and ini- tiated by a low going pulse on the WE pin. On the fall- ing edge of WE, the address information is latched. On rising edge, the data and the control pins (CE and OE) are latched. The Ready/Busy pin goes to a logic low level indicating that the 28C64A is in a write cycle which signals the microprocessor host that the system bus is free for other activity. When Ready/Busy goes back to a high, the 28C64A has completed writing and is ready to accept another cycle. 2.5 Data Polling The 28C64A features Data polling to signal the comple- tion of a byte write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of I/O7 (I/O0 to I/O6 are indetermin- able). After completion of the write cycle, true data is available. Data polling allows a simple read/compare operation to determine the status of the chip eliminating the need for external hardware. 2.6 Electronic Signature for Device Identification An extra row of 32 bytes of EEPROM memory is avail- able to the user for device identification. By raising A9 to 12V ±0.5V and using address locations 1FEO to 1FFF, the additional bytes can be written to or read from in the same manner as the regular memory array. 2.7 Chip Clear All data may be cleared to 1's in a chip clear cycle by raising OE to 12 volts and bringing the WE and CE low. This procedure clears all data, except for the extra row.
- 7. 28C64A 28C64A Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. Package: L = Plastic Leaded Chip Carrier (PLCC) P = Plastic DIP (600 mil) SO = Plastic Small Outline IC (600 mil) Temperature Blank = 0°C to +70°C Range: I = -40°C to +85°C Access Time: 15 150 ns 20 200 ns 25 250 ns Shipping: Blank Tube T Tape and Reel “L” and “SO” Option: Blank = twc = 1ms F = twc = 200 µs Device: 28C64A 8K x 8 CMOS EEPROM 28C64A F T – 15 I /P 2004 Microchip Technology Inc. DS11109K-page 7
- 8. 28C64A DS11109K-page 8 2004 Microchip Technology Inc. NOTES:
- 9. 2004 Microchip Technology Inc. DS11109K-page 9 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
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