6.design and implementation of fast floating point multiplier unit
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This document describes the design and implementation of a fast floating point multiplier unit. It discusses floating point numbers that cannot be represented by integers and the importance of fast floating point multiplication. The proposed method implements a floating point multiplier using Verilog HDL to increase speed. Applications include digital signal processing, microprocessors, and image processing. The design aims to decrease delay and increase speed by using pipelining and optimizing carry propagation in adders.
6.design and implementation of fast floating point multiplier unit
- 1. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 DESIGN AND IMPLEMENTATION OF FAST FLOATING POINT MULTIPLIER UNIT Abstract: Floating point numbers are the quantities thatcannot be represented by integers, either because they contain fractional values or because they lie outside the range re presentable within the system's bit width. Multiplication of two floating point numbers is very important for processors. Architecture for a fast floating point multiplier yielding with the single precision IEEE 754- 2008 standard has been used in this project. The floating point representation can preserve the resolution and accuracy compared to fixed point. Pipeline is a technique where multiple instructions are overlapped in execution. Multiple operations performed at the same time by pipeline will increase the instruction throughput. In several high performance computing systems such as digital signal processors, FIR filters, microprocessors, etc multipliers are key components. The most important aim of the design is to make the multiplier quicker by decreasing delay. Decrease of delay can be caused by propagation of carry in the adders having smallest amount power delay constant. Existing Method: The change in the level of integration broughtabout by up to date VLSI trends has rendered possible the mixing of many complex components in a single device. This single device has ready the systems work faster and useful for applications such as portable device like mobile phone, multimedia and methodical computation. As the technology is advancing need for high
- 2. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 speed is on a rise. Multiplier unit uses maximum time and power compared to other arithmetic unit. To reduce the computation time efficient multiplier units are used. Thus, the speed, power and size of a multiplier has been a key issue and therefore the many focus on their research projects. Proposed Method: In floating point will use extensive range ofvalues. Floating point unit is widely used in various applications. This makes the developer to work on faster floating point multiplier units. Floating-point representation can keep its resolution and accuracy when evaluate to fixed-point representations. In this Paper a Floating Point Multiplier is Implemented Using Verilog HDL. Applications: 1. Arithmetic applications. 2. Digital Signal Processing. 3. ALU of Microprocessors. 4. Image processing…etc... Advantages: 1. High Speed, 2. Low power and 3. Less Area. System Configuration:- In the hardware part a normal computer where Xilinx ISE 14.3 software can be easily operated is required, i.e., with a minimum system configuration
- 3. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 HARDWARE REQUIREMENT Processor - Pentium –III Speed - 1.1 GHz RAM - 1 GB (min) Hard Disk - 40 GB Floppy Drive - 1.44 MB Key Board - Standard Windows Keyboard Mouse - Two or Three Button Mouse Monitor - SVGA SOFTWARE REQUIREMENTS Operating System :Windows95/98/2000/XP/Windows7 Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation
- 4. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 This software’s where Verilog source code can be used for design implementation.