INTEL 8051-PORT 1
PREPARED BY
B.SARAVANAMANIKANDAN
ASSISTANTPROFESSOR
Kongunadu college of engineering and technology
Port-1 Configuration
KNCET EEE Department
• Port 0 and 2 together can be used to address the external
memory. Port 0 can also be used to exchange data from
the external port. accessing 64K bytes of external memory,
it needs a path for the 16 bits of the address. P0 gives
lower Byte of Address.
KNCET EEE Department
PORT 1
• Port 1 is a bidirectional I/O port with internal pull ups
• The circuit has 3 FET.
• When port 1 as input port logic level is loaded
to the latch .This is will turn off the FET 1.
• This will effectively float the port pin to high impedance
state and will be connected the pin read buffer.
• The pin is at logic level 1 is at instant.
• An external device may place a 0 by driving the pin ground
or it may place a 1 on pin by leaving it at logic state.
KNCET EEE Department
• When used as output port the value will be loaded to the
latch.
• The latches which contain level 1 will turn off FET T1 and
will drive the pin high through pull register formed by T2
and T3.
• This will ground the pin and it will show logic level 0.
• The latches containing level 0 will turn on FET 1
KNCET EEE Department
PORT 2
KNCET
EEE Department
PORT 2
• Port 2 can be used as a bidirectional I/O port
• It can used as a higher order internal bus for external memory
interface
• When used as a input port logic level is stored in latch
• T1 is turned of and floats in high impedance state. The pin is
directly connected pin read buffer.
• The external device can place 0 or 1.
• When used as output port the working of port is similar to port 1 that
means the latch o will turn on FET T1.
• Thus ground the pin
• The latch containing 1 will turn off T1 and pin will be driven to logic
level 1.
• When port is used to higher order address bit for external memory
access the control . They are directly connected pin trough FET
KNCET
EEE Department
PORT 3
KNCET EEE Department
PORT 3
• Port 3 can be used as a bidirectional I/O.
• Different pins of port3 also facilitate alternate functions.
• The functions port3 pins is either under the control of port
latches under the control of SFR.
• These pins are individually programmable unlike other
ports where alternate functions of all port pins are
programmed together.
• It read by two ways
read latch signal
read pin signal
KNCET EEE Department
Conclusion:
• The port configuration of 8051 microcontroller are
explained in detail manner.
KNCET
EEE Department
KNCET EEE Department

More Related Content

PPTX
8051 i/o port circuit
PPTX
Unit2.2 8051
PPT
Ch3 ppt
PDF
8051 Microcontroller I/O ports
PPT
Micro controller
PPSX
8051 architecture
DOC
4th yr dmumicrocontroller1
8051 i/o port circuit
Unit2.2 8051
Ch3 ppt
8051 Microcontroller I/O ports
Micro controller
8051 architecture
4th yr dmumicrocontroller1

What's hot (20)

PPTX
8051 Microcontroller
PPT
8051 microcontroller and it’s interface
PDF
AT89C51 Data sheets
PDF
PPTX
I o ports.ppt
PPT
8051 Microcontroller
PPTX
8051 microcontroller
PPTX
I/O port programming in 8051
PPTX
Embedded systems, lesson 16
PPTX
Interfacing external memory in 8051
PPTX
8051 Microcontroller PPT's By Er. Swapnil Kaware
PPT
Microcontroller 8051
PPTX
8051 microcontroller
PPT
Microcontroller 8051
DOC
Pc based wire less data aquisition system using rf(1)
DOCX
Study of 8051 microcontroller
PDF
Unit 5
PDF
International Journal of Engineering Research and Development (IJERD)
PPT
Microcontroller 8051
PPTX
8051 Microcontroller
8051 Microcontroller
8051 microcontroller and it’s interface
AT89C51 Data sheets
I o ports.ppt
8051 Microcontroller
8051 microcontroller
I/O port programming in 8051
Embedded systems, lesson 16
Interfacing external memory in 8051
8051 Microcontroller PPT's By Er. Swapnil Kaware
Microcontroller 8051
8051 microcontroller
Microcontroller 8051
Pc based wire less data aquisition system using rf(1)
Study of 8051 microcontroller
Unit 5
International Journal of Engineering Research and Development (IJERD)
Microcontroller 8051
8051 Microcontroller
Ad

Similar to 8051 port configuration (20)

PPTX
8051 i o port circuit
PPTX
Input and Output ports of controller.pptx
PPTX
1.7_IO Ports (2).pptx
PDF
SE PAI Unit 5_IO programming in 8051
PPTX
Microcontroller (1).pptx
PPTX
Hardware View of Intel 8051
PPT
Interface
PDF
Pin configuration of 8051 Microcontroller.pdf
PPTX
DMA It can give more time to an intersection approach that is experiencing h...
PPTX
computer architecture and micro controllers
PPT
I o ports and timers of 8051
PPTX
8086 – CPU –Pin Diagram.pptx
PPT
8051-microcontroller
PPT
Logic gates
PPT
PPTX
3-8051 Microcontroller-28-01-2024 (1).pptx
PPTX
UNIT 4 8051Microcontroller.pptx
PPTX
Unit 01.Lec2 Introduction to 8051 microcontroller (2).pptx
PPTX
UNIT 4.pptx
PDF
COA UNIT-1 Input-Output Instructions.pdf
8051 i o port circuit
Input and Output ports of controller.pptx
1.7_IO Ports (2).pptx
SE PAI Unit 5_IO programming in 8051
Microcontroller (1).pptx
Hardware View of Intel 8051
Interface
Pin configuration of 8051 Microcontroller.pdf
DMA It can give more time to an intersection approach that is experiencing h...
computer architecture and micro controllers
I o ports and timers of 8051
8086 – CPU –Pin Diagram.pptx
8051-microcontroller
Logic gates
3-8051 Microcontroller-28-01-2024 (1).pptx
UNIT 4 8051Microcontroller.pptx
Unit 01.Lec2 Introduction to 8051 microcontroller (2).pptx
UNIT 4.pptx
COA UNIT-1 Input-Output Instructions.pdf
Ad

More from saravanamanikandan02 (6)

PPTX
Programmable dma controller 8237
PPTX
Timers of 8051
PPTX
DATA TRANSFER SCHEMES OF 8085
PPTX
Addressing modes 8085
PPT
Machine cycles
PPTX
Programmable dma controller 8237
Timers of 8051
DATA TRANSFER SCHEMES OF 8085
Addressing modes 8085
Machine cycles

Recently uploaded (20)

PPTX
AUTOMOTIVE ENGINE MANAGEMENT (MECHATRONICS).pptx
PDF
Accra-Kumasi Expressway - Prefeasibility Report Volume 1 of 7.11.2018.pdf
PPTX
Sorting and Hashing in Data Structures with Algorithms, Techniques, Implement...
PDF
Applications of Equal_Area_Criterion.pdf
PPTX
Chemical Technological Processes, Feasibility Study and Chemical Process Indu...
PDF
Java Basics-Introduction and program control
PDF
Abrasive, erosive and cavitation wear.pdf
PPTX
CyberSecurity Mobile and Wireless Devices
PPTX
"Array and Linked List in Data Structures with Types, Operations, Implementat...
PDF
UEFA_Embodied_Carbon_Emissions_Football_Infrastructure.pdf
PPTX
Information Storage and Retrieval Techniques Unit III
PDF
null (2) bgfbg bfgb bfgb fbfg bfbgf b.pdf
PDF
MLpara ingenieira CIVIL, meca Y AMBIENTAL
PPTX
Graph Data Structures with Types, Traversals, Connectivity, and Real-Life App...
PPTX
Principal presentation for NAAC (1).pptx
PDF
Implantable Drug Delivery System_NDDS_BPHARMACY__SEM VII_PCI .pdf
PPTX
CN_Unite_1 AI&DS ENGGERING SPPU PUNE UNIVERSITY
PPTX
mechattonicsand iotwith sensor and actuator
PDF
Design Guidelines and solutions for Plastics parts
PPTX
Measurement Uncertainty and Measurement System analysis
AUTOMOTIVE ENGINE MANAGEMENT (MECHATRONICS).pptx
Accra-Kumasi Expressway - Prefeasibility Report Volume 1 of 7.11.2018.pdf
Sorting and Hashing in Data Structures with Algorithms, Techniques, Implement...
Applications of Equal_Area_Criterion.pdf
Chemical Technological Processes, Feasibility Study and Chemical Process Indu...
Java Basics-Introduction and program control
Abrasive, erosive and cavitation wear.pdf
CyberSecurity Mobile and Wireless Devices
"Array and Linked List in Data Structures with Types, Operations, Implementat...
UEFA_Embodied_Carbon_Emissions_Football_Infrastructure.pdf
Information Storage and Retrieval Techniques Unit III
null (2) bgfbg bfgb bfgb fbfg bfbgf b.pdf
MLpara ingenieira CIVIL, meca Y AMBIENTAL
Graph Data Structures with Types, Traversals, Connectivity, and Real-Life App...
Principal presentation for NAAC (1).pptx
Implantable Drug Delivery System_NDDS_BPHARMACY__SEM VII_PCI .pdf
CN_Unite_1 AI&DS ENGGERING SPPU PUNE UNIVERSITY
mechattonicsand iotwith sensor and actuator
Design Guidelines and solutions for Plastics parts
Measurement Uncertainty and Measurement System analysis

8051 port configuration

  • 1. INTEL 8051-PORT 1 PREPARED BY B.SARAVANAMANIKANDAN ASSISTANTPROFESSOR Kongunadu college of engineering and technology
  • 3. • Port 0 and 2 together can be used to address the external memory. Port 0 can also be used to exchange data from the external port. accessing 64K bytes of external memory, it needs a path for the 16 bits of the address. P0 gives lower Byte of Address. KNCET EEE Department
  • 4. PORT 1 • Port 1 is a bidirectional I/O port with internal pull ups • The circuit has 3 FET. • When port 1 as input port logic level is loaded to the latch .This is will turn off the FET 1. • This will effectively float the port pin to high impedance state and will be connected the pin read buffer. • The pin is at logic level 1 is at instant. • An external device may place a 0 by driving the pin ground or it may place a 1 on pin by leaving it at logic state. KNCET EEE Department
  • 5. • When used as output port the value will be loaded to the latch. • The latches which contain level 1 will turn off FET T1 and will drive the pin high through pull register formed by T2 and T3. • This will ground the pin and it will show logic level 0. • The latches containing level 0 will turn on FET 1 KNCET EEE Department
  • 7. PORT 2 • Port 2 can be used as a bidirectional I/O port • It can used as a higher order internal bus for external memory interface • When used as a input port logic level is stored in latch • T1 is turned of and floats in high impedance state. The pin is directly connected pin read buffer. • The external device can place 0 or 1. • When used as output port the working of port is similar to port 1 that means the latch o will turn on FET T1. • Thus ground the pin • The latch containing 1 will turn off T1 and pin will be driven to logic level 1. • When port is used to higher order address bit for external memory access the control . They are directly connected pin trough FET KNCET EEE Department
  • 8. PORT 3 KNCET EEE Department
  • 9. PORT 3 • Port 3 can be used as a bidirectional I/O. • Different pins of port3 also facilitate alternate functions. • The functions port3 pins is either under the control of port latches under the control of SFR. • These pins are individually programmable unlike other ports where alternate functions of all port pins are programmed together. • It read by two ways read latch signal read pin signal KNCET EEE Department
  • 10. Conclusion: • The port configuration of 8051 microcontroller are explained in detail manner. KNCET EEE Department