A 2.4 ghz cmos lna input matching design using resistive feedback topology in 0.13µm technology

IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 172
A 2.4 GHZ CMOS LNA INPUT MATCHING DESIGN USING RESISTIVE
FEEDBACK TOPOLOGY IN 0.13µ𝒎 TECHNOLOGY
M.RamanaReddy1
, N.S MurthySarma2
, P.ChandraSekhar3
Abstract
The attempt made in the paper shows an innovative designing for the enhancement and reliability in CMOS technology. A 2.4 GHz
resistive feedback narrowband noise amplifier (LNA) using a series inductor input matching networks. It is easy reliable with an extra
gm boosting as well as inductively degenerated topology. By using this resistive feedback topology increases the gain as well as noise
figure of 2.2 dB,S21 parameter of 26dB,and IIP3 of -13dBm,while 2.8mW of power consuming from a 1.2V and its area 0.6mm2
in
0.13µm CMOS ,which gives the best figure of merit and performance.
Keywords: LNA, CMOS, noise figure, resistive feedback, gm boosting, voltage gain boosting.
-------------------------------------------------------------------***------------------------------------------------------------------
1. INTRODUCTION
Still the challenge is CMOS radio frequency (RF) front end
circuit is for high performance, low cost, low power
consumption [1]-[7]. The topologies like inductively coupled
degenerated common source. LNA [3], and the resistive
feedback LNA have their own advantages and disadvantages
with limitations. In order to overcome the limitations so many
designs have been implemented and investigated.
By using inductively degenerated narrow band systems low
NF, ease of input matching, high gain and low power
consumption[8]. However due to inductor at gate and source
the input device large inductance values would be required and
also occupies large chip area due to these RF LNA provides
wideband input and output matching and small die area
because no inductor is required for input matching.
The input matching can be a series resonator circuit for the RF
front end to an external device antenna, an RF switch as shown
in below figure 1.It can generate Q-times if voltage gain across
cgs [1] to match the input impedance. At a resonant frequency
w0, the quality factor is given by QL=(w0 Lser/Rser)and the
voltage across the Cser is jQLVin.
Fig (1) Input matching network (a) parallel RLC network (b)
Series RLC network
In section I this paper proposed a resistive feedback topology
LNA gm boosting from inductively degenerated topology and
input matching network from resistive feedback. Section II
describes the proposed LNA concepts, noise analysis with
small signal models. In section III implementation and
experimental results of LNA conclusions are in section IV.
1.1 LNA Requirements:
1. Gain (10-20 db) to amplify the received signal and to reduce
the input referred noise of the subsequent stages.
2. Good linearity: Handling large undesired signals without
much distortion.
3. Low noise for high sensitivity
4. Maximum power gain 50  termination for proper operation
and can route the LNA to the antenna which is located an
unknown distance away without worrying about the length of
the transmission line [10],[12].
1.2 Basic Topologies
1. Wide band LNA input matching topologies (a) Resistive
termination (b) common gate (c) resistive shunt feedback.
2. Narrow band LNA input matching topologies (a) inductive
degenerated (b) resistive terminated [10] , [12].

__________________________________________________________________________________________
1.3. Resistive Feedback LNA:
(a)
(b)
Fig 2(a): Resistive feedback low noise amplifier (b):
equivalent input matching network
Fig(2) shows the RF LNA schematic ,the series RLC resonator
matching for the resistive feedback topology, the input
impedance at the gate of M1 is converted into series network C
res and R ser ,as shown in above fig. where C sc is[12]
2
1
(1 )gs
L
c
Q
 , R Series
  2
1 1
F L
m L L
R R
g R Q

 
,
RL is output impedance L
L
L
C
at the operating frequency and is
0
L
series
LG
Q
R
 
 
 
.
The series matching topology boosts the voltage gain at the
gate M1 by (1-jQL) and hence the effective trans conductance is
boosted by  2
1 LQ this LNA can achieve a voltage gain by
a factor of
 2
2
1 L
L
Q
Q

when compared to L-degenerated
LNA [12].
Fig: (3) Noise analysis of small signal model of the gm
boosted resistive feedback.
From above fig 3.The input impedance [12]
  2
2
1
1
1
1
1 11
1
F L
in G
gs m L
F L
G
m L L
gs
L
R R
z sL
sC g R
R R
sL
g R Q
sC
Q
 
   
  

  
   
 
 

z in is
equal to
  2
1 1
F L
m L L
R R
g R Q

 
at resonant frequency ωo..
In this proposed LNA, the inductor at the source of M1 is
Eliminated compared with the inductive common source LNA
.By removing this source inductor reduces the chip area. The
typical q of a an integrated inductor is in the range of 5-20
[13].In order to reach noise figure 1 Db ,the parasitic ,such as
substrate resistance ,ESD ,and series inductor resistance
dominate the noise performance of LNA. This topology more
freedom for the chosen of single inductor (LG), with nice
quality factor for high noise performance design aspect [14].
2. NOISE ANALYSIS
The small signal model of fig(3) is the gate resistance of the
input resistor,M1 is neglected with consideration of gate
impedance is capacitive ,and the blocking capacitor in the
feedback path is shorted, since it has a small impedance at the
required frequency RL is the loss of gate inductor LG .the
transistor M2 is not considered in case of the noise contribution

__________________________________________________________________________________________
because of noise cancellation mechanism of cascade
configuration of the transistor when the inverse trans
conductance of the cascade .RL is the load impedance when LL
and CL resonate at the resonant frequency.
The noise factor calculation for designed topology is
 
   
 
 
 
2
2 2 2 2
2
2 2
2
2
1
1 1
1
2 | |
51
1
2
51
F LLG
S F L L m s L m s
oF L
L TL m s
oF L
L TL m s
R RR
F
R R R Q g R Q g R
R R
c
R Q g R
R R
R Q g R







   
 
   
   
   
   
   
   
Where α is the ratio of device trans conductance and the zero
bias drain conductance, where γ is the thermal noise factor, δ is
the gate induced noise factor, C is correlation coefficient
between drain noise and induced gate noise for long channel
devices=1, γ=2/3, δ=4/3 and C=-j0.395[1], [14]. The important
relation (RF+RL)/(gmRL(1+QL
2
)) is equal to Rs(gmRL>>1) for
the narrow band LNA.
From fig(2), the input matching condition is applied , when
RF>>RL, it can be assumed that [(RF+2RL)/ (RF+RL)2
]=1, at this
condition noise factor function of QL can be expressed as
 
   
2
2
2
1
1
1
2 | | 1 3
5 5
LG
S m L L m s
o o
L m s
T T
R
F
R g R Q g R
c Q g R


  
 
    

   
    
   
The minimum noise factor and optimum Q factor is expressed
by
min. 1 2.30 (4)D
o
p
T
F

 
 
   
 
And
2
53
1 1 1
| |
| | (5)
5 5
1
S
L
Lopt
S
L
R
Rc
Q c
R
R


  
    
  
  
      
Let α=1, C=-J0.395, =2.5 and α=5 for a short channel device
[1] and RS =50Ω,RL=1KΩ then 4 and 5 equations become as
min. 1 5.75 (6)D
o
p
T
F


 
   
 
3.34(7)LoptQ 
2.1 LNA Implementation
The complete schematic of the proposed resistive feedback
LNA input matching topology designed in a standard 8 metal
0.18mm RF CMOS technology which is operated at 2.4 GHz
shown in fig 4.the two stage cascaded architecture of a core
amplifier and an open-drain output buffer. the cascade
configuration of core amplifier have provided isolated and
reduce the Miler capacitance in between gate and drain of the
input device M1 with size 200µm/0.13µ𝑚 which gives
minimum NF, with 2 ma and 1.2 V supply for transistor
biasing.
The M5 transistor M6 transistor which have thick gate oxide,
high threshold and break down voltage to protecting the gate of
the input device from electro static discharge(ESD)[15]. The
ESD protection device improves the noise figure by 0.1 dB
because of parasitic capacitance and finite output resistance.
The total gate inductance is approximately 8.8 ƞH .the
feedback resistance RF is 8.4 k Ω and load impedance is
8nH.the quality factor is10.
2.2 Simulated Results And Discussion:
The fig (4) Shows the S-parameter.S11 of the designed LNA is
-10.7dB,S21 is28.3 dB .The noise figure is 2.2dB ,the IIP3(third
order interception point)including buffer is -22.4 dBm and
table is given below
3. SIMULATION RESULT ANALYSIS
Table-1 parameters and performance
Specs Simulation
Frequency 2.4Ghz 2.4Ghz
S11 -10dB - 12 dB
S21 28dB 28.7dB
NF 2dB 2.2dB
IIP3 10dBm -22.4dBm
Power 4.8mw 4.8mw
Supply 1.2v 1.2v
The design was simulated using the ADS and also cadence
tools provided for the 0.13m RF CMOS process. The
following graphs shows S21, S11, noise figure, IIP3, of
resistive feedback topology LNA

__________________________________________________________________________________________
(a)
(b)
(c)
(d)
(e)
Fig 4 (a) S21 parameters (b) noise figure (c) S22parameters (d)
S11Parameters (e) Third order intercept point
4. CONCLUSIONS
The design of receiver supporting 4G wireless applications in
all bands presents many challenges. Some of the characteristics
of the receivers are multi band multi standard operation,
MIMO support, low power and low cost. By applying
analytical mode lings for key performance parameters of LNA
is required 4G front ends. This paper has presented the design
of gain S21 28dB with a noise figure 2dB while drawing
4.8mW power from 1.2 volts supply by using resistive
feedback LNA topology. A lesson learned in this design is the
importance of intuitive understanding of resonance and circuit
theory, while the design of LNA is being made with wireless
telemetry telecommand system and also for wireless sensor
networks.

__________________________________________________________________________________________
REFERENCES
[1] D. Shaeffer, T. Lee, "A 1.5V, 1.5 GHz CMOS low noise
amplifier", IEEE Journal of Solid State Circuits, Vol. 32, May
1997.
[2] T.H. Lee, "5-GHz CMOS low noise amplifier", IEEE
Journal of Solid State Circuits, Vol.32, May, 1997.
[3] Shaeffer, T.H. Lee,””Comment on Corrections to a
1.5V,1.5 Ghz CMOS low noise amplifier ,”IEEE J. Solid-State
Circuits,vol.41,no,pp.2359,oct 2006.
[4] D.J.Allstot,X,Li, and S.Shekar, ”Design considerations for
CMOS low-noise amplifiers,” in Proc.IEEE Radio Frequency
Integrated Circuits Symp, jun 2004,pp 97-100. `
[5] F.Bruccoleri,E.A.M.Klumperink, and B.Nauta, “Wide-band
CMOS low noise amplifier exploiting thermal noise
cancelling.” IEEE J. Solid State Circuit, vol.39, no.2.pp.275-
282, Feb.2004.
[6] P.Heydari, “Design and analysis of performance-optimized
CMOS UWB distributed LNA,”IEEEJ .Solid-State Circuits,
vol.42, no.9 PP 1892-1905, Sep 2007.
[7] J.Borremans, P.Wambacq, C.Soens, Y.Rolain, and
M.Kuijk,“Low-area active-feedback low-noise amplifier
design in scaled digital CMOS,”IEEEJ. Solid-state Circuits,
vol43 no.11, pp 2422-2433, nov 2008.
[8] A 2.4 GHz LNA is 0.18/micron CMOS Technology
"International Conference on VLSI communication and
Instrumentation ICUCI 2011 Proceedings published by
International Journal of Computer Applications (IJCA).
[9] PTM Website (online available (Transistors)
http://ptm:asu.edu/
[10] T.Lee, "The design of radio frequency integrated circuits"
second edition, Cambridge 1998.
[11]. Agilent Technologies, Web.
http://prphotos.tm.agilent.com/2010/03sepem10109 index.html
[12]. ECEN 665 (ESS) “RF Communication Circuits and
Systems”.
[13]. J.R.Long and MA Coplan, “The modeling,
characterization, and design of monolithic for silicon RF ic’s”
IEEE J.Solid state circuit, Vol.32 no.3, pp 357-369,
march.1997.
[14]. A.Vander ziel, "Noise in solid–state devices and lasers",
pro.IEEE, vol.5.8, no 8 pp.1178-1206, Aug.1970.
[15]. B.Kleveland, T.J.Maloney, I.Morgan, L. Madden,
T.H.Lee, and S.S.Wong, "Distributed ESD protection for high
speed integrated circuits" IEEE Electron device
let,,vol.21,.pp.390-392 ,Aug.2000.

A 2.4 ghz cmos lna input matching design using resistive feedback topology in 0.13µm technology

More Related Content

What's hot (18)

Similar to A 2.4 ghz cmos lna input matching design using resistive feedback topology in 0.13µm technology (20)

More from eSAT Journals (20)

Recently uploaded (20)

A 2.4 ghz cmos lna input matching design using resistive feedback topology in 0.13µm technology