M.TECH IEEE.Technical seminar paper for Vlsi design and embedded systems.
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The document proposes designs for ternary logic gates based on single power supply voltage for CMOS technology. It describes the design of a simple ternary inverter (STI), negative ternary inverter (NTI), and positive ternary inverter (PTI) using only enhancement-type MOSFETs. Transistor widths and lengths are optimized to achieve the desired voltage transfer characteristics. Basic ternary logic gates including a ternary NAND (TNAND) and ternary NOR (TNOR) are also designed using a similar single-transistor approach. The proposed gate designs aim to reduce transistor count and power consumption compared to prior ternary logic designs.
![Design of CMOS Ternary Logic Family based on
Single Supply Voltage
V. T. Gaikwad P. R. Deshmukh
Department of Information Technology, Amravati (M.S.), India
Sipna COET, Amravati (M.S.), India,
vtgaikwad@rediffmail.com
Abstract— Since inception, CMOS logic is considered for
implementation of only binary logic. As the circuit complexity is
increasing, the interconnection in binary occupies large area on a
VLSI chip and thus, degrading the performance of binary. Hence
the non binary higher radix logic which is called as multi valued
logic (MVL) is considered as solution to this issue. A ternary logic
or a three-valued logic is considered as the best radix of several
MVL systems. In this paper, the designs of ternary logic circuits
are proposed based on single power supply voltage. The proposed
ternary logic gates are useful in designing the ternary logic
circuits. The proposed designs are based on the use of only
enhancement type MOSFETS so that it can be implemented with
recent CMOS technology.
The design of a set of inverters and basic ternary logic gates
is proposed. The transistor count in the basic ternary gates is
being reduced thereby improving component density. The
proposed GATES are designed & simulated with the help of
Microwind EDA tool & can be implemented at its layout side
using VLSI CMOS technology.
Keywords – CMOS technology, Radix, Enhancement
MOSFET, Multi Valued Logic, Ternary Logic, VLSI.
I. INTRODUCTION
Because of the advanced MOS technology & an easily
implemented binary algebra, the circuit complexity of binary
logic has been successfully pushed to the VLSI/ULSI level.
However, there exists some problem in present-day binary
systems that of interconnection, both on chip and off chips. On
chip, the interconnection problem is in the wire routing. As the
scale of integration continues to increase, the silicon area for
wire routing becomes increasingly greater than that for the
active logic elements, owing to the vast information exchanges
between each active block in the system. Therefore the speed
of a circuit decreases, due to the accompanied larger
capacitance with the longer interconnection lines. In the other
respect, the interconnections between chips face the pin
number limit. As well as the pin counts increasing at an
incredible rate as the chip becomes larger, the system
performance is also sacrificed due to frequent off-chip
connections. All the above difficulties can be reduced if the
multi valued logic is used for interconnections as it contents
more information per interconnection as compared to binary
interconnections. Therefore the multi valued logic is now
being considered for designing of VLSI/ULSI digital systems
due to its advantages over binary logic [1] [2] [3]. The multi
valued implementation will not only allow for transmitting
more information but it effectively reduces the chip area also.
The other advantage of using the MVL for interconnection is
that the number of pin outs and interconnections can be
reduced [4].
The multi valued logic memories are implemented
commercially. Considering the cost and radix relation
theoretically, the ternary logic circuits are more economical
than binary logic circuits [5-6].
But the complexity in design is a main draw back in
multiple valued logic circuits as compared to the binary logic
circuits. There has been development in the MVL circuit
implementation with the growth of device technology.
Several authors [6-15] have proposed the realization of
ternary CMOS circuits. In most of these designs, the power
supply voltages higher than the MOSFETs threshold voltages
are used which leads to the high power consumption. The
Carbon Nanotube FET (CNTFET) based multi valued circuits
have been reported by some authors [16-17] where they have
specified the issue related to metallic CNTs.
II. DESIGN AND SIMULATION OF TERNARY
LOGIC GATES
In design of digital systems, the inverter, NOR gate, and
NAND gates are considered to be the basic building blocks.
We propose the implementations of ternary inverter, NOR
gate, and NAND gate. The prime objective in our work is to
minimize the power consumption and propagation delay times
thereby reducing the number of transistors, by eliminating the
use of resistors. In the proposed designs the smaller single
supply voltage and the MOSFETs with smaller threshold
voltage are used. Three logic levels are represented by states 0,
1, 2 with potential (0v), (0.5v), and + Vcc (+1v) respectively.
III. DESIGN OF TERNARY INVERTER
The ternary inverter is a complement function; which in
the binary notation is known as an inverter. It is also called as
the MVL-NOT function. Depending on the inversion logic,
ternary inverters are of tree types namely, STI (Simple
Ternary Inverter), NTI (Negative Ternary Inverter) and PTI
(Positive Ternary Inverter). The logic functions of these
2015 International Conference on Pervasive Computing (ICPC)
978-1-4799-6272-3/15/$31.00(c)2015 IEEE](https://image.slidesharecdn.com/designifcmosternarylogicfamily-151219205530/85/M-TECH-IEEE-Technical-seminar-paper-for-Vlsi-design-and-embedded-systems-1-320.jpg)
![inverter are shown in Tab. 1. The rule of ternary inversion for
these three types of basic ternary operations are defined by in
equation (1)
𝑋𝑐 = �
𝐶 , 𝑖𝑓 𝑥 = 1
𝐶 − 𝑋 , 𝑖𝑓 𝑥 ≠ 1
(1)
Where the value of 𝐶 in above equation is 2 for a PTI, 1 for a
STI and 0 for a NTI.
A MVL-NOT function is an elementary function in
MVL. High accuracy is necessary for voltage mode multi-
valued signal as the voltage levels for each logic level are
equal division of VDD.
Table I gives the truth table for these inverters
TABLE I. TRUTH TABLE OF TERNARY INVERTERS.
X NTI PTI STI
0 2 2 2
1 0 2 1
2 0 0 0
The logic symbols of these three inverters are given in Fig. 1.
(a)
(b)
(c)
Fig.1 Ternary Inverter symbols (a) STI. (b) NTI (c) PTI
A. Commutation Point of Inverters
The commutation voltage Vc is prime aspect in proper
design of ternary inverters which works as a switching
element. The commutation point is deciding the threshold of
switching activity of the inverter. The sizing of NMOS &
PMOS devices has a strong influence on the commutation
point Vc. The commutation voltage of an inverter can be given
as,
𝑽𝒄 =
𝑲.𝑽 𝑻𝑵 + 𝑽 𝑫𝑫− 𝑽 𝑷𝑷
𝟏+𝑲
(2)
Where
K = �
µn
Wn
Ln
µp Wp
Lp
𝝁 𝒏 - mobility of electron (600 V.cm-2
)
𝝁 𝒑 - mobility of holes (270 V. cm-2
)
𝑾𝒏 - n-channel MOS width ( in µm)
𝑳𝒏 - n- channel MOS lencth ( in μm)
𝑾𝒑 - p channel MOS width ( in µm)
Lp - p channel MOS length ( in µm)
𝑽 𝑫𝑫 - supply voltage (1.0V)
𝑽 𝑻𝑵 - Threshold voltage of n-channel device.
VTP - threshold voltage of p-channel device
For the proposed designs of STI, NTI & PTI, the appropriate
values of W/L based on equation (2) are used.
The commutation points of the inverters can observe on the
respective transfer characteristics.
B. Design of STI, NTI & PTI
MOS implementation of STI is described in [13, 14]. In
traditional design of simple ternary inverter (STI), positive
ternary inverter (PTI), negative ternary inverter (NTI) use a
pass transistors/CMOS transmission gate at its output is done
by using dual supply voltage.
Alternative new implementation of these three inverters is
shown in Fig. 2. The designs using single supply voltage &
without using the transmission gate or pass transistors leads to
a significant reduction in the power dissipation as well as in
propagation delays.
Fig 2. Schematic of CMOS STI, NTI & PTI.
Transistor T1 is enhancement PMOS & transistor T2 are
enhancement NMOS. The schematic for STI, NTI & PTI is
same but with the variation in width and length parameter of
each. Fig. 3 shows design layout of a Simple Ternary Inverter
(STI) implemented using a PMOS transistor & NMOS
transistor with Logic 2 at VDD, Logic 0 at GND (0 V) & logic
1 is a middle voltage between VDD & GND. The resistance of
channels can be change by changing the length-to-width ratio
of the PMOS and NMOS transistors. Thus, the length-to-width
ratio can be effectively used to change the resistance of
transistors as per the design requirement [8] [9].](https://image.slidesharecdn.com/designifcmosternarylogicfamily-151219205530/85/M-TECH-IEEE-Technical-seminar-paper-for-Vlsi-design-and-embedded-systems-2-320.jpg)
![Fig.3. Layout of Standard Ternary Inverter (STI)
The set of ternary inverters and logic gates like TNAND
(Ternary NAND) and TNOR (Ternary NOR) can be used to
realize the complex ternary functions
The circuit operation of this STI is simulated and
analyzed using Microwind design and simulation tool. Fig. 7
shows the output Voltage Vs Time characteristics and Fig. 8
shows the transfer characteristics of STI. Table II gives the
logic level voltages for inputs and outputs of ternary inverters.
TABLE II. STI LOGIC LEVEL VOLTAGE
Logic
Value
Voltage Level
I/p (V)
Voltage Level
O/p (V)
0 0 1.0
1 0.5 0.51
2 1.0 0
The power dissipation and the transition time of output
voltage signal are observed to be very small as specified in
result section.
IV. DESIGN OF TERNARY NAND GATE
A TNAND function gives the inversion of the minimum
value of the input signal where input signal belongs to 0, 1 and 2
or -1, 0 & +1 in balance ternary [1]. The NAND output can be
defined as,
Y= INV [ Min (I1,I2,I3…...In) ] (3)
The truth table of the function is given in Table III.
The CMOS design of proposed TNAND based on single supply
voltage is shown in Fig. 4. The results of the design are simulated
using Microwind. The transient characteristic of TNAND is
shown Fig 10 for Voltage Vs Time by applying different input
logic levels.
Fig.4. Proposed NAND with Standard Ternary logic
TABLE III: TERNARY NAND TRUTH TABLE.
V. DESIGN OF TERNARY NOR GATE
A TNOR o/p function gives the inversion of the
maximum value of the input signal [1]. Thus the NOR output can
be defined as,
Y= INV [ Max (I1,I2,I3…...In) ] (4)
TABLE IV TERNARY NOR TRUTH TABLE
Input A Input B
O/P
TNOR
0 0 2
0 1 1
0 2 0
1 0 1
1 1 1
1 2 0
2 0 0
2 1 0
2 2 0
Ternary NOR gate con be implemented with the same analogy
as that of TNAND.
Input A Input B
O/P
TNAND
0 0 2
0 1 2
0 2 2
1 0 2
1 1 1
1 2 1
2 0 2
2 1 1
2 2 0](https://image.slidesharecdn.com/designifcmosternarylogicfamily-151219205530/85/M-TECH-IEEE-Technical-seminar-paper-for-Vlsi-design-and-embedded-systems-3-320.jpg)
![VI. DESIGN OF TAND & TOR GATES
The basic elements of ternary logic family are STI,
TNAND & TNOR. By using these gates we can further
implement TAND, TOR. The implementation is shown with
logic symbol in Fig. 6. The logic gates like TEXOR and
TXNOR can also be implemented using this basic gate.
In multi valued logic, AND is basically a MIN function
and OR is a MAX function[1], which are specified in equation
(5) and in equation (6) respectively.
TAND Output Y= MIN [I1,I2,I3…...In] (5)
TOR Output Y= MAX [I1,I2,I3…...In] (6)
TAND gate and TOR gates can be implemented by inverting
the outputs of TNAND & TNOR respectively by using the
STI.
a) TAND & TOR from TNAND & TNOR
b) Symbol of TAND & TOR gate
Fig. 6. Logic symbol for TAND & TOR
In the design of TAND & TOR, the STI, proposed in this
work is used for the inversion at the output of TNAND &
TNOR. As the STI is designed without using transmission
gate/ pass transistor, it effectively reduces the component
count in the design of TAND & TOR gates. Operation of these
designs is verified & analyzed. Fig 11 shows the verification
of output of TAND for different logic levels at the input.
VII. RESULTS & DISCUSSIONS
A. Simulation & verification of outputs
The proposed ternary logic gates are design & their
performance is simulated for 45 nm technology using Microwind
EDA tool. Fig.7 shows the transient characteristic and Fig. 8
shows the transfer characteristic of proposed STI.
The outputs for NTI and PTI are observed as per the truth
tables and are shown with their transient characteristics in Fig. 9
and in Fig. 10 respectively.
The truth tables of ternary NAND & ternary AND are verified by
applying all logic level combinations at the inputs. The
corresponding input and output characteristics are shown in Fig
11 for ternary NAND gate and in Fig 12 for ternary AND gate.
Fig 7.Transient characteristic for STI
Fig 8. Transfer characeristic of STI
Fig.9. Transient characteristic of NTI
Fig.10. Transient characteristic of PTI](https://image.slidesharecdn.com/designifcmosternarylogicfamily-151219205530/85/M-TECH-IEEE-Technical-seminar-paper-for-Vlsi-design-and-embedded-systems-4-320.jpg)
![Fig.11. Transient Characteristic of TNAND.
Fig.12. Output Voltage Vs Time Characteristic of TAND.
B. Power Dissipation
The power dissipation P depends on three main factors
capacitance C, the supply voltage VDD and the clock frequency
f. For a CMOS inverter, equation (7) below, shows a linear
dependence of the power dissipation on these three factors.
P=
1
2
C V2
DD f (7)
Where
C - output load capacitance (Farad)
VDD - supply voltage (V)
f - clock frequency (HZ)
The average power dissipation of these ternary gates
are calculated for the maximum output voltage swing. The
designs are proposed with the minimum transistor count
thereby reducing the overall power dissipation and reducing
the transition times.
Table V shows the average power dissipation over
500 ns time scale associated with the respective logic gate.
TABLE V. POWER DISSIPATION
Gate Power Dissipation
STI 0.065 µW
TNAND 0.191 mW
TAND 0.213 mW
Some of the results for power dissipation are compared with
the available results of previous designs & summarized in
following table VI.
TABLE VI: COMPARISON OF POWER DISSIPATION OF STI
Ref [6] Ref [14] Ref [12]
Proposed
Work
2.56
mw
0.7 µw 1.9 µw 0.065 µw
C. Rise time & Fall time
The rise time & fall time is mainly contributing to the
propagation delay of the logic gate. The proposed designs are
simulated to obtain rise time and fall time for various
switching transitions. The rise times and fall times of STI are
given in table VII
TABLE VII. RISE TIME & FALL TIME OF STI
O/p Transition
Rise Time/Fall
Time (ps)
1- 2 0.9
2 -1 1.1
1- 0 0.9
0 - 1 1.2
2 - 0 1.6
As the inverter is considered to be the basic switching
element in any design, the transition time of STI is considered
to be reference is observed to be very small.
CONCLUSION
Most of the traditional designs are based on ternary
logic, which requires dual power supply. Similarly for the
design of inverter as a basic switching element, the
transmission gates/ transistors are used to pull the output at
specific required voltage level. In the proposed designs, these
output transmission gates/pull up transistors is eliminated from
the inverters, thereby reducing the component count.
Similarly use of single power supply to implement the ternary
logic gates has lead to significant reductions in the overall
power dissipation and improving the transition time. The
proposed logic gates are useful further to design the low power
ternary circuits.
Considering the various advantages of the multi
valued logic, the appropriate design of the MVL logic gates is
important so that it will lead to the further development and its
applications in this area.](https://image.slidesharecdn.com/designifcmosternarylogicfamily-151219205530/85/M-TECH-IEEE-Technical-seminar-paper-for-Vlsi-design-and-embedded-systems-5-320.jpg)
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[13] A. Heung and H.T.Moufta, "Depletion/ enhancement CMOS for a low
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[14] P. C. Balla and Andreas Antoniou, “Low Power Dissipation MOS
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[15] J.S.Wang, C.Y. Wu, M.-K. Tsai, “Low power dynamic ternary logic”,
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[16] S. Lin, Y-B Kim, and F. Lombardi, “A novel CNTFET-based ternary
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[17] Jinghang Liang, Linbin Chen, Jie Han & Lombardi F., “Design and
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Page(s): 695 – 708, July 2014.](https://image.slidesharecdn.com/designifcmosternarylogicfamily-151219205530/85/M-TECH-IEEE-Technical-seminar-paper-for-Vlsi-design-and-embedded-systems-6-320.jpg)
M.TECH IEEE.Technical seminar paper for Vlsi design and embedded systems.
- 1. Design of CMOS Ternary Logic Family based on Single Supply Voltage V. T. Gaikwad P. R. Deshmukh Department of Information Technology, Amravati (M.S.), India Sipna COET, Amravati (M.S.), India, vtgaikwad@rediffmail.com Abstract— Since inception, CMOS logic is considered for implementation of only binary logic. As the circuit complexity is increasing, the interconnection in binary occupies large area on a VLSI chip and thus, degrading the performance of binary. Hence the non binary higher radix logic which is called as multi valued logic (MVL) is considered as solution to this issue. A ternary logic or a three-valued logic is considered as the best radix of several MVL systems. In this paper, the designs of ternary logic circuits are proposed based on single power supply voltage. The proposed ternary logic gates are useful in designing the ternary logic circuits. The proposed designs are based on the use of only enhancement type MOSFETS so that it can be implemented with recent CMOS technology. The design of a set of inverters and basic ternary logic gates is proposed. The transistor count in the basic ternary gates is being reduced thereby improving component density. The proposed GATES are designed & simulated with the help of Microwind EDA tool & can be implemented at its layout side using VLSI CMOS technology. Keywords – CMOS technology, Radix, Enhancement MOSFET, Multi Valued Logic, Ternary Logic, VLSI. I. INTRODUCTION Because of the advanced MOS technology & an easily implemented binary algebra, the circuit complexity of binary logic has been successfully pushed to the VLSI/ULSI level. However, there exists some problem in present-day binary systems that of interconnection, both on chip and off chips. On chip, the interconnection problem is in the wire routing. As the scale of integration continues to increase, the silicon area for wire routing becomes increasingly greater than that for the active logic elements, owing to the vast information exchanges between each active block in the system. Therefore the speed of a circuit decreases, due to the accompanied larger capacitance with the longer interconnection lines. In the other respect, the interconnections between chips face the pin number limit. As well as the pin counts increasing at an incredible rate as the chip becomes larger, the system performance is also sacrificed due to frequent off-chip connections. All the above difficulties can be reduced if the multi valued logic is used for interconnections as it contents more information per interconnection as compared to binary interconnections. Therefore the multi valued logic is now being considered for designing of VLSI/ULSI digital systems due to its advantages over binary logic [1] [2] [3]. The multi valued implementation will not only allow for transmitting more information but it effectively reduces the chip area also. The other advantage of using the MVL for interconnection is that the number of pin outs and interconnections can be reduced [4]. The multi valued logic memories are implemented commercially. Considering the cost and radix relation theoretically, the ternary logic circuits are more economical than binary logic circuits [5-6]. But the complexity in design is a main draw back in multiple valued logic circuits as compared to the binary logic circuits. There has been development in the MVL circuit implementation with the growth of device technology. Several authors [6-15] have proposed the realization of ternary CMOS circuits. In most of these designs, the power supply voltages higher than the MOSFETs threshold voltages are used which leads to the high power consumption. The Carbon Nanotube FET (CNTFET) based multi valued circuits have been reported by some authors [16-17] where they have specified the issue related to metallic CNTs. II. DESIGN AND SIMULATION OF TERNARY LOGIC GATES In design of digital systems, the inverter, NOR gate, and NAND gates are considered to be the basic building blocks. We propose the implementations of ternary inverter, NOR gate, and NAND gate. The prime objective in our work is to minimize the power consumption and propagation delay times thereby reducing the number of transistors, by eliminating the use of resistors. In the proposed designs the smaller single supply voltage and the MOSFETs with smaller threshold voltage are used. Three logic levels are represented by states 0, 1, 2 with potential (0v), (0.5v), and + Vcc (+1v) respectively. III. DESIGN OF TERNARY INVERTER The ternary inverter is a complement function; which in the binary notation is known as an inverter. It is also called as the MVL-NOT function. Depending on the inversion logic, ternary inverters are of tree types namely, STI (Simple Ternary Inverter), NTI (Negative Ternary Inverter) and PTI (Positive Ternary Inverter). The logic functions of these 2015 International Conference on Pervasive Computing (ICPC) 978-1-4799-6272-3/15/$31.00(c)2015 IEEE
- 2. inverter are shown in Tab. 1. The rule of ternary inversion for these three types of basic ternary operations are defined by in equation (1) 𝑋𝑐 = � 𝐶 , 𝑖𝑓 𝑥 = 1 𝐶 − 𝑋 , 𝑖𝑓 𝑥 ≠ 1 (1) Where the value of 𝐶 in above equation is 2 for a PTI, 1 for a STI and 0 for a NTI. A MVL-NOT function is an elementary function in MVL. High accuracy is necessary for voltage mode multi- valued signal as the voltage levels for each logic level are equal division of VDD. Table I gives the truth table for these inverters TABLE I. TRUTH TABLE OF TERNARY INVERTERS. X NTI PTI STI 0 2 2 2 1 0 2 1 2 0 0 0 The logic symbols of these three inverters are given in Fig. 1. (a) (b) (c) Fig.1 Ternary Inverter symbols (a) STI. (b) NTI (c) PTI A. Commutation Point of Inverters The commutation voltage Vc is prime aspect in proper design of ternary inverters which works as a switching element. The commutation point is deciding the threshold of switching activity of the inverter. The sizing of NMOS & PMOS devices has a strong influence on the commutation point Vc. The commutation voltage of an inverter can be given as, 𝑽𝒄 = 𝑲.𝑽 𝑻𝑵 + 𝑽 𝑫𝑫− 𝑽 𝑷𝑷 𝟏+𝑲 (2) Where K = � µn Wn Ln µp Wp Lp 𝝁 𝒏 - mobility of electron (600 V.cm-2 ) 𝝁 𝒑 - mobility of holes (270 V. cm-2 ) 𝑾𝒏 - n-channel MOS width ( in µm) 𝑳𝒏 - n- channel MOS lencth ( in μm) 𝑾𝒑 - p channel MOS width ( in µm) Lp - p channel MOS length ( in µm) 𝑽 𝑫𝑫 - supply voltage (1.0V) 𝑽 𝑻𝑵 - Threshold voltage of n-channel device. VTP - threshold voltage of p-channel device For the proposed designs of STI, NTI & PTI, the appropriate values of W/L based on equation (2) are used. The commutation points of the inverters can observe on the respective transfer characteristics. B. Design of STI, NTI & PTI MOS implementation of STI is described in [13, 14]. In traditional design of simple ternary inverter (STI), positive ternary inverter (PTI), negative ternary inverter (NTI) use a pass transistors/CMOS transmission gate at its output is done by using dual supply voltage. Alternative new implementation of these three inverters is shown in Fig. 2. The designs using single supply voltage & without using the transmission gate or pass transistors leads to a significant reduction in the power dissipation as well as in propagation delays. Fig 2. Schematic of CMOS STI, NTI & PTI. Transistor T1 is enhancement PMOS & transistor T2 are enhancement NMOS. The schematic for STI, NTI & PTI is same but with the variation in width and length parameter of each. Fig. 3 shows design layout of a Simple Ternary Inverter (STI) implemented using a PMOS transistor & NMOS transistor with Logic 2 at VDD, Logic 0 at GND (0 V) & logic 1 is a middle voltage between VDD & GND. The resistance of channels can be change by changing the length-to-width ratio of the PMOS and NMOS transistors. Thus, the length-to-width ratio can be effectively used to change the resistance of transistors as per the design requirement [8] [9].
- 3. Fig.3. Layout of Standard Ternary Inverter (STI) The set of ternary inverters and logic gates like TNAND (Ternary NAND) and TNOR (Ternary NOR) can be used to realize the complex ternary functions The circuit operation of this STI is simulated and analyzed using Microwind design and simulation tool. Fig. 7 shows the output Voltage Vs Time characteristics and Fig. 8 shows the transfer characteristics of STI. Table II gives the logic level voltages for inputs and outputs of ternary inverters. TABLE II. STI LOGIC LEVEL VOLTAGE Logic Value Voltage Level I/p (V) Voltage Level O/p (V) 0 0 1.0 1 0.5 0.51 2 1.0 0 The power dissipation and the transition time of output voltage signal are observed to be very small as specified in result section. IV. DESIGN OF TERNARY NAND GATE A TNAND function gives the inversion of the minimum value of the input signal where input signal belongs to 0, 1 and 2 or -1, 0 & +1 in balance ternary [1]. The NAND output can be defined as, Y= INV [ Min (I1,I2,I3…...In) ] (3) The truth table of the function is given in Table III. The CMOS design of proposed TNAND based on single supply voltage is shown in Fig. 4. The results of the design are simulated using Microwind. The transient characteristic of TNAND is shown Fig 10 for Voltage Vs Time by applying different input logic levels. Fig.4. Proposed NAND with Standard Ternary logic TABLE III: TERNARY NAND TRUTH TABLE. V. DESIGN OF TERNARY NOR GATE A TNOR o/p function gives the inversion of the maximum value of the input signal [1]. Thus the NOR output can be defined as, Y= INV [ Max (I1,I2,I3…...In) ] (4) TABLE IV TERNARY NOR TRUTH TABLE Input A Input B O/P TNOR 0 0 2 0 1 1 0 2 0 1 0 1 1 1 1 1 2 0 2 0 0 2 1 0 2 2 0 Ternary NOR gate con be implemented with the same analogy as that of TNAND. Input A Input B O/P TNAND 0 0 2 0 1 2 0 2 2 1 0 2 1 1 1 1 2 1 2 0 2 2 1 1 2 2 0
- 4. VI. DESIGN OF TAND & TOR GATES The basic elements of ternary logic family are STI, TNAND & TNOR. By using these gates we can further implement TAND, TOR. The implementation is shown with logic symbol in Fig. 6. The logic gates like TEXOR and TXNOR can also be implemented using this basic gate. In multi valued logic, AND is basically a MIN function and OR is a MAX function[1], which are specified in equation (5) and in equation (6) respectively. TAND Output Y= MIN [I1,I2,I3…...In] (5) TOR Output Y= MAX [I1,I2,I3…...In] (6) TAND gate and TOR gates can be implemented by inverting the outputs of TNAND & TNOR respectively by using the STI. a) TAND & TOR from TNAND & TNOR b) Symbol of TAND & TOR gate Fig. 6. Logic symbol for TAND & TOR In the design of TAND & TOR, the STI, proposed in this work is used for the inversion at the output of TNAND & TNOR. As the STI is designed without using transmission gate/ pass transistor, it effectively reduces the component count in the design of TAND & TOR gates. Operation of these designs is verified & analyzed. Fig 11 shows the verification of output of TAND for different logic levels at the input. VII. RESULTS & DISCUSSIONS A. Simulation & verification of outputs The proposed ternary logic gates are design & their performance is simulated for 45 nm technology using Microwind EDA tool. Fig.7 shows the transient characteristic and Fig. 8 shows the transfer characteristic of proposed STI. The outputs for NTI and PTI are observed as per the truth tables and are shown with their transient characteristics in Fig. 9 and in Fig. 10 respectively. The truth tables of ternary NAND & ternary AND are verified by applying all logic level combinations at the inputs. The corresponding input and output characteristics are shown in Fig 11 for ternary NAND gate and in Fig 12 for ternary AND gate. Fig 7.Transient characteristic for STI Fig 8. Transfer characeristic of STI Fig.9. Transient characteristic of NTI Fig.10. Transient characteristic of PTI
- 5. Fig.11. Transient Characteristic of TNAND. Fig.12. Output Voltage Vs Time Characteristic of TAND. B. Power Dissipation The power dissipation P depends on three main factors capacitance C, the supply voltage VDD and the clock frequency f. For a CMOS inverter, equation (7) below, shows a linear dependence of the power dissipation on these three factors. P= 1 2 C V2 DD f (7) Where C - output load capacitance (Farad) VDD - supply voltage (V) f - clock frequency (HZ) The average power dissipation of these ternary gates are calculated for the maximum output voltage swing. The designs are proposed with the minimum transistor count thereby reducing the overall power dissipation and reducing the transition times. Table V shows the average power dissipation over 500 ns time scale associated with the respective logic gate. TABLE V. POWER DISSIPATION Gate Power Dissipation STI 0.065 µW TNAND 0.191 mW TAND 0.213 mW Some of the results for power dissipation are compared with the available results of previous designs & summarized in following table VI. TABLE VI: COMPARISON OF POWER DISSIPATION OF STI Ref [6] Ref [14] Ref [12] Proposed Work 2.56 mw 0.7 µw 1.9 µw 0.065 µw C. Rise time & Fall time The rise time & fall time is mainly contributing to the propagation delay of the logic gate. The proposed designs are simulated to obtain rise time and fall time for various switching transitions. The rise times and fall times of STI are given in table VII TABLE VII. RISE TIME & FALL TIME OF STI O/p Transition Rise Time/Fall Time (ps) 1- 2 0.9 2 -1 1.1 1- 0 0.9 0 - 1 1.2 2 - 0 1.6 As the inverter is considered to be the basic switching element in any design, the transition time of STI is considered to be reference is observed to be very small. CONCLUSION Most of the traditional designs are based on ternary logic, which requires dual power supply. Similarly for the design of inverter as a basic switching element, the transmission gates/ transistors are used to pull the output at specific required voltage level. In the proposed designs, these output transmission gates/pull up transistors is eliminated from the inverters, thereby reducing the component count. Similarly use of single power supply to implement the ternary logic gates has lead to significant reductions in the overall power dissipation and improving the transition time. The proposed logic gates are useful further to design the low power ternary circuits. Considering the various advantages of the multi valued logic, the appropriate design of the MVL logic gates is important so that it will lead to the further development and its applications in this area.
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