A dynamically reconfigurable multi asip architecture for multistandard and multimode turbo decoding
0 likes170 views
This document presents a design for a dynamically reconfigurable multiprocessor architecture for turbo decoding, aimed at improving flexibility and throughput for multistandard wireless communication. The proposed architecture enhances existing systems by offering fast reconfiguration while maintaining decoding performance, addressing issues in latency and scalability. It includes advanced features like a bus-based communication infrastructure and adaptable ring buses for efficient configuration management.
A dynamically reconfigurable multi asip architecture for multistandard and multimode turbo decoding
- 1. The Master of IEEE Projects Copyright © 2016LeMenizInfotech. All rights reserved LeMenizInfotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web :www.lemenizinfotech.com/ www.ieeemaster.com Mail : projects@lemenizinfotech.com A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding Abstract: The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. Enhancement of the project: Increase no of ASIP in the configurable UDec system architecture. Existing System: The FlexiTreP ASIP supports both SBTC and DBTC for various standards and it is configured through an interleaver memory, a program memory, and the dynamically reconfigurable channel code control. a reconfigurable multiprocessor approach in order to decode multiple data streams in parallel was proposed. However, the configuration process of the platform is not described. A mixed XML/SystemC simulation model of the platform has been implemented to reach a maximum throughput of 86 Mb/s, which does not satisfy the throughput requirement of recent communication standards. Furthermore, the latency aspect and the scalability of the configuration process for a higher number of processing elements (PEs) are not discussed. In fact, previous works provide an efficient way to reach the high-performance requirement of emerging standards. However, the dynamic reconfiguration aspect of these platforms is superficially addressed. Among the few works that consider this issue, we can cite the recent architecture presented, where solutions for the reconfiguration management of the NoC-based multiprocessor turbo/low-density parity-check (LDPC) decoder architecture presented in were
- 2. The Master of IEEE Projects Copyright © 2016LeMenizInfotech. All rights reserved LeMenizInfotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web :www.lemenizinfotech.com/ www.ieeemaster.com Mail : projects@lemenizinfotech.com proposed. Up to 35 PEs and up to 8 configuration buses have been implemented. However, the proposed solution does not guarantee that the configuration process can be masked by the current decoding task. Then, stopping the current processing to configure the new configuration is unavoidable and leads to a decoding quality loss in terms of BER. To leverage these issues, this brief presents a novel dynamically reconfigurable turbo decoder providing an efficient and high- speed configuration process. Disadvantages: Performance is low Proposed System: The proposed dynamic reconfigurable UDec turbo decoder architecture is shown in Fig. 1. It consists of two rows of RDecASIPs interconnected via two butterfly topology network on chip (NoCs). Each row corresponds to a component decoder. In the example of Fig. 1, four ASIPs are organized in two component decoders, respectively, built with two ASIPs. Within each component decoder, the ASIPs are connected by two 44-bit buses for boundary state metrics exchange (not shown in Fig. 1). The RDecASIP implements the Max-Log-MAP algorithm. It supports both single and double binary convolutional TCs. Moreover, sliding window technique is used. Large frames are processed by dividing the frame into N windows, each with a maximum size of 64 symbols. Each ASIP can manage a maximum of 12 windows. Each ASIP can be configured through a 26 × 12 configuration memory. The configuration memory contains all parameters required to perform the initialization of the ASIP. Since the RDecASIP is designed to work in a multi-ASIP architecture as described, it requires several parameters to deal with a subblock of the data frame and several parameters to configure the ASIP mode.
- 3. The Master of IEEE Projects Copyright © 2016LeMenizInfotech. All rights reserved LeMenizInfotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web :www.lemenizinfotech.com/ www.ieeemaster.com Mail : projects@lemenizinfotech.com Fig. 1. Reconfigurable UDec system architecture example with four ASIPs The platform is dynamically configured through a dedicated bus-based communication infrastructure shown in Fig. 1 that consists in a pipeline unidirectional bus implementing incremental burst, multicast, and broadcast mechanisms. It can be split in three functional blocks: 1) master interface (MI); 2) slave interface (SI); and 3) selector. Each configuration memory is connected to the bus through an SI. The configuration manager deals with the configuration generation that is based on internal decisions and external information and commands. FLEXIBLE UDEC ARCHITECTURE This section presents the techniques that we propose in order to increase the dynamic configuration ability of the UDec architecture Ring Buses Adaptation
- 4. The Master of IEEE Projects Copyright © 2016LeMenizInfotech. All rights reserved LeMenizInfotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web :www.lemenizinfotech.com/ www.ieeemaster.com Mail : projects@lemenizinfotech.com The ring buses consist of direct connections between the ASIPs allowing exchanging boundary state metrics. So, when the number and the location of the selected ASIPs dynamically evolve, the loop connections between the last and the first selected ASIPs have to be adapted. Fig. 2 shows different examples of the ring buses adaptation when four ASIPs are implemented in each component decoder. Fig. 2(a) shows the case where two ASIPs are selected to perform the decoding task. The location of the first ASIP has been shifted from RDecASIP 0 to RDecASIP 1. Fig. 2(b) shows the case where three ASIPs are selected and the location of the first ASIP has been shifted from RDecASIP 0 to RDecASIP 2. In this case, the last ASIP of the component decoder is the RDecASIP 0, and the RDecASIP 1 has to be bypassed. Fig. 2. Ring buses dynamic adaptation examples and architecture. (a) Two selected ASIPs. (b) Three selected ASIPs. (c) Flexible architecture illustrated for one ring bus. Butterfly Topology NoCs Adaptation
- 5. The Master of IEEE Projects Copyright © 2016LeMenizInfotech. All rights reserved LeMenizInfotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web :www.lemenizinfotech.com/ www.ieeemaster.com Mail : projects@lemenizinfotech.com The extrinsic information transfers through the NoC are also impacted when the location of the selected ASIPs changes dynamically. Indeed, the routing information for the transfer is computed by the network interface associated with each ASIP depending on a global address of the symbol generated by the ASIP. Fig. 3 illustrates the routing principle for the considered butterfly topology NoC. Fig. 3. Butterfly topology routing principle. Advantages: high performances Software implementation: Modelsim Xilinx ISE