A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates
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This document presents a novel design for a 4-bit Johnson counter using reversible logic gates, highlighting the benefits of reversible circuits in reducing power dissipation and enhancing efficiency in quantum computing applications. The authors introduce key concepts such as quantum cost, garbage output, and the functioning of reversible gates relevant to their proposed design. Additionally, the paper discusses the implementation details, resulting parameters, and emphasizes the potential impact of their design on various technological fields.
![IJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 08, 2014 | ISSN (online): 2321-0613
All rights reserved by www.ijsrd.com 119
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates
Heranmoy Maity1
Abhijit Dey2
Shashank Kumar Singh3
1,2,3
Department of Electronics and Communication Engineering
1,2,3
NSHM Knowledge Campus, Durgapur, India
Abstract— In recent years, reversible logic circuits have
attracted considerable attention in improving some fields
like nanotechnology, quantum computing, cryptography,
optical computing and low power design of circuits due to
its low power dissipating characteristic. In this paper we
proposed the design of 4-bit Johnson counter which uses
reversible gates and derived quantum cost, constant inputs,
garbage output and number of gates to implement it.
Keywords: Reversible logic, Quantum cost, Constant input,
Garbage output, Johnson Counter, Quantum computing
I. INTRODUCTION
Landauer states that the loss of one bit of information
dissipates KTln2 joules of energy, where K is the
Boltzmann constant and T is the absolute temperature at
which the operation is performed [1]. At room temperature
the heat dissipation due to loss of one bit of information is
very small but not negligible. This computation procedure is
irreversible. Further Bennett, showed that one can avoid
KTln2 joules of energy dissipation from the circuit if input
can be extracted from output and it would be possible if and
only if reversible gates are used [2]. Research is going on in
the field of reversible logic and a good amount of research
work has been carried out in the area of reversible
combinational logic. However, there is not much work in the
area of sequential circuit like flip-flops and counters. A
counter, by function, is a sequential circuit consisting a set
of flip-flops connected in a suitable manner to count the
sequence of the input pulses presented to it in digital
form.[10] This paper proposes a novel design of 4-bit
Johnson or Shift counter using reversible gates.
II. BASIC CONCEPTS
This section explains some basic concepts of reversible
gates and quantum circuits which are as follows:
A. Reversible logic Function
It is an n-input n-output logic function in which there is a
one-to-one correspondence between the inputs and the
outputs, i.e. not only the outputs can be uniquely determined
from the inputs, but also the inputs can be recovered from
the outputs.[6] This prevents the loss of information which
is the root cause of power dissipation in irreversible logic
circuits. Energy dissipation can be reduced or even
eliminated if computation becomes Information-lossless.
The reversible logic circuits must be constructed under two
main constraints. They are:
Fan-out is not permitted.
Loops or feedbacks are not permitted
Quantum logic gates have some properties as shown in
“(1.1).”
}…… (1.1)
Any reversible logic gate (circuit) is realized by using
mentioned gates above, NOT and FG gates. The properties
above show that when two V gates are in series they will
behave as a NOT gate. Similarly, two V+
gates in series also
function as a NOT gate. A V gate in series with V+
gate, and
vice versa, is an identity.
B. Garbage output
This refers to the number of unused outputs present in a
reversible logic. A garbage output is an output that is needed
to change an irreversible gate to a reversible one and are not
used to the input to the other gates
C. Quantum gate
Quantum gates are reversible and based on quantum
computing. For realizing 1×1 and 2×2 quantum gates we can
use quantum technique. Since bigger quantum gates like
3×3, 4x4 etc. cannot be realized by quantum technique
directly, 1×1 and 2×2 quantum gates are used for realizing
this bigger quantum gates.
D. Quantum Cost
This refers to the cost of the circuit in terms of the cost of a
primitive gate. The quantum cost of a reversible gate is the
number of 1x1 and 2x2 reversible gates or quantum gates
required in its design. The quantum costs of all reversible
1x1 and 2x2 gates are taken as unity. Since every reversible
gate is a combination of 1 x 1 or 2 x 2 quantum gate, so the
quantum cost of a reversible gate can be calculated by
counting the numbers of NOT, Controlled-V, Controlled-V+
and CNOT gates used.[3],[14]
E. Reversible gate
A gate with equal number of input and output in which input
and output have one –to-one mapping. This helps to
determine the outputs from the inputs and also the inputs
can be uniquely recovered from the outputs. If the input
vector of a reversible gate is denoted by IV= (I1,I2,I3,…,IK),
the output vector can be represented as OV=
(O1,O2,O3,…,OK). A reversible gate can be represented as
K×K in which the number of input and output is K.
F. Feynman gate (cnot gate)
The Feynman gate (FG) or the Controlled-NOT gate
(CNOT) is a 2-input 2- output reversible gate having the
mapping (A, B) to (P = A, Q = A⊕B) where A, B are the
inputs and P, Q are the outputs, respectively.[5]. Since it is a
2×2 gate, it has a quantum cost of 1. “Fig. 1” and “Fig. 2”
shows the block diagram and quantum representation of the
Feynman gate. “Fig. 3” and “Fig. 4”
shows the block diagram and quantum representation of
Double Feynman Gate respectively. Quantum cost of DFG
is 2 as it needs two CNOT gate to implement it.
Fig. 1: 2X2 Feynman](https://image.slidesharecdn.com/ijsrdv2i8102-150923084517-lva1-app6891/85/A-Novel-Design-of-4-Bit-Johnson-Counter-Using-Reversible-Logic-Gates-1-320.jpg)
![A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates
(IJSRD/Vol. 2/Issue 08/2014/028)
All rights reserved by www.ijsrd.com 120
Fig. 2: Quantum representation of Feynman
Fig. 3: Double Feynman Gate
Fig. 4: Quantum Representation of DFG
G. SAM Gate
Input vector Iv and Output vector Ov are represented as
Iv=(A,B,C) and Ov= ̅ ̅ ̅ ̅
and respectively. The block diagram of 3x3 SAM gate is
shown in “Fig. 5” and its quantum representation is shown
in “Fig. 6”. The quantum cost of SAM gate is 4. [4],[9]
Fig. 5: Block diagram of 3x3 SAM Gate
Fig. 6: Quantum representation of SAM gate.
If we give 0 to 3rd
input then we get NOT of 1st
input in 1st
output, OR of 1st
and 2nd
inputs in 2nd
output and
AND of 1st
and 2nd
inputs in 3rd
output. This operation is
shown in “Fig. 7”. So this gate can be used as two input
universal gate.
Fig. 7: SAM as NOT, OR and AND.
The Characteristic equation of D Flip-Flop is
̅̅̅̅̅̅ “Fig. 8” shows the D flip-flop
implementation by using SAM and DFG gate. Quantum cost
of this D Flip-Flop implementation is 6.[7]-[8][11]-[13]
Fig. 8: D Flip-Flop
III. PROPOSED WORK
A. Johnson Counter
The shift or Johnson counter is constructed by connecting
the inverted output of the last flip-flop to the input of the
first flip-flop. The truth table given in Table-I, one can
observe that, for a 4-bit Johnson counter, there are 8-states.
In general, an n-flip-flop shift counter will result in 2n states
or Modulo-2n counter.
CLK Q1 Q2 Q3 Q4
0 0 0 0 0
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
1 1 1 1 1
1 0 1 1 1
1 0 0 1 1
1 0 0 0 1
1 0 0 0 0
Table 1: Truth table of 4-bit Johnson counter
B. Proposed Design of Johnson Counter
“Fig. 9” shows the proposed design of Johnson counter
using SAM and DFG gate
Fig. 9: Proposed Design of Johnson Counter
IV. RESULTS AND DISCUSSION
In the implementation of 4-bit Johnson counter we use four
SAM gate having Quantum cost (QC) of 4 and four DFG
gate having Quantum cost =2. Number of gates, constant](https://image.slidesharecdn.com/ijsrdv2i8102-150923084517-lva1-app6891/85/A-Novel-Design-of-4-Bit-Johnson-Counter-Using-Reversible-Logic-Gates-2-320.jpg)
![A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates
(IJSRD/Vol. 2/Issue 08/2014/028)
All rights reserved by www.ijsrd.com 121
inputs, garbage output and quantum cost are shown in
Table-II.
No of Gates No. of
constant
input
No. of
garbage
output
Quantum
cost
8 8 4 24
Table 2
V. CONCLUSION
We have presented the basic concepts of multipurpose
binary reversible gates. Such gates can be used in regular
circuits realizing Boolean functions. This paper proposes
designs of basic reversible sequential elements such as flip-
flops and four bit reversible Johnson or Shift Counter. In
this paper, we implement a Johnson counter design directly
from reversible gates. Minimization of Quantum cost,
garbage output and number of gate is a challenging one.
Here in this paper the proposed designs are better in terms of
quantum cost and garbage outputs. The proposed design can
have great impact in quantum computing. The proposed
synchronous counter designs have the applications in
building reversible ALU, nanotechnology, low power circuit
design, cryptography, optical computing etc.
REFERENCES
[1] Landauer, R., “Irreversibility and heat generation in
the computing process”, IBM J. Research and
Development, vol. 5, pp. 183-191, 1961.
[2] C.H. Bennett, “Logical Reversibility of
Computation”, IBM J. Research and Development,
vol. 17, pp. 525-532, November 1973.
[3] J.E Rice, "A New Look at Reversible Memory
Elements", Proceedings International Symposium on
Circuits and Systems (ISCAS) 2006, Kos, Greece,
May 21-24 ,2006, pp. 243-246.
[4] Md. SelimAl Mamun and Syed Monowar Hossain.
"Design of Reversible Random Access Memory."
International Journal of Computer Applications 56.15
(2012): 18-23.
[5] R. Feynman, “Quantum Mechanical Computers,”
Optics News, Vol.11, pp. 11–20, 1985.
[6] Perkowski, M., A.Al-Rabadi, P. Kerntopf, A. Buller,
M. Chrzanowska-Jeske, A. Mishchenko, M. Azad
Khan, A. Coppola, S. Yanushkevich,V. Shmerko and
L. Jozwiak, “A general decomposition for reversible
logic”, Proc. RM’2001, Starkville, pp: 119-138, 2001
[7] M.-L.Chuang and C.-Y. Wang, “Synthesis of
reversible sequential elements,” ACM journal of
Engineering Technologies in Computing Systems
(JETC). Vol. 3, No.4, 1–19, 2008.
[8] Lafifa Jamal, Farah Sharmin, Md. Abdul Mottalib
and Hafiz Md. Hasan Babu, Design and Minimization
of Reversible Circuits for a Data Acquisition and
Storage System, International Journal of Engineering
and Technology Volume 2 No. 1, January, 2012.
[9] Md. Selim Al Mamun and David Menville, Quantum
Cost Optimization for Reversible Sequential Circuit,
(IJACSA) International Journal of Advanced
Computer Science and Applications, Vol. 4, No. 12,
2013.
[10]Shashank K. Singh, H. Maity and A. Dey,”A novel
design of MOD-8 synchronous UP/DOWN counter
using Reversible gate”, International Journal of
Sceintific Research And Education, Vol. 2, Issue 9,
pp. 1968-1976, sept. 2014.
[11]H. Thapliyal and A. P. Vinod, “Design of reversible
sequential elements with feasibility of transistor
implementation” In Proc. the 2007 IEEE Intl. Symp.
On Cir.and Sys., pages 625–628, 2007.
[12]J. E. Rice, An introduction to reversible latches. The
Computer journal,Vol. 51, No.6, 700–709. 2008.
[13]M.S.A.Mamun and B. K. Karmaker,” Design of
Reversible Counter” International Journal of
Advanced Computer Science and Applications
(IJACSA),Vol. 5, No. 1, 2014
[14]Himanshu Thapliyal and Nagarajan Ranganathan,
Design of Reversible Sequential Circuits Optimizing
Quantum Cost, Delay, and Garbage Outputs, ACM
Journal on Emerging Technologies in Computer
Systems, Vol. 6,No. 4,Article 14, 2010.](https://image.slidesharecdn.com/ijsrdv2i8102-150923084517-lva1-app6891/85/A-Novel-Design-of-4-Bit-Johnson-Counter-Using-Reversible-Logic-Gates-3-320.jpg)
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates
- 1. IJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 08, 2014 | ISSN (online): 2321-0613 All rights reserved by www.ijsrd.com 119 A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates Heranmoy Maity1 Abhijit Dey2 Shashank Kumar Singh3 1,2,3 Department of Electronics and Communication Engineering 1,2,3 NSHM Knowledge Campus, Durgapur, India Abstract— In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it. Keywords: Reversible logic, Quantum cost, Constant input, Garbage output, Johnson Counter, Quantum computing I. INTRODUCTION Landauer states that the loss of one bit of information dissipates KTln2 joules of energy, where K is the Boltzmann constant and T is the absolute temperature at which the operation is performed [1]. At room temperature the heat dissipation due to loss of one bit of information is very small but not negligible. This computation procedure is irreversible. Further Bennett, showed that one can avoid KTln2 joules of energy dissipation from the circuit if input can be extracted from output and it would be possible if and only if reversible gates are used [2]. Research is going on in the field of reversible logic and a good amount of research work has been carried out in the area of reversible combinational logic. However, there is not much work in the area of sequential circuit like flip-flops and counters. A counter, by function, is a sequential circuit consisting a set of flip-flops connected in a suitable manner to count the sequence of the input pulses presented to it in digital form.[10] This paper proposes a novel design of 4-bit Johnson or Shift counter using reversible gates. II. BASIC CONCEPTS This section explains some basic concepts of reversible gates and quantum circuits which are as follows: A. Reversible logic Function It is an n-input n-output logic function in which there is a one-to-one correspondence between the inputs and the outputs, i.e. not only the outputs can be uniquely determined from the inputs, but also the inputs can be recovered from the outputs.[6] This prevents the loss of information which is the root cause of power dissipation in irreversible logic circuits. Energy dissipation can be reduced or even eliminated if computation becomes Information-lossless. The reversible logic circuits must be constructed under two main constraints. They are: Fan-out is not permitted. Loops or feedbacks are not permitted Quantum logic gates have some properties as shown in “(1.1).” }…… (1.1) Any reversible logic gate (circuit) is realized by using mentioned gates above, NOT and FG gates. The properties above show that when two V gates are in series they will behave as a NOT gate. Similarly, two V+ gates in series also function as a NOT gate. A V gate in series with V+ gate, and vice versa, is an identity. B. Garbage output This refers to the number of unused outputs present in a reversible logic. A garbage output is an output that is needed to change an irreversible gate to a reversible one and are not used to the input to the other gates C. Quantum gate Quantum gates are reversible and based on quantum computing. For realizing 1×1 and 2×2 quantum gates we can use quantum technique. Since bigger quantum gates like 3×3, 4x4 etc. cannot be realized by quantum technique directly, 1×1 and 2×2 quantum gates are used for realizing this bigger quantum gates. D. Quantum Cost This refers to the cost of the circuit in terms of the cost of a primitive gate. The quantum cost of a reversible gate is the number of 1x1 and 2x2 reversible gates or quantum gates required in its design. The quantum costs of all reversible 1x1 and 2x2 gates are taken as unity. Since every reversible gate is a combination of 1 x 1 or 2 x 2 quantum gate, so the quantum cost of a reversible gate can be calculated by counting the numbers of NOT, Controlled-V, Controlled-V+ and CNOT gates used.[3],[14] E. Reversible gate A gate with equal number of input and output in which input and output have one –to-one mapping. This helps to determine the outputs from the inputs and also the inputs can be uniquely recovered from the outputs. If the input vector of a reversible gate is denoted by IV= (I1,I2,I3,…,IK), the output vector can be represented as OV= (O1,O2,O3,…,OK). A reversible gate can be represented as K×K in which the number of input and output is K. F. Feynman gate (cnot gate) The Feynman gate (FG) or the Controlled-NOT gate (CNOT) is a 2-input 2- output reversible gate having the mapping (A, B) to (P = A, Q = A⊕B) where A, B are the inputs and P, Q are the outputs, respectively.[5]. Since it is a 2×2 gate, it has a quantum cost of 1. “Fig. 1” and “Fig. 2” shows the block diagram and quantum representation of the Feynman gate. “Fig. 3” and “Fig. 4” shows the block diagram and quantum representation of Double Feynman Gate respectively. Quantum cost of DFG is 2 as it needs two CNOT gate to implement it. Fig. 1: 2X2 Feynman
- 2. A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates (IJSRD/Vol. 2/Issue 08/2014/028) All rights reserved by www.ijsrd.com 120 Fig. 2: Quantum representation of Feynman Fig. 3: Double Feynman Gate Fig. 4: Quantum Representation of DFG G. SAM Gate Input vector Iv and Output vector Ov are represented as Iv=(A,B,C) and Ov= ̅ ̅ ̅ ̅ and respectively. The block diagram of 3x3 SAM gate is shown in “Fig. 5” and its quantum representation is shown in “Fig. 6”. The quantum cost of SAM gate is 4. [4],[9] Fig. 5: Block diagram of 3x3 SAM Gate Fig. 6: Quantum representation of SAM gate. If we give 0 to 3rd input then we get NOT of 1st input in 1st output, OR of 1st and 2nd inputs in 2nd output and AND of 1st and 2nd inputs in 3rd output. This operation is shown in “Fig. 7”. So this gate can be used as two input universal gate. Fig. 7: SAM as NOT, OR and AND. The Characteristic equation of D Flip-Flop is ̅̅̅̅̅̅ “Fig. 8” shows the D flip-flop implementation by using SAM and DFG gate. Quantum cost of this D Flip-Flop implementation is 6.[7]-[8][11]-[13] Fig. 8: D Flip-Flop III. PROPOSED WORK A. Johnson Counter The shift or Johnson counter is constructed by connecting the inverted output of the last flip-flop to the input of the first flip-flop. The truth table given in Table-I, one can observe that, for a 4-bit Johnson counter, there are 8-states. In general, an n-flip-flop shift counter will result in 2n states or Modulo-2n counter. CLK Q1 Q2 Q3 Q4 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 Table 1: Truth table of 4-bit Johnson counter B. Proposed Design of Johnson Counter “Fig. 9” shows the proposed design of Johnson counter using SAM and DFG gate Fig. 9: Proposed Design of Johnson Counter IV. RESULTS AND DISCUSSION In the implementation of 4-bit Johnson counter we use four SAM gate having Quantum cost (QC) of 4 and four DFG gate having Quantum cost =2. Number of gates, constant
- 3. A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates (IJSRD/Vol. 2/Issue 08/2014/028) All rights reserved by www.ijsrd.com 121 inputs, garbage output and quantum cost are shown in Table-II. No of Gates No. of constant input No. of garbage output Quantum cost 8 8 4 24 Table 2 V. CONCLUSION We have presented the basic concepts of multipurpose binary reversible gates. Such gates can be used in regular circuits realizing Boolean functions. This paper proposes designs of basic reversible sequential elements such as flip- flops and four bit reversible Johnson or Shift Counter. In this paper, we implement a Johnson counter design directly from reversible gates. Minimization of Quantum cost, garbage output and number of gate is a challenging one. Here in this paper the proposed designs are better in terms of quantum cost and garbage outputs. The proposed design can have great impact in quantum computing. The proposed synchronous counter designs have the applications in building reversible ALU, nanotechnology, low power circuit design, cryptography, optical computing etc. REFERENCES [1] Landauer, R., “Irreversibility and heat generation in the computing process”, IBM J. Research and Development, vol. 5, pp. 183-191, 1961. [2] C.H. Bennett, “Logical Reversibility of Computation”, IBM J. Research and Development, vol. 17, pp. 525-532, November 1973. [3] J.E Rice, "A New Look at Reversible Memory Elements", Proceedings International Symposium on Circuits and Systems (ISCAS) 2006, Kos, Greece, May 21-24 ,2006, pp. 243-246. [4] Md. SelimAl Mamun and Syed Monowar Hossain. "Design of Reversible Random Access Memory." International Journal of Computer Applications 56.15 (2012): 18-23. [5] R. Feynman, “Quantum Mechanical Computers,” Optics News, Vol.11, pp. 11–20, 1985. [6] Perkowski, M., A.Al-Rabadi, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, M. Azad Khan, A. Coppola, S. Yanushkevich,V. Shmerko and L. Jozwiak, “A general decomposition for reversible logic”, Proc. RM’2001, Starkville, pp: 119-138, 2001 [7] M.-L.Chuang and C.-Y. Wang, “Synthesis of reversible sequential elements,” ACM journal of Engineering Technologies in Computing Systems (JETC). Vol. 3, No.4, 1–19, 2008. [8] Lafifa Jamal, Farah Sharmin, Md. Abdul Mottalib and Hafiz Md. Hasan Babu, Design and Minimization of Reversible Circuits for a Data Acquisition and Storage System, International Journal of Engineering and Technology Volume 2 No. 1, January, 2012. [9] Md. Selim Al Mamun and David Menville, Quantum Cost Optimization for Reversible Sequential Circuit, (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 4, No. 12, 2013. [10]Shashank K. Singh, H. Maity and A. Dey,”A novel design of MOD-8 synchronous UP/DOWN counter using Reversible gate”, International Journal of Sceintific Research And Education, Vol. 2, Issue 9, pp. 1968-1976, sept. 2014. [11]H. Thapliyal and A. P. Vinod, “Design of reversible sequential elements with feasibility of transistor implementation” In Proc. the 2007 IEEE Intl. Symp. On Cir.and Sys., pages 625–628, 2007. [12]J. E. Rice, An introduction to reversible latches. The Computer journal,Vol. 51, No.6, 700–709. 2008. [13]M.S.A.Mamun and B. K. Karmaker,” Design of Reversible Counter” International Journal of Advanced Computer Science and Applications (IJACSA),Vol. 5, No. 1, 2014 [14]Himanshu Thapliyal and Nagarajan Ranganathan, Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay, and Garbage Outputs, ACM Journal on Emerging Technologies in Computer Systems, Vol. 6,No. 4,Article 14, 2010.