This document describes a hardware implementation of a stochastic SIR model on an FPGA board to provide faster simulation compared to software. A MATLAB simulation was used to test the algorithm. A MATLAB program was created to automatically generate Verilog code with customizable parameters. A 64-bit XOR feedback shift register random number generator was used. The Verilog code implementation was verified against MATLAB results and showed stable repeats. The FPGA implementation provided a 5000x speedup over software for a population of 120 individuals.