Advanced VLSI PPT 21EC71 Module 2.......
- 1. 21EC71:Advanced VLSI 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 1 Module 2: Floor planning, Placement & Routing Prof. Manjunath E Dept. of Electronics & Communication Engineering, Dr. T Thimmaiah Institute of Technology, Kolar Gold Fields
- 6. 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 6 2.1 Floor planning Goals & Objectives: Goals: 1. Arrange the blocks on a Chip 2. Decide the location of the I/O Pads 3. Decide the location and number of the power pads 4. Decide the type of power distribution 5. Decide the location and type of clock distribution Objectives: 1. Minimize the chip area 2. Minimize the delay
- 7. 2.2 Measurement of Delay in Floor planning 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 7
- 8. Worst Case Interconnect delay : 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 8
- 9. 2.3 Floor planning Tools: 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 9
- 11. 2.4 Channel Definition / Allocation: 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 11
- 13. Slicing Floor plan & Slicing tree: 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 13
- 15. Non Slicing Floor plan; Two solution is to 1. Move the blocks until we obtain a slicing floor plan. 2. The other solution is to allow the use of L -shaped, rather than rectangular, channels (or areas with fixed connectors 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 15
- 16. Channel Definition & Ordering : 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 16
- 18. 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 18 2.5 I/O and Power Planning :
- 20. 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 20 The Substrate connection employs a down bond to the carrier, we have several options
- 26. 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 26 Placement Algorithms: There are two classes of placement algorithms commonly used in commercial CAD tools: 1. constructive placement 2. Iterative placement improvement. A constructive placement method uses a set of rules to arrive at a constructed placement. The most commonly used methods are variations on the 1. Min-cut algorithm 2. Eigen Value Method
- 30. 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 30 Force Directed relaxation (b) Force directed pairwise relaxation (c)
- 33. 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 33 Routing Goals and Objectives: 1. The goal of global routing is to provide complete instructions to the detailed router on where to route every net. 2. The objectives of global routing are one or more of the following: • Minimize the total interconnect length. • Maximize the probability that the detailed router can complete the routing. • Minimize the critical path delay.
- 34. 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 34 Global routing methods: 1. Sequential routing: Each net in turn and calculates the shortest path suing tree algorithms- with the added restrictions of using the available channels. (each net (connection between pins or components) is processed one by one.) 2. Order independent routing: Routing each net, ignoring how crowded the channels are (This approach routes each net without considering the current occupancy or congestion of channels.) 3. Order Dependent: The routing is sequential, but the order of processing the nets are in order. • In order-dependent routing, the sequence in which nets are processed affects the final routing result. • The quality of routing can significantly vary depending on this order; thus, careful selection of the routing order is crucial. 4. Hierarchical Routing: The routing which handles all nets at a particular level at once. • This method is often more efficient for larger or complex designs since it divides the routing problem into manageable chunks, improving scalability and performance.
- 36. 21EC71 | Prof. MANJUNATH E., Dr. TTIT, KGF 36 Back Annotation: • once a circuit layout is completed, the actual lengths of interconnections and the parasitic of routing channels can be extracted and annotated back into the timing simulation. • This provides a more accurate picture of how the design will perform after fabrication. • It is a critical step for validating that the design meets the required specifications before moving on to manufacturing.