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ARCHITECTURE OF 80386 IN DETAIL SPPU COMPUTER ENGINEERING SEM 4

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The document provides an in-depth overview of the 80386 microprocessor, detailing its features, operating modes, architecture, and versions. It highlights the advancements of the 80386 over its predecessors, such as multitasking capabilities, memory protection, and various addressing modes. Additionally, it presents the programming model, including general-purpose and segment registers, as well as control registers and flags essential for programming with the 80386.

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1 Hope Foundation's International Institute of Information Technology, Pune Department of Computer Engineering Academic Year : 2024-25, Semester - II SUBJECT: MICROPROCESSOR CLASS: SE PREPAIRED BY SWATI D. JADHAV CONNECTSWATIJADHAV55@GMAIL.COM JANUARY 14, 2025
UNIT I INTRODUCTION TO 80386 (07 HOURS) • CO1: Exhibit skill of assembly language programming for the application. • CO2: Classify Processor architectures. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 2 JANUARY 14, 2025
OUTINE ● 80386 MICROPROCESSOR ● FEATURES OF 80386 ● OPERATING MODES OF 80386 ● ARCHITECTURE OF 80386 MICROPROCESSOR ● VERSIONS ● PROGRAMER MODELS ● OPERATING MODES ● ADDRESSING MODES ● DATA TYPES ● APPLICATION INSTRUCTION SETS CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 3 JANUARY 14, 2025
80386 MICROPROCESSOR • 80386 Microprocessor • A 32-bit processor • Holds the ability to carry out 32-bit operations in one cycle. • It has a data and address bus of 32-bit each. Thus has the ability to address 4 GB (or 232) of physical memory. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 4 JANUARY 14, 2025
KEY FEATURES • Multitasking internal dedicated hardware that permits multitasking. • Protection capability are the two key characteristics of the 80386 microprocessor. 80386 has CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 5 JANUARY 14, 2025
WHY 80386? • 8085 is a 8-bit microprocessor. • 8086 is a 16-bit microprocessor. • 80286 was an advancement of 8086 with some additional characteristics. • But with the advent of technology intel introduced a 32-bit microprocessor whose processing speed was twice that of the 80286 microprocessor. • This was an 80386 microprocessor that was designed by Intel in October 1985. • An upgraded version of the 80286 microprocessor. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 6 JANUARY 14, 2025
FEATURES OF 80386 ✔ 32-bit microprocessor. ✔ Has ALU 32-bit. ✔ Holds data bus of 32-bit. ✔ Address bus of 32 bit. ✔ Physical memory addressability of 4 GB ✔ Virtual memory addressability of 64 TB. ✔ Supports a variety of operating clock frequencies- 16 MHz, 20 MHz, 25 MHz, and 33 MHz. ✔ It offers 3 stage pipeline: 1. Fetch 2. Decode 3. Execute. ✔ As it supports simultaneous fetching, decoding, and execution inside the system. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 7 JANUARY 14, 2025
OPERATING MODES OF 80386 • 80286 supports two operating modes. 1.Real address mode 2.Protected virtual address mode. • 80386 supports 3 operating modes. 1.Real 2.Protected 3.Vrtual real mode. • Initially, the 80286 was booted in real mode. However, to have better operating performance, separate software command is used to switch from the real mode to the protected mode. • But it requires the resetting of the microprocessor in order to switch to real mode from protected mode. • This drawback is eliminated in 80386 that allows the switching between the modes using software commands. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 8 JANUARY 14, 2025
OPERATING MODES OF 80386 1. Protected mode: Operates in a similar way like 80286 but offers higher memory addressing ability. 2. Virtual mode: The overall memory of 80386 can be divided into various virtual machines. All of them acts as a separate computer with 8086 microprocessor. This mode is also called virtual 8086 mode or V86 mode. 3. Virtual real mode: This mode allows the system to execute multiple programs in the protected memory. In case a program at a particular memory gets crashed then it will not cause any adverse effect on the other part of the memory. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 9 JANUARY 14, 2025
ARCHITECTURE OF 80386 MICROPROCESSOR CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 10 5 2 3 4 1 JANUARY 14, 2025
ARCHITECTURE OF 80386 MICROPROCESSOR • Basically, it has 5 functional units which are as follows: 1. Bus Interface Unit 2. Code Fetch Unit 3. Instruction Decode Unit 4. Execution Unit 5. Memory Management Unit CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 11 JANUARY 14, 2025
1. BUS INTERFACE UNIT (BIU) CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 12 JANUARY 14, 2025
1. BUS INTERFACE UNIT (BIU) • BIU holds a 32-bit bidirectional data bus as well as a 32-bit address bus. • Whenever a need for instruction or a data fetch is generated by the system then the BIU generates signals (according to the priority) for activating the data and address bus in order to fetch the data from the desired address. • The BIU connects the peripheral devices through the memory unit. • Controls the interfacing of external buses with the coprocessors. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 13 JANUARY 14, 2025
2. CODE PRE-FETCH UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 14 JANUARY 14, 2025
2. CODE PREFETCH UNIT • The code Pre-fetch unit fetches that instruction from the memory and stores it in a 16-byte pre-fetch queue. • So to speed up the operation this unit fetches the instructions in advance and the queue stores these instructions. • The sequence in which the instructions are fetched and gets stored in the queue depends on the order they exist in the memory. • It is to be noted here that, code prefetching holds lower priority than data transferring. • As whenever a need for data transfer is generated by the system then immediately the code pre-fetcher leaves control over the buses. • So that the BIU can transfer the required data. • But prefetching of instruction and storing it in the queue reduces the wait for the upcoming instruction to almost zero. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 15 JANUARY 14, 2025
3. INSTRUCTION DECODE UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 16 JANUARY 14, 2025
3. INSTRUCTION DECODE UNIT • We know that instructions in the memory are stored in the form of bits. • So, this unit decodes the instructions stored in the prefetch queue. • Basically the decoder changes the machine language code into assembly language and transfers it to the processor for further execution. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 17 JANUARY 14, 2025
4. EXECUTION UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 18 JANUARY 14, 2025
4. EXECUTION UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 19 JANUARY 14, 2025
4. EXECUTION UNIT • The decoded instructions are stored in the decoded instruction queue. • So, these instructions are provided to the execution unit in order to execute the instructions. • The execution unit controls the execution of the decoded instructions. • This unit has a 32-bit ALU, that performs the operation over 32-bit data in one cycle. • Also, it consists of 8 general purpose as well as 8 special purpose registers. • These are used for data handling and calculation of offset address. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 20 JANUARY 14, 2025
5. MEMORY MANAGEMENT UNIT • This unit has two separate units within it. These are • A. Segmentation Unit and • B. Paging Unit CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 21 JANUARY 14, 2025
A. Segmentation unit CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 22 JANUARY 14, 2025
A. Segmentation unit CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 23 JANUARY 14, 2025
A. Segmentation unit • The segmentation unit plays a vital role in the 80836 microprocessor. It offers a protection mechanism in order to protect the code or data present in the memory from application programs. It gives 4 level protection to the data or code present in the memory. Every information in the memory is assigned a privilege level from PL0 to PL3. • Here, PL0 holds the highest priority and PL3 holds the lowest priority. • Suppose a file (either data or code) is needed to be accessed is stored in the memory at PL0. Then only those programs which are working at PL0 would be able to access that file. While other programs will not be able to access the same. Also, if a file is present at PL1, then programs of PL0 and PL1 both can access it. As PL0 has a higher priority than PL1. So, for protection purposes, the main part of the OS is stored in PL0 while PL3 holds the user programs. Providing protection to the data or code inside the system is the most advantageous factor that was first given by the 80386 microprocessor. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 24 JANUARY 14, 2025
B. PAGING UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 25 JANUARY 14, 2025
B. PAGING UNIT • The paging unit operates only in protected mode. • It changes the linear address into a physical address. • As the programmer only provides the virtual address and not the physical address. The segmentation unit controls the action of the paging unit, as the segmentation unit has the ability to convert the logical address into the linear address at the time of executing an instruction. • Basically, it changes the overall task map into pages and each page has a size of 4K. • This allows the handling of tasks in the form of pages rather than segments. • The paging unit supports multitasking. • This is so because the physical memory is not required to hold the whole segment of any task. Despite this, only that part of the segment which is needed to be currently executed must be stored in that memory whose physical address is calculated by the paging unit. This resultantly reduces the memory requirement and hence this frees the memory for other tasks. Thus by this we get an effective way for managing the memory to support multitasking. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 26 JANUARY 14, 2025
80386 VERSIONS • 1. 80386SX: The SX stands for single execution Holds a data bus of 16-bit. • 2. 80386DX: The DX stands for double execution Has a data bus of 32-bit. • Normally 80386 is 80386DX having 32-bit data bus. • But sometimes a system having an 8086 microprocessor needs to improve its performance as well as protection. And we know that 8086 is a 16-bit microprocessor, that operates on 2 banks. • 80386 in general has a 32-bit data bus that needs 4 banks. • To access some of the features of 80386 in a system having 8086 processor, we use 80386SX as a processor having a data bus of 16- bit. • Thus, in this case, a system can systembe upgraded to facilities of 80386 by simply changing the processor despite changing the overall . This is the reason why we have 80386SX version of the 80386 microprocessor. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 27 JANUARY 14, 2025
Programmers Model Includes the registers, flags, and segments that a programmer interacts with during coding. 1. General-Purpose Registers: EAX, EBX, ECX, EDX: 32-bit general-purpose registers used for various arithmetic, logical, and data manipulation operations. ESI, EDI: Used for source and destination addressing during string operations. EBP: Base pointer, used for stack frames in procedures. ESP: Stack pointer, points to the top of the stack. 1. Segment Registers: CS (Code Segment): Holds the base address for code instructions. DS (Data Segment): Points to data storage locations. SS (Stack Segment): Points to the stack. ES, FS, GS: Additional segment registers for memory management. 28 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Programmers Model 3. Control Registers: CR0: Controls the processor's operating mode (e.g., protected mode, paging, and other system control features). CR2: Holds the address of the last page fault. CR3: Points to the base of the page directory in paging. 4. Flags Register (EFLAGS): The EFLAGS register contains various flags that indicate the results of arithmetic or logic operations (such as the Zero Flag, Carry Flag, etc.). It also contains control flags for enabling interrupts and switching between operating modes (e.g., the Interrupt Flag, Direction Flag). 29 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Operating Modes The 80386 supports different operating modes, which define how the processor interacts with memory and external devices. 1. Real Mode: ○ In Real Mode, the processor operates as an 8086-compatible processor, addressing only up to 1 MB of memory (segmented memory). ○ This mode does not provide memory protection, paging, or multitasking features. 2. Protected Mode: ○ In Protected Mode, the 80386 can access up to 4 GB of memory and supports features like memory protection, virtual memory, and multitasking. It also provides mechanisms for handling errors and exceptions more efficiently. 3. Virtual 8086 Mode: ○ Virtual 8086 Mode allows the processor to run 16-bit real-mode applications (written for the 8086 or 80286) within a protected mode environment, maintaining backward compatibility while allowing 30 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 31 Sr. No. Addressing Mode Sr. No. Addressing Mode 1 Immediate Addressing Mode 5 Indexed Addressing Mode 2 Register Addressing Mode 6 Base-Register Plus Displacement Addressing 3 Direct Addressing Mode 7 Relative Addressing Mode 4 Indirect Addressing Mode 8 Segmented Addressing Mode JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 32 Immediate Addressing Mode 01 Operand is directly specified in the instruction itself (i.e., the operand is a constant value). ● Syntax: MOV AX, 5 Here, 5 is the immediate value that gets loaded into register AX. ● Example: MOV EAX, 0x1234 This instruction moves the immediate value 0x1234 into the EAX register. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 33 Register Addressing Mode 02 ● The operand is stored in a register. ● This is one of the simplest modes, where the source or destination of the operation is a register. ● Syntax: MOV AX, BX The contents of register BX are moved into register AX. ● Example: ADD AX, BX This adds the contents of register BX to AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 34 Direct Addressing Mode 03 ● This mode involves accessing a memory location directly using a 16-bit or 32-bit address. ● Syntax: MOV AX, [1000h] This moves the contents of the memory location 0x1000 into register AX. ● Example: MOV AX, [EAX] This accesses the memory at the address stored in EAX and moves the contents of that memory location into AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 35 Indirect Addressing Mode 04 ● The operand is accessed via a register that holds a memory address. The effective address is computed indirectly by the contents of a register. ● Syntax: MOV AX, [BX] The operand is located at the memory address contained in the BX register. ● Example: MOV AX, [EBX] This instruction moves the contents of the memory location pointed to by EBX into AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 36 Indexed Addressing Mode 05 ● The effective address is calculated by adding a displacement (or offset) to a base address. ● Syntax: MOV AX, [BX + SI] The effective address is the sum of the BX register and the SI register. ● Example: MOV AX, [EAX + ECX] This instruction adds EAX and ECX to compute the effective address, then moves the value from that memory address into AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 37 Base-Register Plus Displacement Addressing 06 ● This mode is a variant of indexed addressing. ● Syntax: MOV AX, [BX + 10] This calculates the effective address as the sum of BX and the displacement 10, and moves the contents of that address into AX. ● Example: MOV AX, [EBX + 0x04] This moves the contents of the memory at address EBX + 0x04 into AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 38 Relative Addressing Mode 07 ● This mode is used for branching or jumping instructions. ● Syntax: JMP short label Here, label is a memory address computed by adding the displacement to the current instruction pointer. ● Example: JMP [EAX] This instruction jumps to the address contained in the EAX register. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Addressing Modes and Data Types in the 80386 39 Segmented Addressing Mode 08 ● In 80386, memory is divided into segments, and the segment registers (CS, DS, SS, ES, FS, GS) determine the base address for each segment. ● The effective address of an operand is computed as the sum of the segment base and the offset (the actual address within the segment). ● Syntax: MOV AX, [ES:BX] Here, BX is the offset within the segment, and ES is the segment base. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Data Types in the 80386 Supports 16-bit and 8-bit data types for backward compatibility and for specific types of operations. 1. Byte (8 bits) ● A byte is an 8-bit unit of data. It is the smallest addressable unit of memory and is used for storing values such as characters or small integers. ● Example: MOV AL, [BX] This moves a byte from the memory location pointed to by BX into the AL register. 2. Word (16 bits) ● A word is a 16-bit unit of data. In the 80386, it is used to handle 16-bit integers, pointers, or addresses. ● Example: MOV AX, [BX] This moves a word (16 bits) from the memory location pointed to by BX into the AX register. 40 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Data Types in the 80386 3. Double Word (32 bits) ● A double word is a 32-bit unit of data. The 80386 primarily uses 32-bit data and 32-bit registers, such as EAX, EBX, ECX, etc. ● Example: MOV EAX, [EBX] This moves a double word (32 bits) from the memory location pointed to by EBX into the EAX register. 4. Quad Word (64 bits) (Note: Not directly supported by the 80386 as the processor is 32-bit, but the 80386 can handle 64-bit operations in future processors like x86-64) ● The 80386 itself doesn't directly support 64-bit data types, but in newer processors (like the x86-64), 64-bit data types can be processed. 41 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
Data Types in the 80386 5. Packed Data Types (BCD and Floating Point): ● The 80386 also supports packed binary-coded decimal (BCD) and floating-point operations, although these are typically handled by a coprocessor (e.g., the 80387 floating-point unit). ● BCD is used for financial and business calculations, where each digit is stored in a byte. ● Floating-point numbers are represented by 32-bit or 64-bit values in IEEE format for real-number arithmetic. 42 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
43 MOV: Moves data from a source to a destination. Example: MOV EAX, EBX PUSH: Pushes data onto the stack. Example: PUSH AX POP: Pops data from the stack into a register or memory location. Example: POP BX XCHG: Exchanges the values of two operands. Example:XCHG AX, BX LEA (Load Effective Address): Loads the effective address of a memory operand into a register. Example: LEA EAX, [EBX + 4] MOVSB, MOVSW, MOVSD: Used for moving bytes, words, and double words, respectively, in string operations. Applications Instruction Set of the Intel 80386 1. Data Movement Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
44 ADD: Adds two operands. Example: ADD AX, BX SUB: Subtracts the second operand from the first. Example: SUB EAX, EBX MUL: Multiplies two operands (unsigned). Example: MUL BX IMUL: Multiplies two operands (signed). Example: IMUL AX, BX DIV: Divides the accumulator by the operand (unsigned). Example: DIV BX IDIV: Divides the accumulator by the operand (signed). Example: IDIV BX INC: Increments the operand by 1. Example: INC AX ( This adds 1 to AX.) 2. Binary Arithmetic Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
45 DEC: Decrements the operand by 1. Example: DEC BX This subtracts 1 from BX. NEG: Negates the operand. Example: NEG AX This changes the sign of the value in AX. CMP: Compares two operands by subtracting them and setting flags accordingly. Example: CMP AX, BX This subtracts BX from AX and sets the flags based on the result. Applications Instruction Set of the Intel 80386 2. Binary Arithmetic Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
46 ● AAA (ASCII Adjust AX After Addition): Adjusts the value in the AX register after a BCD addition. Example: AAA This instruction adjusts AX after adding two packed BCD digits. ● AAM (ASCII Adjust AX on Multiply): Adjusts the AX register after multiplication of BCD numbers. Example: AAM This performs the necessary adjustments to AX after a BCD multiplication. ● AAD (ASCII Adjust AX on Division): Adjusts AX for BCD division. Example: AAD This adjusts AX after a division operation. ● AAS (ASCII Adjust AX for Subtraction): Adjusts AX after BCD subtraction. Example: AAS This adjusts AX after a BCD subtraction. Applications Instruction Set of the Intel 80386 3. Decimal Arithmetic Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
47 AND: Performs a bitwise AND operation between two operands. Example: AND AX, BX This performs a bitwise AND between AX and BX. OR: Performs a bitwise OR operation between two operands. Example: OR AX, BX This performs a bitwise OR between AX and BX. XOR: Performs a bitwise XOR operation between two operands. Example: XOR AX, BX This performs a bitwise XOR between AX and BX. NOT: Inverts the bits of the operand. Example: NOT AX This performs a bitwise NOT on AX. SHL / SAL (Shift Left): Shifts the bits of the operand to the left. Example: SHL AX, 1 This shifts the bits in AX one position to the left (equivalent to multiplying by 2). Applications Instruction Set of the Intel 80386 4. Logical Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
48 SHR (Shift Right): Shifts the bits of the operand to the right. Example: SHR BX, 1 This shifts the bits in BX one position to the right (equivalent to dividing by 2). ROL (Rotate Left) and ROR (Rotate Right): These instructions rotate the bits of the operand to the left or right. Example: ROL AX, 1 This rotates the bits of AX one position to the left. Applications Instruction Set of the Intel 80386 4. Logical Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
5. Control Transfer Instructions Control transfer instructions are used to alter the flow of execution in a program. These instructions include jumps, calls, and returns. ● JMP: Jumps to a specified address (unconditional). ○ Example: JMP label This jumps to the address specified by label. ● JE / JZ: Jumps if the zero flag is set (i.e., if the previous comparison was equal). ○ Example: JE label This jumps to label if the zero flag is set. 49 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
5. Control Transfer Instructions ● JNE / JNZ: Jumps if the zero flag is not set (i.e., if the previous comparison was not equal). ○ Example: JNE label This jumps to label if the zero flag is not set. ● CALL: Calls a procedure (pushes the return address to the stack). ○ Example: CALL procedure This calls the procedure at procedure and pushes the return address onto the stack. ● RET: Returns from a procedure (pops the return address from the stack). ○ Example: RET This pops the return address from the stack and jumps to that 50 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
5. Control Transfer Instructions ● INT: Triggers an interrupt. ○ Example: INT 21h This triggers interrupt 21h. 51 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
6. String and Character Transfer Instructions String instructions operate on sequences of data (strings) and typically use registers such as SI (source index) and DI (destination index) for indexing. ● MOVSB / MOVSW / MOVSD: Move bytes, words, or double words between memory locations. Example: MOVSB This moves a byte from the memory location pointed to by SI to the memory location pointed to by DI. ● CMPSB / CMPSW / CMPSD: Compare strings of bytes, words, or double words. ○ Example: CMPSB This compares bytes in the strings at SI and DI. 52 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
6. String and Character Transfer Instructions ● SCASB / SCASW / SCASD: Scan a string for a particular value. ○ Example: SCASB This scans a byte at DI and compares it with the value in AL. ● LODSB / LODSW / LODSD: Load a byte, word, or double word from the string into AL, AX, or EAX. ○ Example: LODSB This loads a byte from the memory location pointed to by SI 53 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
THANK YOU 54 PREPAIRED BY SWATI D. JADHAV CONNECTSWATIJADHAV55@GMAIL.COM JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.

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ARCHITECTURE OF 80386 IN DETAIL SPPU COMPUTER ENGINEERING SEM 4

  • 1. 1 Hope Foundation's International Institute of Information Technology, Pune Department of Computer Engineering Academic Year : 2024-25, Semester - II SUBJECT: MICROPROCESSOR CLASS: SE PREPAIRED BY SWATI D. JADHAV CONNECTSWATIJADHAV55@GMAIL.COM JANUARY 14, 2025
  • 2. UNIT I INTRODUCTION TO 80386 (07 HOURS) • CO1: Exhibit skill of assembly language programming for the application. • CO2: Classify Processor architectures. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 2 JANUARY 14, 2025
  • 3. OUTINE ● 80386 MICROPROCESSOR ● FEATURES OF 80386 ● OPERATING MODES OF 80386 ● ARCHITECTURE OF 80386 MICROPROCESSOR ● VERSIONS ● PROGRAMER MODELS ● OPERATING MODES ● ADDRESSING MODES ● DATA TYPES ● APPLICATION INSTRUCTION SETS CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 3 JANUARY 14, 2025
  • 4. 80386 MICROPROCESSOR • 80386 Microprocessor • A 32-bit processor • Holds the ability to carry out 32-bit operations in one cycle. • It has a data and address bus of 32-bit each. Thus has the ability to address 4 GB (or 232) of physical memory. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 4 JANUARY 14, 2025
  • 5. KEY FEATURES • Multitasking internal dedicated hardware that permits multitasking. • Protection capability are the two key characteristics of the 80386 microprocessor. 80386 has CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 5 JANUARY 14, 2025
  • 6. WHY 80386? • 8085 is a 8-bit microprocessor. • 8086 is a 16-bit microprocessor. • 80286 was an advancement of 8086 with some additional characteristics. • But with the advent of technology intel introduced a 32-bit microprocessor whose processing speed was twice that of the 80286 microprocessor. • This was an 80386 microprocessor that was designed by Intel in October 1985. • An upgraded version of the 80286 microprocessor. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 6 JANUARY 14, 2025
  • 7. FEATURES OF 80386 ✔ 32-bit microprocessor. ✔ Has ALU 32-bit. ✔ Holds data bus of 32-bit. ✔ Address bus of 32 bit. ✔ Physical memory addressability of 4 GB ✔ Virtual memory addressability of 64 TB. ✔ Supports a variety of operating clock frequencies- 16 MHz, 20 MHz, 25 MHz, and 33 MHz. ✔ It offers 3 stage pipeline: 1. Fetch 2. Decode 3. Execute. ✔ As it supports simultaneous fetching, decoding, and execution inside the system. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 7 JANUARY 14, 2025
  • 8. OPERATING MODES OF 80386 • 80286 supports two operating modes. 1.Real address mode 2.Protected virtual address mode. • 80386 supports 3 operating modes. 1.Real 2.Protected 3.Vrtual real mode. • Initially, the 80286 was booted in real mode. However, to have better operating performance, separate software command is used to switch from the real mode to the protected mode. • But it requires the resetting of the microprocessor in order to switch to real mode from protected mode. • This drawback is eliminated in 80386 that allows the switching between the modes using software commands. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 8 JANUARY 14, 2025
  • 9. OPERATING MODES OF 80386 1. Protected mode: Operates in a similar way like 80286 but offers higher memory addressing ability. 2. Virtual mode: The overall memory of 80386 can be divided into various virtual machines. All of them acts as a separate computer with 8086 microprocessor. This mode is also called virtual 8086 mode or V86 mode. 3. Virtual real mode: This mode allows the system to execute multiple programs in the protected memory. In case a program at a particular memory gets crashed then it will not cause any adverse effect on the other part of the memory. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 9 JANUARY 14, 2025
  • 10. ARCHITECTURE OF 80386 MICROPROCESSOR CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 10 5 2 3 4 1 JANUARY 14, 2025
  • 11. ARCHITECTURE OF 80386 MICROPROCESSOR • Basically, it has 5 functional units which are as follows: 1. Bus Interface Unit 2. Code Fetch Unit 3. Instruction Decode Unit 4. Execution Unit 5. Memory Management Unit CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 11 JANUARY 14, 2025
  • 12. 1. BUS INTERFACE UNIT (BIU) CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 12 JANUARY 14, 2025
  • 13. 1. BUS INTERFACE UNIT (BIU) • BIU holds a 32-bit bidirectional data bus as well as a 32-bit address bus. • Whenever a need for instruction or a data fetch is generated by the system then the BIU generates signals (according to the priority) for activating the data and address bus in order to fetch the data from the desired address. • The BIU connects the peripheral devices through the memory unit. • Controls the interfacing of external buses with the coprocessors. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 13 JANUARY 14, 2025
  • 14. 2. CODE PRE-FETCH UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 14 JANUARY 14, 2025
  • 15. 2. CODE PREFETCH UNIT • The code Pre-fetch unit fetches that instruction from the memory and stores it in a 16-byte pre-fetch queue. • So to speed up the operation this unit fetches the instructions in advance and the queue stores these instructions. • The sequence in which the instructions are fetched and gets stored in the queue depends on the order they exist in the memory. • It is to be noted here that, code prefetching holds lower priority than data transferring. • As whenever a need for data transfer is generated by the system then immediately the code pre-fetcher leaves control over the buses. • So that the BIU can transfer the required data. • But prefetching of instruction and storing it in the queue reduces the wait for the upcoming instruction to almost zero. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 15 JANUARY 14, 2025
  • 16. 3. INSTRUCTION DECODE UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 16 JANUARY 14, 2025
  • 17. 3. INSTRUCTION DECODE UNIT • We know that instructions in the memory are stored in the form of bits. • So, this unit decodes the instructions stored in the prefetch queue. • Basically the decoder changes the machine language code into assembly language and transfers it to the processor for further execution. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 17 JANUARY 14, 2025
  • 18. 4. EXECUTION UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 18 JANUARY 14, 2025
  • 19. 4. EXECUTION UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 19 JANUARY 14, 2025
  • 20. 4. EXECUTION UNIT • The decoded instructions are stored in the decoded instruction queue. • So, these instructions are provided to the execution unit in order to execute the instructions. • The execution unit controls the execution of the decoded instructions. • This unit has a 32-bit ALU, that performs the operation over 32-bit data in one cycle. • Also, it consists of 8 general purpose as well as 8 special purpose registers. • These are used for data handling and calculation of offset address. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 20 JANUARY 14, 2025
  • 21. 5. MEMORY MANAGEMENT UNIT • This unit has two separate units within it. These are • A. Segmentation Unit and • B. Paging Unit CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 21 JANUARY 14, 2025
  • 22. A. Segmentation unit CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 22 JANUARY 14, 2025
  • 23. A. Segmentation unit CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 23 JANUARY 14, 2025
  • 24. A. Segmentation unit • The segmentation unit plays a vital role in the 80836 microprocessor. It offers a protection mechanism in order to protect the code or data present in the memory from application programs. It gives 4 level protection to the data or code present in the memory. Every information in the memory is assigned a privilege level from PL0 to PL3. • Here, PL0 holds the highest priority and PL3 holds the lowest priority. • Suppose a file (either data or code) is needed to be accessed is stored in the memory at PL0. Then only those programs which are working at PL0 would be able to access that file. While other programs will not be able to access the same. Also, if a file is present at PL1, then programs of PL0 and PL1 both can access it. As PL0 has a higher priority than PL1. So, for protection purposes, the main part of the OS is stored in PL0 while PL3 holds the user programs. Providing protection to the data or code inside the system is the most advantageous factor that was first given by the 80386 microprocessor. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 24 JANUARY 14, 2025
  • 25. B. PAGING UNIT CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 25 JANUARY 14, 2025
  • 26. B. PAGING UNIT • The paging unit operates only in protected mode. • It changes the linear address into a physical address. • As the programmer only provides the virtual address and not the physical address. The segmentation unit controls the action of the paging unit, as the segmentation unit has the ability to convert the logical address into the linear address at the time of executing an instruction. • Basically, it changes the overall task map into pages and each page has a size of 4K. • This allows the handling of tasks in the form of pages rather than segments. • The paging unit supports multitasking. • This is so because the physical memory is not required to hold the whole segment of any task. Despite this, only that part of the segment which is needed to be currently executed must be stored in that memory whose physical address is calculated by the paging unit. This resultantly reduces the memory requirement and hence this frees the memory for other tasks. Thus by this we get an effective way for managing the memory to support multitasking. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 26 JANUARY 14, 2025
  • 27. 80386 VERSIONS • 1. 80386SX: The SX stands for single execution Holds a data bus of 16-bit. • 2. 80386DX: The DX stands for double execution Has a data bus of 32-bit. • Normally 80386 is 80386DX having 32-bit data bus. • But sometimes a system having an 8086 microprocessor needs to improve its performance as well as protection. And we know that 8086 is a 16-bit microprocessor, that operates on 2 banks. • 80386 in general has a 32-bit data bus that needs 4 banks. • To access some of the features of 80386 in a system having 8086 processor, we use 80386SX as a processor having a data bus of 16- bit. • Thus, in this case, a system can systembe upgraded to facilities of 80386 by simply changing the processor despite changing the overall . This is the reason why we have 80386SX version of the 80386 microprocessor. CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures. 27 JANUARY 14, 2025
  • 28. Programmers Model Includes the registers, flags, and segments that a programmer interacts with during coding. 1. General-Purpose Registers: EAX, EBX, ECX, EDX: 32-bit general-purpose registers used for various arithmetic, logical, and data manipulation operations. ESI, EDI: Used for source and destination addressing during string operations. EBP: Base pointer, used for stack frames in procedures. ESP: Stack pointer, points to the top of the stack. 1. Segment Registers: CS (Code Segment): Holds the base address for code instructions. DS (Data Segment): Points to data storage locations. SS (Stack Segment): Points to the stack. ES, FS, GS: Additional segment registers for memory management. 28 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 29. Programmers Model 3. Control Registers: CR0: Controls the processor's operating mode (e.g., protected mode, paging, and other system control features). CR2: Holds the address of the last page fault. CR3: Points to the base of the page directory in paging. 4. Flags Register (EFLAGS): The EFLAGS register contains various flags that indicate the results of arithmetic or logic operations (such as the Zero Flag, Carry Flag, etc.). It also contains control flags for enabling interrupts and switching between operating modes (e.g., the Interrupt Flag, Direction Flag). 29 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 30. Operating Modes The 80386 supports different operating modes, which define how the processor interacts with memory and external devices. 1. Real Mode: ○ In Real Mode, the processor operates as an 8086-compatible processor, addressing only up to 1 MB of memory (segmented memory). ○ This mode does not provide memory protection, paging, or multitasking features. 2. Protected Mode: ○ In Protected Mode, the 80386 can access up to 4 GB of memory and supports features like memory protection, virtual memory, and multitasking. It also provides mechanisms for handling errors and exceptions more efficiently. 3. Virtual 8086 Mode: ○ Virtual 8086 Mode allows the processor to run 16-bit real-mode applications (written for the 8086 or 80286) within a protected mode environment, maintaining backward compatibility while allowing 30 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 31. Addressing Modes and Data Types in the 80386 31 Sr. No. Addressing Mode Sr. No. Addressing Mode 1 Immediate Addressing Mode 5 Indexed Addressing Mode 2 Register Addressing Mode 6 Base-Register Plus Displacement Addressing 3 Direct Addressing Mode 7 Relative Addressing Mode 4 Indirect Addressing Mode 8 Segmented Addressing Mode JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 32. Addressing Modes and Data Types in the 80386 32 Immediate Addressing Mode 01 Operand is directly specified in the instruction itself (i.e., the operand is a constant value). ● Syntax: MOV AX, 5 Here, 5 is the immediate value that gets loaded into register AX. ● Example: MOV EAX, 0x1234 This instruction moves the immediate value 0x1234 into the EAX register. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 33. Addressing Modes and Data Types in the 80386 33 Register Addressing Mode 02 ● The operand is stored in a register. ● This is one of the simplest modes, where the source or destination of the operation is a register. ● Syntax: MOV AX, BX The contents of register BX are moved into register AX. ● Example: ADD AX, BX This adds the contents of register BX to AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 34. Addressing Modes and Data Types in the 80386 34 Direct Addressing Mode 03 ● This mode involves accessing a memory location directly using a 16-bit or 32-bit address. ● Syntax: MOV AX, [1000h] This moves the contents of the memory location 0x1000 into register AX. ● Example: MOV AX, [EAX] This accesses the memory at the address stored in EAX and moves the contents of that memory location into AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 35. Addressing Modes and Data Types in the 80386 35 Indirect Addressing Mode 04 ● The operand is accessed via a register that holds a memory address. The effective address is computed indirectly by the contents of a register. ● Syntax: MOV AX, [BX] The operand is located at the memory address contained in the BX register. ● Example: MOV AX, [EBX] This instruction moves the contents of the memory location pointed to by EBX into AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 36. Addressing Modes and Data Types in the 80386 36 Indexed Addressing Mode 05 ● The effective address is calculated by adding a displacement (or offset) to a base address. ● Syntax: MOV AX, [BX + SI] The effective address is the sum of the BX register and the SI register. ● Example: MOV AX, [EAX + ECX] This instruction adds EAX and ECX to compute the effective address, then moves the value from that memory address into AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 37. Addressing Modes and Data Types in the 80386 37 Base-Register Plus Displacement Addressing 06 ● This mode is a variant of indexed addressing. ● Syntax: MOV AX, [BX + 10] This calculates the effective address as the sum of BX and the displacement 10, and moves the contents of that address into AX. ● Example: MOV AX, [EBX + 0x04] This moves the contents of the memory at address EBX + 0x04 into AX. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 38. Addressing Modes and Data Types in the 80386 38 Relative Addressing Mode 07 ● This mode is used for branching or jumping instructions. ● Syntax: JMP short label Here, label is a memory address computed by adding the displacement to the current instruction pointer. ● Example: JMP [EAX] This instruction jumps to the address contained in the EAX register. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 39. Addressing Modes and Data Types in the 80386 39 Segmented Addressing Mode 08 ● In 80386, memory is divided into segments, and the segment registers (CS, DS, SS, ES, FS, GS) determine the base address for each segment. ● The effective address of an operand is computed as the sum of the segment base and the offset (the actual address within the segment). ● Syntax: MOV AX, [ES:BX] Here, BX is the offset within the segment, and ES is the segment base. JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 40. Data Types in the 80386 Supports 16-bit and 8-bit data types for backward compatibility and for specific types of operations. 1. Byte (8 bits) ● A byte is an 8-bit unit of data. It is the smallest addressable unit of memory and is used for storing values such as characters or small integers. ● Example: MOV AL, [BX] This moves a byte from the memory location pointed to by BX into the AL register. 2. Word (16 bits) ● A word is a 16-bit unit of data. In the 80386, it is used to handle 16-bit integers, pointers, or addresses. ● Example: MOV AX, [BX] This moves a word (16 bits) from the memory location pointed to by BX into the AX register. 40 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 41. Data Types in the 80386 3. Double Word (32 bits) ● A double word is a 32-bit unit of data. The 80386 primarily uses 32-bit data and 32-bit registers, such as EAX, EBX, ECX, etc. ● Example: MOV EAX, [EBX] This moves a double word (32 bits) from the memory location pointed to by EBX into the EAX register. 4. Quad Word (64 bits) (Note: Not directly supported by the 80386 as the processor is 32-bit, but the 80386 can handle 64-bit operations in future processors like x86-64) ● The 80386 itself doesn't directly support 64-bit data types, but in newer processors (like the x86-64), 64-bit data types can be processed. 41 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 42. Data Types in the 80386 5. Packed Data Types (BCD and Floating Point): ● The 80386 also supports packed binary-coded decimal (BCD) and floating-point operations, although these are typically handled by a coprocessor (e.g., the 80387 floating-point unit). ● BCD is used for financial and business calculations, where each digit is stored in a byte. ● Floating-point numbers are represented by 32-bit or 64-bit values in IEEE format for real-number arithmetic. 42 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 43. 43 MOV: Moves data from a source to a destination. Example: MOV EAX, EBX PUSH: Pushes data onto the stack. Example: PUSH AX POP: Pops data from the stack into a register or memory location. Example: POP BX XCHG: Exchanges the values of two operands. Example:XCHG AX, BX LEA (Load Effective Address): Loads the effective address of a memory operand into a register. Example: LEA EAX, [EBX + 4] MOVSB, MOVSW, MOVSD: Used for moving bytes, words, and double words, respectively, in string operations. Applications Instruction Set of the Intel 80386 1. Data Movement Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 44. 44 ADD: Adds two operands. Example: ADD AX, BX SUB: Subtracts the second operand from the first. Example: SUB EAX, EBX MUL: Multiplies two operands (unsigned). Example: MUL BX IMUL: Multiplies two operands (signed). Example: IMUL AX, BX DIV: Divides the accumulator by the operand (unsigned). Example: DIV BX IDIV: Divides the accumulator by the operand (signed). Example: IDIV BX INC: Increments the operand by 1. Example: INC AX ( This adds 1 to AX.) 2. Binary Arithmetic Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 45. 45 DEC: Decrements the operand by 1. Example: DEC BX This subtracts 1 from BX. NEG: Negates the operand. Example: NEG AX This changes the sign of the value in AX. CMP: Compares two operands by subtracting them and setting flags accordingly. Example: CMP AX, BX This subtracts BX from AX and sets the flags based on the result. Applications Instruction Set of the Intel 80386 2. Binary Arithmetic Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 46. 46 ● AAA (ASCII Adjust AX After Addition): Adjusts the value in the AX register after a BCD addition. Example: AAA This instruction adjusts AX after adding two packed BCD digits. ● AAM (ASCII Adjust AX on Multiply): Adjusts the AX register after multiplication of BCD numbers. Example: AAM This performs the necessary adjustments to AX after a BCD multiplication. ● AAD (ASCII Adjust AX on Division): Adjusts AX for BCD division. Example: AAD This adjusts AX after a division operation. ● AAS (ASCII Adjust AX for Subtraction): Adjusts AX after BCD subtraction. Example: AAS This adjusts AX after a BCD subtraction. Applications Instruction Set of the Intel 80386 3. Decimal Arithmetic Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 47. 47 AND: Performs a bitwise AND operation between two operands. Example: AND AX, BX This performs a bitwise AND between AX and BX. OR: Performs a bitwise OR operation between two operands. Example: OR AX, BX This performs a bitwise OR between AX and BX. XOR: Performs a bitwise XOR operation between two operands. Example: XOR AX, BX This performs a bitwise XOR between AX and BX. NOT: Inverts the bits of the operand. Example: NOT AX This performs a bitwise NOT on AX. SHL / SAL (Shift Left): Shifts the bits of the operand to the left. Example: SHL AX, 1 This shifts the bits in AX one position to the left (equivalent to multiplying by 2). Applications Instruction Set of the Intel 80386 4. Logical Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 48. 48 SHR (Shift Right): Shifts the bits of the operand to the right. Example: SHR BX, 1 This shifts the bits in BX one position to the right (equivalent to dividing by 2). ROL (Rotate Left) and ROR (Rotate Right): These instructions rotate the bits of the operand to the left or right. Example: ROL AX, 1 This rotates the bits of AX one position to the left. Applications Instruction Set of the Intel 80386 4. Logical Instructions JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 49. 5. Control Transfer Instructions Control transfer instructions are used to alter the flow of execution in a program. These instructions include jumps, calls, and returns. ● JMP: Jumps to a specified address (unconditional). ○ Example: JMP label This jumps to the address specified by label. ● JE / JZ: Jumps if the zero flag is set (i.e., if the previous comparison was equal). ○ Example: JE label This jumps to label if the zero flag is set. 49 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 50. 5. Control Transfer Instructions ● JNE / JNZ: Jumps if the zero flag is not set (i.e., if the previous comparison was not equal). ○ Example: JNE label This jumps to label if the zero flag is not set. ● CALL: Calls a procedure (pushes the return address to the stack). ○ Example: CALL procedure This calls the procedure at procedure and pushes the return address onto the stack. ● RET: Returns from a procedure (pops the return address from the stack). ○ Example: RET This pops the return address from the stack and jumps to that 50 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 51. 5. Control Transfer Instructions ● INT: Triggers an interrupt. ○ Example: INT 21h This triggers interrupt 21h. 51 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 52. 6. String and Character Transfer Instructions String instructions operate on sequences of data (strings) and typically use registers such as SI (source index) and DI (destination index) for indexing. ● MOVSB / MOVSW / MOVSD: Move bytes, words, or double words between memory locations. Example: MOVSB This moves a byte from the memory location pointed to by SI to the memory location pointed to by DI. ● CMPSB / CMPSW / CMPSD: Compare strings of bytes, words, or double words. ○ Example: CMPSB This compares bytes in the strings at SI and DI. 52 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 53. 6. String and Character Transfer Instructions ● SCASB / SCASW / SCASD: Scan a string for a particular value. ○ Example: SCASB This scans a byte at DI and compares it with the value in AL. ● LODSB / LODSW / LODSD: Load a byte, word, or double word from the string into AL, AX, or EAX. ○ Example: LODSB This loads a byte from the memory location pointed to by SI 53 JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.
  • 54. THANK YOU 54 PREPAIRED BY SWATI D. JADHAV CONNECTSWATIJADHAV55@GMAIL.COM JANUARY 14, 2025 CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor architectures.