2. Overview of Exceptions in ARM
• • Exceptions are events that interrupt normal
execution.
• • Can be caused by software, hardware, or
external signals.
• • ARM handles exceptions using vector table
entries.
• • Examples include Reset, Undefined
Instructions, and Data Abort.
3. Types of Exceptions
• 1. **Reset** – Occurs on processor startup or reset
signal.
• 2. **Undefined Instruction** – Triggered when an
unknown instruction is executed.
• 3. **Software Interrupt (SWI)** – Used for OS calls
and system services.
• 4. **Prefetch Abort** – When instruction fetch fails
due to memory issues.
• 5. **Data Abort** – Occurs when an invalid memory
access happens.
4. Exception Handling Process
• 1. Processor saves CPSR into SPSR of the mode
handling the exception.
• 2. The processor switches to the relevant mode
(e.g., Abort mode).
• 3. Execution jumps to the corresponding address
in the vector table.
• 4. Exception handler executes necessary routines.
• 5. The handler restores CPSR and resumes normal
execution.
5. Exception Flow Diagram
• Shows how ARM transitions between modes when exceptions occur.
• Includes how CPSR is saved and execution branches to exception handlers.
[Insert Figure Here]
6. Software Interrupt (SWI) in Detail
• • SWI is a special instruction used to invoke
system calls.
• • Used to switch from user mode to
supervisor mode.
• • Common in OS kernels and embedded
system calls.
• • The processor jumps to the SWI vector in
the vector table.
7. Overview of Interrupts in ARM
• • Interrupts allow external devices to signal
the processor.
• • ARM supports two main types of interrupts:
• - **IRQ (Interrupt Request):** General-
purpose interrupt.
• - **FIQ (Fast Interrupt Request):** Higher
priority, faster response.
8. ARM Vector Table
• • The vector table is a memory-mapped table at
address 0x00000000.
• • Contains branch instructions pointing to
exception handlers.
• • Entries in the vector table:
• - Reset (0x00), Undefined Instruction (0x04),
SWI (0x08),
• - Prefetch Abort (0x0C), Data Abort (0x10), IRQ
(0x18), FIQ (0x1C).
9. FIQ vs IRQ – Key Differences
• • **FIQ (Fast Interrupt Request):**
• - Higher priority than IRQ.
• - Uses banked registers for faster execution.
• - Typically used for real-time applications like
motor control.
• • **IRQ (Interrupt Request):**
• - Standard interrupt with lower priority.
• - Saves context and switches to interrupt mode.
10. Nested Interrupt Handling
• • ARM supports **nested interrupts**, where
a higher priority interrupt can preempt a
lower one.
• • The interrupt handler must save the CPSR
before enabling other interrupts.
• • Used in real-time systems to ensure high-
priority tasks run first.
11. Core Extensions in ARM
• • ARM cores include hardware extensions to
improve performance and efficiency.
• • Three major core extensions:
• - Cache & Tightly Coupled Memory (TCM)
• - Memory Management (MMU, MPU)
• - Coprocessor Interface.
12. Cache and Tightly Coupled Memory (TCM)
• • Cache stores frequently accessed data to
speed up execution.
• • ARM processors may have **separate
instruction and data caches** (Harvard
architecture).
• • TCM is a high-speed SRAM used for real-
time tasks requiring predictable memory
access.
13. • Diagram comparing cache-based and TCM-based architectures.
• Shows how memory access latency is reduced.
14. Memory Management – MMU & MPU
• • **Memory Protection Unit (MPU):**
• - Defines memory regions with access permissions.
• - Used in embedded systems with simple memory
maps.
• • **Memory Management Unit (MMU):**
• - Provides virtual memory mapping.
• - Supports multitasking operating systems (Linux,
Android).
15. Coprocessors in ARM
• • ARM supports coprocessors to enhance
specific functionalities.
• • Example: Vector Floating Point (VFP)
coprocessor for floating-point arithmetic.
• • Coprocessor 15 (CP15) controls cache,
MMU, and system configuration.
![Exception Flow Diagram
• Shows how ARM transitions between modes when exceptions occur.
• Includes how CPSR is saved and execution branches to exception handlers.
[Insert Figure Here]](https://image.slidesharecdn.com/armadvancedexceptionsinterruptsextensions-250305143502-35b6f839/85/ARM_Advanced_Exceptions_Interrupts_Extensions-pptx-5-320.jpg)
