ARPS Architecture 1
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This document outlines a proposed VLSI architecture for deformable motion estimation using the Adaptive Rood Pattern Search (ARPS) technique. It begins with an introduction to motion estimation and the ARPS method. It then presents the objectives to design an efficient architecture using ARPS and enhance it for mesh-based motion estimation. Simulation results showing the performance of ARPS are provided, followed by descriptions of the proposed architecture and Xilinx simulation results. Future work plans to optimize the architecture and develop an adaptive mesh-based motion estimation.
![INTRODUCTION
Motion Estimation is one of the most important block Video
compression system. [5]
Block-Matching algorithm (BMA) used for motion estimation (ME) in
various video coding.
FS is highly computational so, we use fast BMA Techniques.
Adaptive Rood Pattern Search (ARPS) most efficient in terms of
the computational speed and achieves good PSNR.
3](https://image.slidesharecdn.com/12ec62r10-140523074035-phpapp01/85/ARPS-Architecture-1-3-320.jpg)
![Adaptive Rood Pattern
• Predicted MV along with four-armed rood pattern is added
into ARP which is similar to target MV.
• ARP’s size,
L = Max {| MVpredicted(x)|,| MVpredicted(y)|}
• Leftmost blocks in each frame have a fixed arm length of 2
pixels.
• ARP has either 5 (non overlapping) or 4 (with overlapping)
search points in the initial search stage.
13
Figure. 1. Adaptive Rood Pattern
[1][2]](https://image.slidesharecdn.com/12ec62r10-140523074035-phpapp01/85/ARPS-Architecture-1-13-320.jpg)
![Fixed Pattern – for refined search
• Initial search, leads to new search center.
• Small search pattern (URP) is used for local refined
search unrestrictedly and repeatedly .
• MME point of current step becomes center for next
iteration until MME point is at the center of the fixed
pattern.
14
Figure. 2. Two type of fixed Search Patterns
[1][2]](https://image.slidesharecdn.com/12ec62r10-140523074035-phpapp01/85/ARPS-Architecture-1-14-320.jpg)
![REFERENCES
[1] Yao Nie and Kai-Kuang Ma “Adaptive Rood Pattern Search for Fast Block-Matching Motion Estimation”
IEEE Transactions, Image Processing, Vol. 11, No. 12, pp. 1442-1448, December 2002.
[2] Kai-Kuang Ma and Gang Qiu “An Adaptive Rood Pattern Search For Fast Block-Matching Motion
Estimation in JVT/H.26L” IEEE Conference, Circuits and Systems, Vol. 2, pp. II – 708 – II – 711, 2003.
[3] Mohammed Sayed and Wael Badawy “An Affine-Based Algorithm and SIMD Architecture for Video
Compression with Low Bit-Rate Applications” IEEE Transactions, Circuits and Systems for Video
Technology, Vol. 16, No. 4, April 2006.
[4] Wael Badawy, Guoqing Zhang and Magdy Bayoumi “VLSI Architecture for Hierarchical Mesh Based
Motion Estimation”, IEEE conference, Signal processing systems, pp. 110-119, October 1999.
[5] Iain E.G. Richardson, “H.264 and MPEG-4 Video Compression Video Coding for Next generation
Multimedia”, 2003.
[6] S. Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis,” second edition, Prentice Hall
publication, February 2003.
25](https://image.slidesharecdn.com/12ec62r10-140523074035-phpapp01/85/ARPS-Architecture-1-25-320.jpg)
ARPS Architecture 1
- 1. VLSI ARCHITECTURE FOR DEFORMABLE MOTION ESTIMATION USING ARPS TECHNIQUE 1 HARSH KAUSHIK 12EC62R10 GUIDED BY :- DR. INDRAJIT CHAKRABARTI
- 2. OUTLINE INTRODUCTION OBJECTIVE MIDSEM WORK ARPS METHOD PROPOSED ARCHITECTURE XILINX RESULTS REFERENCES 2
- 3. INTRODUCTION Motion Estimation is one of the most important block Video compression system. [5] Block-Matching algorithm (BMA) used for motion estimation (ME) in various video coding. FS is highly computational so, we use fast BMA Techniques. Adaptive Rood Pattern Search (ARPS) most efficient in terms of the computational speed and achieves good PSNR. 3
- 4. OBJECTIVE • To design an efficient architecture for block-matching motion estimation using ARPS search technique • To enhance the architecture for mesh based motion estimation which will help to incorporate the non-translational motions such as shear, rotation, zoom etc. present in the video. 4
- 5. MATLAB SIMULATION RESULTS 5 AVERAGE PSNR (dB) PERFORMANCE OF FS, TSS, DS, ARPS AND FIXED MESH ARPS Video (Kbps) FS TSS DS ARPS FIXED MESH ARPS AKIYO(1024) 43.7737 43.6324 43.7575 43.7228 40.6678 BRIDGE-CLOSE(1024) 35.0512 35.0512 35.0512 35.0512 34.2305 CONTAINER (1024) 38.3828 38.3823 38.3822 38.3820 37.6384 ELEPHANT DREAMS (1024) 38.4459 38.0282 38.2063 38.0708 38.1541 FOREMAN (1024) 33.8942 33.1140 33.6211 33.4685 28.4741 FOOTBALL (1024) 23.5653 22.8817 22.7465 22.8567 22.4860 HALL (1024) 35.5239 35.4433 35.4129 35.3432 30.6391 MOTHER AND DAUGHTER (1024) 42.2745 42.1989 42.2362 42.2024 39.2444 NEWS (1024) 38.4927 38.4050 38.4446 38.4142 34.5488 PARIS (1024) 31.3799 31.0338 31.2952 31.2478 28.2278 SILENT (1024) 37.1517 36.9080 36.8728 36.8263 36.9954 STEFAN (1024) 25.9698 24.7376 24.3586 25.5327 22.4696 TABLE (1024) 31.3935 30.7814 30.6616 30.4916 27.0253 TEMPETE (1024) 26.7330 26.5292 26.5532 26.5184 25.1976 WATERFALL (1024) 35.3052 35.3051 35.3053 35.3047 32.5124
- 6. AVERAGE NUMBER OF SEARCH POINTS PER MV GENERATION 6 Video (Kbps) FS TSS DS ARPS AKIYO(1024) 262.1717 23.2121 12.2596 5.0378 BRIDGE-CLOSE(1024) 262.1717 23.2432 14.2559 6.0570 CONTAINER (1024) 262.1717 23.2256 12.3772 5.1253 ELEPHANT DREAMS (1024) 262.1717 23.2935 16.343 8.1380 FOREMAN (1024) 262.1717 23.2571 16.043 8.4591 FOOTBALL (1024) 262.1717 23.3654 20.805 11.7219 HALL (1024) 262.1717 23.2510 12.9231 5.8659 MOTHER AND DAUGHTER (1024) 262.1717 23.2874 13.375 6.2562 NEWS (1024) 262.1717 23.2128 12.5235 5.3822 PARIS (1024) 262.1717 23.2217 12.827 5.7681 SILENT (1024) 262.1717 23.2143 12.9878 5.8658 STEFAN (1024) 262.1717 23.3177 17.2021 8.1941 TABLE (1024) 262.1717 23.2853 13.7468 6.5654 TEMPETE (1024) 262.1717 23.2356 12.867 5.9502 WATERFALL (1024) 262.1717 23.2121 12.2942 5.2849
- 8. BLOCK-MATCHING ALGORITHM USING ARPS 8 REFERENCE FRAME CURRENT FRAME RECONSTRUCTED FRAME AKIYO SEQUENCE
- 9. BLOCK-MATCHING ALGORITHM USING ARPS 9 REFERENCE FRAME CURRENT FRAME RECONSTRUCTED FRAME MOTHER AND DAUGHTER SEQUENCE
- 10. BLOCK-MATCHING ALGORITHM USING ARPS 10 REFERENCE FRAME CURRENT FRAME RECONSTRUCTED FRAME TABLE TENNIS SEQUENCE
- 11. BLOCK-MATCHING ALGORITHM USING ARPS 11 REFERENCE FRAME CURRENT FRAME RECONSTRUCTED FRAME FOOTBALL SEQUENCE
- 12. Adaptive Rood Pattern Search method • Two main issues are: 1) Pre-determining the motion behavior of current block ? 2) Size and shape of the search pattern ? • For First issue, Current block’s motion behavior can be predicted by its neighboring blocks’ MVs. • For Second issue, two types of search patterns are used:- 1. Adaptive rood pattern (ARP) 2. Small search pattern (URP) • Prediction of the target motion vector is achieved with the help of ROS (region of search). 12
- 13. Adaptive Rood Pattern • Predicted MV along with four-armed rood pattern is added into ARP which is similar to target MV. • ARP’s size, L = Max {| MVpredicted(x)|,| MVpredicted(y)|} • Leftmost blocks in each frame have a fixed arm length of 2 pixels. • ARP has either 5 (non overlapping) or 4 (with overlapping) search points in the initial search stage. 13 Figure. 1. Adaptive Rood Pattern [1][2]
- 14. Fixed Pattern – for refined search • Initial search, leads to new search center. • Small search pattern (URP) is used for local refined search unrestrictedly and repeatedly . • MME point of current step becomes center for next iteration until MME point is at the center of the fixed pattern. 14 Figure. 2. Two type of fixed Search Patterns [1][2]
- 15. Block Address Generator Current Frame RAM Reference Frame RAM Absolute Difference SAD Adder Reference Frame Base Address Generator Current Frame Base Address Generator Memory Offset Sequence and Position Generator Offset & Position of Minimum SAD Comparator Motion Vector En _ block Search PROPOSED ARCHITECTURE 15 clock over search complete finish finish compare SAD SADmin check Curr Value Ref Value ----- Control path Signals Data path Signals offset pos
- 16. XILINX RESULTS 16 Figure. 4 Behavioral simulation (Virtex - 6) for 50us. (all values in Binary)
- 17. 17 Figure. 5 Behavioral simulation for 50us. (all values in Unsigned Decimal)
- 18. 18Figure. 6 Behavioral simulation showing SAD computation and Position Generation
- 19. 19 Figure. 7 Behavioral simulation showing SAD computation
- 20. Timing Report of Xilinx 20
- 21. Power Report of Xilinx 21
- 22. RTL SCHEMATIC 22
- 24. FUTURE WORK Optimization of the proposed Architecture in terms of speed, power and area. Use of CIF frames as test sequence. Developing an Architecture for Fixed Mesh based motion estimation using ARPS technique. Enhancing the Fixed Mesh into Adaptive Mesh (Hierarchical) for accurate motion estimation. 24
- 25. REFERENCES [1] Yao Nie and Kai-Kuang Ma “Adaptive Rood Pattern Search for Fast Block-Matching Motion Estimation” IEEE Transactions, Image Processing, Vol. 11, No. 12, pp. 1442-1448, December 2002. [2] Kai-Kuang Ma and Gang Qiu “An Adaptive Rood Pattern Search For Fast Block-Matching Motion Estimation in JVT/H.26L” IEEE Conference, Circuits and Systems, Vol. 2, pp. II – 708 – II – 711, 2003. [3] Mohammed Sayed and Wael Badawy “An Affine-Based Algorithm and SIMD Architecture for Video Compression with Low Bit-Rate Applications” IEEE Transactions, Circuits and Systems for Video Technology, Vol. 16, No. 4, April 2006. [4] Wael Badawy, Guoqing Zhang and Magdy Bayoumi “VLSI Architecture for Hierarchical Mesh Based Motion Estimation”, IEEE conference, Signal processing systems, pp. 110-119, October 1999. [5] Iain E.G. Richardson, “H.264 and MPEG-4 Video Compression Video Coding for Next generation Multimedia”, 2003. [6] S. Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis,” second edition, Prentice Hall publication, February 2003. 25
- 26. THANK YOU 26
Editor's Notes
- #4: Applications such as video-on-demand, video conferencing, streaming video, digital TV/HDTV broadcast, CD/DVD storage, etc., demands amount of reduction in video data for storing or transmitting the video efficiently
- #13: As Speed and accuracy of pattern based algorithms depend on pattern size and magnitude of the target motion vector. Adjacent macro block’s belong to same moving object have similar motions so they can be used for prediction of target motion vector.
- #16: DESCRIPTION OF THE BLOCKS IN THE PROPOSED ARCHITECTURE FRAME STORAGE RAM’s :- The pixel values of the current and the reference frames are stored in two RAMs each of size 256 * 256 words having 8-bit width. Each word in the memory (corresponding to each pixel in the stored frame) is addressed by a 16-bit address in such a way that the eight most significant bits make the row-address and the eight least significant bits make the column-address of the pixel in the frame. The frame size considered here is 176 * 144 size of the standard QCIF format is. Before storing the pixel values in RAM, the dimensions of the frame are extended to nearest larger number which is an integer power-of-2 i.e. 256 * 256 in this case, by padding zeros in the remaining places. CURRENT FRAME AND REFERENCE FRAME BASE ADDRESS GENERATOR :- These two units will be storing the current and the reference base address and will be generating addresses of the current macro block for block-matching algorithm and the addresses of the nodes in case of mesh based motion estimation. This block will provide the 16-bit address of the current block and the reference block to the block address generator unit. BLOCK ADDRESS GENERATOR :- This unit is needed to generate offset addresses, with respect to the given block address, in order to scan individual pixels of the given 8 * 8 block in raster-scan order. In other words, it takes the address of an 8 * 8 block as input and generates addresses to the pixels of that block. The input address is the address of the top-left corner pixel of the given 8 * 8 block. A counter is used to address each individual pixel of the given 8 * 8. SAD :- The SAD module computes the sum of absolute differences (SAD) of the current block and the reference block in comparison by taking absolute difference of corresponding pixel values in both the blocks and accumulating 64 absolute differences for (8 * 8) block. All pixel values are 8-bit values. So the maximum possible SAD is 255 * 64 = 16320 which can be stored in a 14-bit register. If the reference block address falls out of the bounds, then the SAD register is loaded with the maximum possible register value i.e. 16383. A block address is invalid if any of its pixel has row address beyond the range [0, 175] and/or column address beyond the range [0, 144]. The SAD computed for each block is stored in a register and it is compared with the existing minimum SAD (MSAD) stored in another register. If the SAD of the recent matching is less than the existing minimum SAD then the comparator raises an indication of availability of a new MSAD, which then asserts load signals for the MSAD and the store the motion vector corresponding to that block in the motion vector register. MOTION VECTOR :- This block will save the values of the motion vectors for each of the macro blocks present in the current frame.