SlideShare a Scribd company logo
38
INTRODUCTION
The fundamental goal of a verification engineer is to ensure
that the Device Under Test (DUT) behaves correctly in
its verification environment. As chip designs grow larger
and more complex with thousands of possible states and
transitions, a comprehensive verification environment must
be created that minimizes development effort. To minimize
effort, functional coverage is used as a guide for directing
verification resources by identifying tested and untested
portions of the design. The approach should give any
verification engineer confidence in DUT functionality.
Functional coverage is a user-defined coverage which maps
each functionality defined in the test plan to be tested to a
cover point. Whenever the functionality to be tested is hit in
the simulation, the functional coverage point is automatically
updated. A functional coverage report can be generated
which summarizes how many coverage points were hit.
Functional coverage metrics can be used to measure the
progress of a verification effort.
The key aspects of functional coverage are as follows:
• It is user-specified and not automatically inferred from
the design.
• It is based on the design specification and is thus
independent of the actual design code or its structure.
This article represents some of the important features of a
functional coverage model that will be useful for verification
engineers to develop a functional coverage model with
high quality. The scenarios discussed subsequently cover
some of the finer aspects of using these constructs more
productively.
USE OF DEFAULT SEQUENCE
FOR TRANSITION COVERAGE
Similar to ‘Default Construct’ which is useful for catching
unplanned or invalid values, ‘Default Sequence’ is used to
catch all transitions (or sequences) that do not lie within any
of the defined transition bins.
When any non-default sequence transition is incremented
or any previously specified bin transition is not in pending
state, then ‘bin allother’ of that cover point will be
incremented.
In the following example, the transition from value 1 to 0 is
specified by bins flag_trans. So if any transition occurs from
1 to 0, then it will be captured by flag_trans bins.
Here, by using default sequence (shown on the next page)
you can capture other transitions that are not specified
exclusively.
Figure 1: Functional Coverage Flow Diagram
Functional Coverage Development Tips: Do’s and Don’ts
by Samrat Patel & Vipul Patel, eInfochips
39
While using default sequence, avoid the following
scenarios:
Scenario-1: The default sequence specification does not
accept multiple transition bins (the [] notation). It will give
an error. Therefore, avoid using a default sequence with
multiple transition bins.
Scenario-2: The default sequence specification cannot
be explicitly ignored. It will be an error for bins designated
as ignore_bins to specify a default sequence. Therefore,
avoid using a default sequence with ignore_bins.
EXCLUSION OF CROSS COVERAGE
AUTO GENERATED BINS
Problem: Suppose the requirement is to do cross
coverage between two cover points and capture only
specific user-defined bins as follows:
In the above example, the coverage report will capture
user-defined bins along with auto-generated bins.
However, the requirement is to capture only specific user
bins.
The limitation of cross coverage is that even on specifying
only user bins, it will also generate cross coverage bins
automatically.
Solution: To disable auto generated cross bins, you
should use ignore_bins as shown below:
Another way is that instead of specifying user-defined bins,
simply use ignore_bins. This will ignore other bins except
required user-defined bins so we can get the expected result.
AVOID USING MULTIPLE BIN CONSTRUCT (THE []
NOTATION) WITH NON-CONSECUTIVE REPETITION
The non-consecutive repetition is specified using
trans_item [= repeat_range]. The required number of
occurrences of a particular value is specified by the
repeat_range.
Problem: Using non-consecutive repetition with multiple
bins construct (the [] notation) gives a fatal run time error
as follows:
cp_flag: coverpoint data [24] {
bins flag_trans = (1 => 0);
bins allother = default sequence;
}
cr_thr_addr: cross cp_thr, cp_reg_addr {
bins thr_add = binsof(cp_reg_addr) intersect
{12’h01C};
ignore_bins thr_add_ig = !binsof(cp_reg_addr) intersect
{12’h01C};
}
cr_thr_addr: cross cp_thr, cp_reg_addr {
ignore_bins thr_add = binsof(cp_reg_addr) intersect
{12’h020};
}
cp_flag: coverpoint data [24] {
bins flag_trans[] = (1 => 0[=3]);
}
Simulation Error:
# ** Fatal: (vsim-8568) Unbounded or undetermined
cp_flag: coverpoint data [24] {
bins flag_trans = (1 => 0);
bins allother [] = default sequence;
}
cp_flag: coverpoint data[24] {
bins flag_trans = (1 => 0);
ignore_bins allother = default sequence;
}
cp_thr: coverpoint data [11:8] {
bins thr_val_0 = {0};
bins thr_val_1 = {1};
}
cp_reg_addr: coverpoint addr {
bins reg_addr_1 = {12’h01C};
bins reg_addr_2 = {12’h020};
}
cr_thr_addr: cross cp_thr, cp_reg_addr {
bins thr_add = binsof(cp_reg_addr) intersect {12’h01C};
}
40
Solution: During non-consecutive repetition, any number
of sample points can occur before the first occurrence of
the specified value and between each occurrence of the
specified value. The transition following the non-consecutive
repetition may occur after any number of sample points, as
long as the repetition value does not occur again.
As length varies for non-consecutive repetition, you cannot
determine it. So you should avoid using the multiple bin
construct (the [] notation) with non-consecutive repetition.	
Here, in flag_trans bins 0[=3] is the same as … 0 => …=>
0…=> 0 means any number of sample points can occur
before the occurrence and between each occurrence of the
specified value. But as you have specified bins flag_trans as
static bin, it will avoid returning a fatal error.
AVOID USE OF DEFAULT
As per LRM, the default specification defines a bin that is
associated with none of the defined value bins. It catches
the coverage point values that do not lie within any of the
defined bins.
Problem-1: If you use multiple bin construct (the [] notation)
then it will create a separate bin for each value.
In following example, the first bin construct associates bin
rsvd_bit with the value of zero. Every value that does not
match bins rsvd_bit is added to its own distinct bin.
But as mentioned above, if the coverage point has a large
number of values and you run simulation for it, then the
simulator crashes and it gives the following fatal error:
Here the question is: Do you really need 2147483647 values?
Solution:
Use default without multiple bin construct (the []
notation): If you use default without multiple bin construct
for large values, then it will a create single bin for all values,
thus avoiding fatal errors.
Use ignore_bins: If you use ignore_bins construct for large
values then it will ignore unnecessary large values, similarly
avoiding fatal errors.
Problem-2: Coverage calculation for a cover point shall not
take into account the coverage captured by the default bin,
which is also excluded from cross coverage.
In following example, for data cover point, bins thr_val is
specified as default. So values 0 to 15 are added into its
own distinct bin. Also data cover point is used in cross
coverage with addr cover point.
varying length sequences formed using Repetitive/
Consecutive operators are not allowed in unsized Array
Transition bins. A transition item in bin ‘err_flag’ of Coverpoint
‘cp_err_flag’ in Covergroup instance ‘/tx_env_pkg::tx_
coverage::cg_err_ctrl_status_reg ‘ has an operator of kind ‘[=
]’. Please fix it
cp_flag: coverpoint data[24] {
bins flag_trans = (1 => 0[=3]);
}
cp_rsvd_bit: coverpoint data[31:13] iff (trans == pkg::READ) {
bins rsvd_bit = {0};
bins others = default;
}
cp_rsvd_bit: coverpoint data[31:13] iff (trans == pkg::READ) {
bins rsvd_bit = {0};
ignore_bins ig_rsvd_bit = {[1:$]};
# ** Fatal: The number of singleton values exceeded the
system limit of 2147483647 for unconstrained array bin ‘other’
in Coverpoint
‘data’ of Covergroup instance ‘/covunit/cg_err_reg’.
cp_rsvd_bit: coverpoint data[31:13] iff (trans == pkg::READ) {
bins rsvd_bit = {0};
bins others[] = default;
}
cp_thr: coverpoint data[11:8] {
bins thr_val_ 0 = 0;
bins thr_val[15] = default;
}
cp_reg_addr: coverpoint addr {
bins reg_addr_1 = {12’h01C};
bins reg_addr_2 = {12’h020};
}
cr_thr_addr : cross cp_thr, cp_reg_addr;
41
Here, data cover point has no coverage because bins are
specified using “default;” also there is no cross coverage
because we don’t have coverage for data cover point.
Solution:
Use wildcard bins: This captures combinations
of all possible values.
Use min/max ($) operators: It specifies minimum
or maximum values range.
AVOID USE OF ILLEGAL_BINS
If you specify any bin as illegal_bins, this will remove
unused or illegal values from the overall coverage
calculation.
Problem: In the following example, during the read
operation the reserved bit value should be zero;
any other value will return an error.
In this scenario, certain questions arise:
Question-1: Is it reasonable to rely on a passive
component to capture an active error? If you want to
capture active errors using illegal_bins and do not use
a passive coverage component (i.e. if you turn it off and
use only an active component), you will not capture any
active errors.
Solution-1:
Use assertion and checkers to capture active errors:
If you want to capture active errors then you can do so
using assertion and checkers. This will throw errors; the
problem of relying on a passive component to capture
active errors will be resolved.
Note:
1. If you have defined checkers and assertions and
still want to cross check for any run time error through
passive component, you can also use illegal_bins.
2. If you are sure of any scenario that should not occur
in any condition, then you can use illegal_bins.
Question-2: How to avoid such condition without using
illegal_bins?
Solution-2:
Use ignore_bins: This ignores other values and does
not throw any type of active errors. Also, it excludes
those values from overall coverage.
We hope these suggestions are useful in your verification
efforts!
cp_thr: coverpoint data[11:8] {
bins thr_val_ 0 = 0;
wildcard bins thr_val_wc = {[4’b???1]};
}
cp_thr: coverpoint data[11:8] {
bins thr_val_ 0 = 0;
bins thr_val_op = {[1:$]};;
}
cp_rsvd_bit: coverpoint data[31:25] iff (trans ==
pkg::READ) {
bins rsvd_bit = {0};
ignore_bins ig_rsvd_bit = {[1:$]};
}
cp_rsvd_bit: coverpoint data[31:25] iff (trans ==
pkg::READ) {
bins rsvd_bit = {0};
illegal_bins il_rsvd_bit = {[1:$]};
}
VERIFICATION
ACADEMYThe Most Comprehensive Resource for Verification Training
21 Video Courses Available Covering
• Intelligent Testbench Automation
• Metrics in SoC Verification
• Verification Planning
• Introductory, Basic, and Advanced UVM
• Assertion-Based Verification
• FPGA Verification
• Testbench Acceleration
• PowerAware Verification
• Analog Mixed-Signal Verification
UVM and Coverage Online Methodology Cookbooks
Discussion Forum with more than 5000 topics
UVM Connect and UVM Express Kits
www. verificationacademy.com
21 Video Courses Available Covering
• Intelligent Testbench Automation
• Metrics in SoC Verification
• Verification Planning
• Introductory, Basic, and Advanced UVM
• Assertion-Based Verification
• FPGA Verification
• Testbench Acceleration
• PowerAware Verification
• Analog Mixed-Signal Verification
UVM and Coverage Online Methodology Cookbooks
Discussion Forum with more than 5000 topics
UVM Connect and UVM Express Kits
www. verificationacademy.com
Editor: Tom Fitzpatrick
Program Manager: Rebecca Granquist
Wilsonville Worldwide Headquarters
8005 SW Boeckman Rd.
Wilsonville, OR 97070-7777
Phone: 503-685-7000
To subscribe visit:
www.mentor.com/horizons
To view our blog visit:
VERIFICATIONHORIZONSBLOG.COM

More Related Content

PPTX
AXI Protocol.pptx
PPTX
Ambha axi
PDF
System verilog important
PDF
Session 8 assertion_based_verification_and_interfaces
PPTX
System verilog assertions
ODP
APB protocol v1.0
PPT
SystemVerilog Assertions verification with SVAUnit - DVCon US 2016 Tutorial
PDF
System Verilog Functional Coverage
AXI Protocol.pptx
Ambha axi
System verilog important
Session 8 assertion_based_verification_and_interfaces
System verilog assertions
APB protocol v1.0
SystemVerilog Assertions verification with SVAUnit - DVCon US 2016 Tutorial
System Verilog Functional Coverage

What's hot (20)

PDF
Doulos coverage-tips-tricks
PDF
Verification Strategy for PCI-Express
PPTX
ODP
PPTX
System verilog coverage
PPT
Axi protocol
PDF
System verilog verification building blocks
PDF
Pci express modi
PPTX
Axi protocol
PPT
AMBA_APB_pst
PPTX
Verilog
PPTX
SOC Verification using SystemVerilog
ODP
Pc ie tl_layer (3)
PDF
Session 8,9 PCI Express
PPTX
AMBA 2.0 PPT
PDF
Uvm presentation dac2011_final
PPTX
Introduction about APB Protocol
PDF
Ral by pushpa
PDF
How to create SystemVerilog verification environment?
Doulos coverage-tips-tricks
Verification Strategy for PCI-Express
System verilog coverage
Axi protocol
System verilog verification building blocks
Pci express modi
Axi protocol
AMBA_APB_pst
Verilog
SOC Verification using SystemVerilog
Pc ie tl_layer (3)
Session 8,9 PCI Express
AMBA 2.0 PPT
Uvm presentation dac2011_final
Introduction about APB Protocol
Ral by pushpa
How to create SystemVerilog verification environment?
Ad

Viewers also liked (15)

PDF
Presentation slides: "How to get 100% code coverage"
PDF
Unit Testing Done Right
PPTX
Code Coverage and Test Suite Effectiveness: Empirical Study with Real Bugs in...
PPT
What's with All This Talk About Coverage?
PPTX
Comparing model coverage and code coverage in Model Driven testing: an explor...
PDF
Tools and techniques of code coverage testing
PDF
Pragmatic Code Coverage
PPT
Code Coverage in Theory and in practice form the DO178B perspective
PPTX
IoT 개발자를 위한 Embedded C에서 Test Coverage를 추출해보자
PDF
Session 7 code_functional_coverage
PPTX
Code coverage analysis in testing
 
PDF
Code coverage
PDF
Code Coverage
PPT
Code coverage
PPTX
Test Strategy
Presentation slides: "How to get 100% code coverage"
Unit Testing Done Right
Code Coverage and Test Suite Effectiveness: Empirical Study with Real Bugs in...
What's with All This Talk About Coverage?
Comparing model coverage and code coverage in Model Driven testing: an explor...
Tools and techniques of code coverage testing
Pragmatic Code Coverage
Code Coverage in Theory and in practice form the DO178B perspective
IoT 개발자를 위한 Embedded C에서 Test Coverage를 추출해보자
Session 7 code_functional_coverage
Code coverage analysis in testing
 
Code coverage
Code Coverage
Code coverage
Test Strategy
Ad

Similar to Functional Coverage Development Tips - Mentor Graphics (20)

PDF
Exploring Microoptimizations Using Tizen Code as an Example
PDF
System verilog Coverage including types.pdf
PDF
Bound and Checked
PPTX
Advanced Computer Programming..pptx
PDF
Analyzing the Blender project with PVS-Studio
PPT
VB Script Overview
PDF
Checking the code of Valgrind dynamic analyzer by a static analyzer
PDF
The Uniform Access Principle
PDF
PVS-Studio team is about to produce a technical breakthrough, but for now let...
PPTX
Instant DBMS Homework Help
PDF
Mid term sem 2 1415 sol
PDF
Accord.Net: Looking for a Bug that Could Help Machines Conquer Humankind
DOCX
systemverilog-interview-questions.docx
PPTX
WINSEM2016-17_CSE1002_LO_1336_24-JAN-2017_RM003_session 10.pptx
PDF
DATABASE AND FILE MANAGEMENT SYSTEMS / TUTORIALOUTLET DOT COM
PPT
C# features
PDF
Visual binning
PPTX
Recipe 5 of Data Warehouse and Business Intelligence - The null values manage...
PDF
Flag Waiving
Exploring Microoptimizations Using Tizen Code as an Example
System verilog Coverage including types.pdf
Bound and Checked
Advanced Computer Programming..pptx
Analyzing the Blender project with PVS-Studio
VB Script Overview
Checking the code of Valgrind dynamic analyzer by a static analyzer
The Uniform Access Principle
PVS-Studio team is about to produce a technical breakthrough, but for now let...
Instant DBMS Homework Help
Mid term sem 2 1415 sol
Accord.Net: Looking for a Bug that Could Help Machines Conquer Humankind
systemverilog-interview-questions.docx
WINSEM2016-17_CSE1002_LO_1336_24-JAN-2017_RM003_session 10.pptx
DATABASE AND FILE MANAGEMENT SYSTEMS / TUTORIALOUTLET DOT COM
C# features
Visual binning
Recipe 5 of Data Warehouse and Business Intelligence - The null values manage...
Flag Waiving

More from eInfochips (An Arrow Company) (20)

PDF
ASIC Design Solution & Challenges for Shorter TTM [Infographic]
PDF
Bringing Internet of Things to Life with ARM Architecture | eInfochips
PPTX
World's 1st successful porting of Android 4.4.4 on a PowerPC architecture - f...
PPTX
Whitepaper - Transforming the Energy & Utilities Industry with Smart Analytics
PPTX
eInfochips Semicon - Trust the Experts
PPTX
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
PDF
Top 10 Design Innovations for 2015 from eInfochips
PDF
Infographic: Technology Stack - Internet of Things
PDF
Connected Worlds - Internet of Things and Big Data
PDF
Infographics 8 factors to evaluate while considering open source
PPTX
Physical Design Services
PDF
Webinar - How To Drive Promotions To Your Magento eCommerce Store
PPTX
Board Design and System Software
PDF
9 Promotional Modules Your e-commerce Portal Should Have
PDF
Retail Site Intelligence
PPTX
Designer Pulse: Medical Device Developers Survey
PPTX
eInfochips Semiconductor Services
PDF
eInfochips IoT Infograph
PPTX
Seizing the day in wearable devices
PDF
Medical devices capabilities
ASIC Design Solution & Challenges for Shorter TTM [Infographic]
Bringing Internet of Things to Life with ARM Architecture | eInfochips
World's 1st successful porting of Android 4.4.4 on a PowerPC architecture - f...
Whitepaper - Transforming the Energy & Utilities Industry with Smart Analytics
eInfochips Semicon - Trust the Experts
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Top 10 Design Innovations for 2015 from eInfochips
Infographic: Technology Stack - Internet of Things
Connected Worlds - Internet of Things and Big Data
Infographics 8 factors to evaluate while considering open source
Physical Design Services
Webinar - How To Drive Promotions To Your Magento eCommerce Store
Board Design and System Software
9 Promotional Modules Your e-commerce Portal Should Have
Retail Site Intelligence
Designer Pulse: Medical Device Developers Survey
eInfochips Semiconductor Services
eInfochips IoT Infograph
Seizing the day in wearable devices
Medical devices capabilities

Recently uploaded (20)

PDF
Encapsulation theory and applications.pdf
PDF
Dropbox Q2 2025 Financial Results & Investor Presentation
PPTX
MYSQL Presentation for SQL database connectivity
PDF
Per capita expenditure prediction using model stacking based on satellite ima...
PPTX
Detection-First SIEM: Rule Types, Dashboards, and Threat-Informed Strategy
PDF
Chapter 3 Spatial Domain Image Processing.pdf
PDF
Reach Out and Touch Someone: Haptics and Empathic Computing
PDF
Review of recent advances in non-invasive hemoglobin estimation
PPTX
Spectroscopy.pptx food analysis technology
PDF
Profit Center Accounting in SAP S/4HANA, S4F28 Col11
PPTX
VMware vSphere Foundation How to Sell Presentation-Ver1.4-2-14-2024.pptx
PPT
Teaching material agriculture food technology
PDF
Encapsulation_ Review paper, used for researhc scholars
PDF
Spectral efficient network and resource selection model in 5G networks
PDF
Empathic Computing: Creating Shared Understanding
PPTX
sap open course for s4hana steps from ECC to s4
PDF
How UI/UX Design Impacts User Retention in Mobile Apps.pdf
DOCX
The AUB Centre for AI in Media Proposal.docx
PPTX
ACSFv1EN-58255 AWS Academy Cloud Security Foundations.pptx
PPTX
KOM of Painting work and Equipment Insulation REV00 update 25-dec.pptx
Encapsulation theory and applications.pdf
Dropbox Q2 2025 Financial Results & Investor Presentation
MYSQL Presentation for SQL database connectivity
Per capita expenditure prediction using model stacking based on satellite ima...
Detection-First SIEM: Rule Types, Dashboards, and Threat-Informed Strategy
Chapter 3 Spatial Domain Image Processing.pdf
Reach Out and Touch Someone: Haptics and Empathic Computing
Review of recent advances in non-invasive hemoglobin estimation
Spectroscopy.pptx food analysis technology
Profit Center Accounting in SAP S/4HANA, S4F28 Col11
VMware vSphere Foundation How to Sell Presentation-Ver1.4-2-14-2024.pptx
Teaching material agriculture food technology
Encapsulation_ Review paper, used for researhc scholars
Spectral efficient network and resource selection model in 5G networks
Empathic Computing: Creating Shared Understanding
sap open course for s4hana steps from ECC to s4
How UI/UX Design Impacts User Retention in Mobile Apps.pdf
The AUB Centre for AI in Media Proposal.docx
ACSFv1EN-58255 AWS Academy Cloud Security Foundations.pptx
KOM of Painting work and Equipment Insulation REV00 update 25-dec.pptx

Functional Coverage Development Tips - Mentor Graphics

  • 1. 38 INTRODUCTION The fundamental goal of a verification engineer is to ensure that the Device Under Test (DUT) behaves correctly in its verification environment. As chip designs grow larger and more complex with thousands of possible states and transitions, a comprehensive verification environment must be created that minimizes development effort. To minimize effort, functional coverage is used as a guide for directing verification resources by identifying tested and untested portions of the design. The approach should give any verification engineer confidence in DUT functionality. Functional coverage is a user-defined coverage which maps each functionality defined in the test plan to be tested to a cover point. Whenever the functionality to be tested is hit in the simulation, the functional coverage point is automatically updated. A functional coverage report can be generated which summarizes how many coverage points were hit. Functional coverage metrics can be used to measure the progress of a verification effort. The key aspects of functional coverage are as follows: • It is user-specified and not automatically inferred from the design. • It is based on the design specification and is thus independent of the actual design code or its structure. This article represents some of the important features of a functional coverage model that will be useful for verification engineers to develop a functional coverage model with high quality. The scenarios discussed subsequently cover some of the finer aspects of using these constructs more productively. USE OF DEFAULT SEQUENCE FOR TRANSITION COVERAGE Similar to ‘Default Construct’ which is useful for catching unplanned or invalid values, ‘Default Sequence’ is used to catch all transitions (or sequences) that do not lie within any of the defined transition bins. When any non-default sequence transition is incremented or any previously specified bin transition is not in pending state, then ‘bin allother’ of that cover point will be incremented. In the following example, the transition from value 1 to 0 is specified by bins flag_trans. So if any transition occurs from 1 to 0, then it will be captured by flag_trans bins. Here, by using default sequence (shown on the next page) you can capture other transitions that are not specified exclusively. Figure 1: Functional Coverage Flow Diagram Functional Coverage Development Tips: Do’s and Don’ts by Samrat Patel & Vipul Patel, eInfochips
  • 2. 39 While using default sequence, avoid the following scenarios: Scenario-1: The default sequence specification does not accept multiple transition bins (the [] notation). It will give an error. Therefore, avoid using a default sequence with multiple transition bins. Scenario-2: The default sequence specification cannot be explicitly ignored. It will be an error for bins designated as ignore_bins to specify a default sequence. Therefore, avoid using a default sequence with ignore_bins. EXCLUSION OF CROSS COVERAGE AUTO GENERATED BINS Problem: Suppose the requirement is to do cross coverage between two cover points and capture only specific user-defined bins as follows: In the above example, the coverage report will capture user-defined bins along with auto-generated bins. However, the requirement is to capture only specific user bins. The limitation of cross coverage is that even on specifying only user bins, it will also generate cross coverage bins automatically. Solution: To disable auto generated cross bins, you should use ignore_bins as shown below: Another way is that instead of specifying user-defined bins, simply use ignore_bins. This will ignore other bins except required user-defined bins so we can get the expected result. AVOID USING MULTIPLE BIN CONSTRUCT (THE [] NOTATION) WITH NON-CONSECUTIVE REPETITION The non-consecutive repetition is specified using trans_item [= repeat_range]. The required number of occurrences of a particular value is specified by the repeat_range. Problem: Using non-consecutive repetition with multiple bins construct (the [] notation) gives a fatal run time error as follows: cp_flag: coverpoint data [24] { bins flag_trans = (1 => 0); bins allother = default sequence; } cr_thr_addr: cross cp_thr, cp_reg_addr { bins thr_add = binsof(cp_reg_addr) intersect {12’h01C}; ignore_bins thr_add_ig = !binsof(cp_reg_addr) intersect {12’h01C}; } cr_thr_addr: cross cp_thr, cp_reg_addr { ignore_bins thr_add = binsof(cp_reg_addr) intersect {12’h020}; } cp_flag: coverpoint data [24] { bins flag_trans[] = (1 => 0[=3]); } Simulation Error: # ** Fatal: (vsim-8568) Unbounded or undetermined cp_flag: coverpoint data [24] { bins flag_trans = (1 => 0); bins allother [] = default sequence; } cp_flag: coverpoint data[24] { bins flag_trans = (1 => 0); ignore_bins allother = default sequence; } cp_thr: coverpoint data [11:8] { bins thr_val_0 = {0}; bins thr_val_1 = {1}; } cp_reg_addr: coverpoint addr { bins reg_addr_1 = {12’h01C}; bins reg_addr_2 = {12’h020}; } cr_thr_addr: cross cp_thr, cp_reg_addr { bins thr_add = binsof(cp_reg_addr) intersect {12’h01C}; }
  • 3. 40 Solution: During non-consecutive repetition, any number of sample points can occur before the first occurrence of the specified value and between each occurrence of the specified value. The transition following the non-consecutive repetition may occur after any number of sample points, as long as the repetition value does not occur again. As length varies for non-consecutive repetition, you cannot determine it. So you should avoid using the multiple bin construct (the [] notation) with non-consecutive repetition. Here, in flag_trans bins 0[=3] is the same as … 0 => …=> 0…=> 0 means any number of sample points can occur before the occurrence and between each occurrence of the specified value. But as you have specified bins flag_trans as static bin, it will avoid returning a fatal error. AVOID USE OF DEFAULT As per LRM, the default specification defines a bin that is associated with none of the defined value bins. It catches the coverage point values that do not lie within any of the defined bins. Problem-1: If you use multiple bin construct (the [] notation) then it will create a separate bin for each value. In following example, the first bin construct associates bin rsvd_bit with the value of zero. Every value that does not match bins rsvd_bit is added to its own distinct bin. But as mentioned above, if the coverage point has a large number of values and you run simulation for it, then the simulator crashes and it gives the following fatal error: Here the question is: Do you really need 2147483647 values? Solution: Use default without multiple bin construct (the [] notation): If you use default without multiple bin construct for large values, then it will a create single bin for all values, thus avoiding fatal errors. Use ignore_bins: If you use ignore_bins construct for large values then it will ignore unnecessary large values, similarly avoiding fatal errors. Problem-2: Coverage calculation for a cover point shall not take into account the coverage captured by the default bin, which is also excluded from cross coverage. In following example, for data cover point, bins thr_val is specified as default. So values 0 to 15 are added into its own distinct bin. Also data cover point is used in cross coverage with addr cover point. varying length sequences formed using Repetitive/ Consecutive operators are not allowed in unsized Array Transition bins. A transition item in bin ‘err_flag’ of Coverpoint ‘cp_err_flag’ in Covergroup instance ‘/tx_env_pkg::tx_ coverage::cg_err_ctrl_status_reg ‘ has an operator of kind ‘[= ]’. Please fix it cp_flag: coverpoint data[24] { bins flag_trans = (1 => 0[=3]); } cp_rsvd_bit: coverpoint data[31:13] iff (trans == pkg::READ) { bins rsvd_bit = {0}; bins others = default; } cp_rsvd_bit: coverpoint data[31:13] iff (trans == pkg::READ) { bins rsvd_bit = {0}; ignore_bins ig_rsvd_bit = {[1:$]}; # ** Fatal: The number of singleton values exceeded the system limit of 2147483647 for unconstrained array bin ‘other’ in Coverpoint ‘data’ of Covergroup instance ‘/covunit/cg_err_reg’. cp_rsvd_bit: coverpoint data[31:13] iff (trans == pkg::READ) { bins rsvd_bit = {0}; bins others[] = default; } cp_thr: coverpoint data[11:8] { bins thr_val_ 0 = 0; bins thr_val[15] = default; } cp_reg_addr: coverpoint addr { bins reg_addr_1 = {12’h01C}; bins reg_addr_2 = {12’h020}; } cr_thr_addr : cross cp_thr, cp_reg_addr;
  • 4. 41 Here, data cover point has no coverage because bins are specified using “default;” also there is no cross coverage because we don’t have coverage for data cover point. Solution: Use wildcard bins: This captures combinations of all possible values. Use min/max ($) operators: It specifies minimum or maximum values range. AVOID USE OF ILLEGAL_BINS If you specify any bin as illegal_bins, this will remove unused or illegal values from the overall coverage calculation. Problem: In the following example, during the read operation the reserved bit value should be zero; any other value will return an error. In this scenario, certain questions arise: Question-1: Is it reasonable to rely on a passive component to capture an active error? If you want to capture active errors using illegal_bins and do not use a passive coverage component (i.e. if you turn it off and use only an active component), you will not capture any active errors. Solution-1: Use assertion and checkers to capture active errors: If you want to capture active errors then you can do so using assertion and checkers. This will throw errors; the problem of relying on a passive component to capture active errors will be resolved. Note: 1. If you have defined checkers and assertions and still want to cross check for any run time error through passive component, you can also use illegal_bins. 2. If you are sure of any scenario that should not occur in any condition, then you can use illegal_bins. Question-2: How to avoid such condition without using illegal_bins? Solution-2: Use ignore_bins: This ignores other values and does not throw any type of active errors. Also, it excludes those values from overall coverage. We hope these suggestions are useful in your verification efforts! cp_thr: coverpoint data[11:8] { bins thr_val_ 0 = 0; wildcard bins thr_val_wc = {[4’b???1]}; } cp_thr: coverpoint data[11:8] { bins thr_val_ 0 = 0; bins thr_val_op = {[1:$]};; } cp_rsvd_bit: coverpoint data[31:25] iff (trans == pkg::READ) { bins rsvd_bit = {0}; ignore_bins ig_rsvd_bit = {[1:$]}; } cp_rsvd_bit: coverpoint data[31:25] iff (trans == pkg::READ) { bins rsvd_bit = {0}; illegal_bins il_rsvd_bit = {[1:$]}; }
  • 5. VERIFICATION ACADEMYThe Most Comprehensive Resource for Verification Training 21 Video Courses Available Covering • Intelligent Testbench Automation • Metrics in SoC Verification • Verification Planning • Introductory, Basic, and Advanced UVM • Assertion-Based Verification • FPGA Verification • Testbench Acceleration • PowerAware Verification • Analog Mixed-Signal Verification UVM and Coverage Online Methodology Cookbooks Discussion Forum with more than 5000 topics UVM Connect and UVM Express Kits www. verificationacademy.com 21 Video Courses Available Covering • Intelligent Testbench Automation • Metrics in SoC Verification • Verification Planning • Introductory, Basic, and Advanced UVM • Assertion-Based Verification • FPGA Verification • Testbench Acceleration • PowerAware Verification • Analog Mixed-Signal Verification UVM and Coverage Online Methodology Cookbooks Discussion Forum with more than 5000 topics UVM Connect and UVM Express Kits www. verificationacademy.com
  • 6. Editor: Tom Fitzpatrick Program Manager: Rebecca Granquist Wilsonville Worldwide Headquarters 8005 SW Boeckman Rd. Wilsonville, OR 97070-7777 Phone: 503-685-7000 To subscribe visit: www.mentor.com/horizons To view our blog visit: VERIFICATIONHORIZONSBLOG.COM