ASIC Design Flow

Intro Flow First Front Back PVR Final
ASIC Design Flow
How to design your own chip
Ahmed Abdelazeem
Faculty of Engineering
Zagazig University
RTL2GDSII Flow, February 2022
Ahmed Abdelazeem Introduction to ASIC Design

Intro Flow First Front Back PVR Final
Table of Contents
1 Introduction
2 Overall Design Flow
3 First steps to design
4 Front-end
5 Back-end Design
6 Physical Verification?
7 Final Words

Intro Flow First Front Back PVR Final Design What Tradeoffs Examples ASICs
Table of Contents
1 Introduction
4 Front-end
5 Back-end Design
7 Final Words

The Life of a CMOS Inverter

Design Implementation Flow
Much like the simple CMOS inverter, the general process of digital
design implementation is the transformation of a design into
various representations,eventually into physical hardware devices,
just on a much BIGGER scale.

What is Hardware Design ?
Physically implementing an idea, a function, a system in hardware.

What is Hardware Design ?
Physically implementing an idea, a function, a system in hardware.
Find the optimal balance between:
Cost / Area
Speed / Throughput
Energy Consumption / Power Density
Design Time

Trade-offs in Design
No free lunch
Depending on the design, some parameters are more important.
You can generally sacrifice one parameter to improve the other:

No free lunch
Speed vs Area
It is possible to speed up a circuit by using larger transistors,
parallel computation blocks

No free lunch
Speed vs Area
It is possible to speed up a circuit by using larger transistors,
parallel computation blocks
Design time vs Performance
Given enough time, the circuits can be optimized for higher
performance

What is Important for the Following Designs ?

Application Specific Integrated Circuits
When to use ASICs ?
The good:
Highest performance
Cheap for mass
production
The bad:
Long development time
Not very configurable
Requires specialization

Intro Flow First Front Back PVR Final flow Implementation Physical Design
Table of Contents
1 Introduction
4 Front-end
5 Back-end Design
7 Final Words

Overall Design Flow

Implementation Flow
Front-end
Front-end chip design
definition:Processes in the
overall chip design flow that
involve system and logical design
and verification
Back-end
Back-end chip design
definition:Processes in the
overall chip design flow that
involve physical design and
verification

Implementation Flow
The terms “physical design”or “back end”or
“place/route”encompass many process steps, such as
Floorplanning
Placement
Clock Tree Synthesis (CTS)
Route
Extraction and Delay Calculation
Static Timing Analysis (STA)
EMIR
Formal Verification
Physical Verification
Mask Prep

Implementation Flow

Intro Flow First Front Back PVR Final Spec Feasibility Block trans
Table of Contents
1 Introduction
4 Front-end
5 Back-end Design
7 Final Words

What Is a Specification?
Ideas begin with a specification,
which can be a textual,
graphical, or sometimes a
software representation.
Definition: A specification
is an explicit set of
requirements to be satisfied
by a material, product,or
service.
Example: The specification
for the latest chip specified
a 250-MHz core clock with a
serial interface, able to
process 1 Mb of data per
second at less than 10W
total power.

Design Specification
A list of requirements
Function:
What is expected from the ASIC
Perfomance:
What speed, power, area ?
I/O requirements:
How will the ASIC fit together with
the system ?

We have specifications, but can we do it ?
Feasibility ?
For most of the projects:
We have never done it, so we don’t know exactly!
We may:
Have experience from earlier projects
Make small experiments to estimate performance
Choose appropriate technology

What Is a Microarchitecture?
Step between the specification
and RTL, the micro-architecture
defines how the block will be
implemented
Definition: The
microarchitecture
implements the specification
and defines specific
mechanisms and structures
for achieving that
implementation
Example: For Block A, the
designer created a
microarchitecture and
partitioned the block into
several smaller modules

Always Start with a Block Diagram
Iterative Process
Identify blocks
What do we need to perform
the functionality?

Iterative Process
Identify blocks
the functionality?
Visualize structure
How are blocks connected?

Iterative Process
Identify blocks
the functionality?
Visualize structure
Find critical paths
Which block is most critical
(speed, area, power)?

Iterative Process
Identify blocks
the functionality?
Visualize structure
Find critical paths
Which block is most critical
(speed, area, power)?
Divide and Conquer
Draw sub-block diagrams

Architectural Transformations
Efficiency
Performance parameters:
Area (mm2)
Clock rate (MHz)
Throughput(data/sec)
Latency(num clock cycles)
’

Parallelization
More computation
If we use 2 parallel blocks:
Area doubles
Clock stays same
Throughput doubles
Latency stays same
’

Pipelining
Faster computation
if we introduce one pipeline
stage:
Area increases a little
Clock doubles
Throughput doubles
Latency doubles
’

Iterative Decomposition
More clock cycles
If we can perform the operation
in two iterations:
Area halves
Clock stays same
Throughput halves
Latency doubles
’

Specification and Microarchitecture: Input and Output
Specification
Input: Requirements from Marketing, CEO
(Chief Executive Officer), CTO (Chief
Technology Officer), etc
Output: Document or model in text/graphics or
software (C++, SystemC, SystemVerilog, etc.)
format
Microarchitecture
Input: Specification + requirement from
designer
Output: Typically a document in text/graphics,
could be software as well

Example: Specification
Let’s assume we have a specification,
microarchitecture, and RTL.
We are designing a chip called “EX”
with
Three main partitions “A,” “B,”
and “C”
Memories in each partition
Perimeter I/O
250-MHz clock
10W total power
Die size not to exceed 10x10 mm2
due to custom package
requirements

Example: Microarchitecture
For Block C
32-bit data bus interface to Block
A
16-bit control interface from Block
B
Use 64 Mb of SRAM
Duplicate datapath elements in a
parallel implementation
Limit of five clock cycles from data
input processed to data output

Intro Flow First Front Back PVR Final Modelling HDL Sim Testb. Ver. Synth. Cell
Table of Contents
1 Introduction
4 Front-end
5 Back-end Design
7 Final Words

Building a Model
Make sure your system works
There are many languages that can be used for modelling:
C, C++, SystemC
Perl, Java, Tcl
Matlab
systemVerilog, Verilog, VHDL
This is not a religion, there is not one definitive answer.
Choose whatever is suitable, not always whatever you are
comfortable with.

Model Types
Key words in modelling
There are many languages that can be used for modelling:
bit-true
The model mimicks the hardware at bit level. Numbers are
actually computed at the same accuracy as the hardware
cycle-true
The model accurately replicates how the hardware works for
every clock cycle.
transaction-based
A high level model that works on blocks of data. It calculates
the end result of the computation, intermediate steps are not
available
The model is an important part of simulation environment

Describing Hardware
Next Lecture
We will discuss this topic in a
second lecture
How to turn an idea into an
architecture
How to come up with a
block diagram
Converting block diagram
into Verilog, VHDL code
.

Simulating your Design
Does it actually work ?
Behavioral simulation
no delays for processing
No performance
parameters
only functionality is verified
Hardware description
Not every construct in
VHDL or Verilog can be
implemented in hardware.
This simulation will not
show this.
.

Testbenches

Verification
Bug hunting
Time consuming
The majority of design is verification
Exhaustive tests are not feasible
A 32 bit adder has 264 possible input combinations. If we
check 1.000.000.000 inputs per second it will take 200 days !!
Every line we write, has a potential for error
People talk about 1 bug every 20 lines of code.
Golden models can be wrong
Sometimes, your hardware description is correct, but your
model is wrong

What Is Logic Synthesis?
Definition: The process of
translating, optimizing, and
mapping RTL code into a
specified standard cell
library.
Example: To determine the
feasibility of the design, we
need to synthesize the RTL
code into gates and measure
timing, power, and area

Logic Synthesis Results
Synthesis is just a tool
Synthesis tools do not magically generate circuits
They are supposed to generate exactly the circuit that you
want
You must have a good idea of what the synthesis result will be

Logic Synthesis Results
Synthesis is just a tool
Synthesis tools do not magically generate circuits
They are supposed to generate exactly the circuit that you
want
You must have a good idea of what the synthesis result will be
If the result is not as you expect, you should convince the
synthesizer to produce the correct result.

Different constraints, different circuits

Don’t trust the synthesizer too much

Logic Synthesis: Input and Output
Inputs:
1 RTL in the Verilog
language or other HDL
2 Constraints in Synopsys
Design Constraints (SDC)
3 Timing Libraries in
Liberty (.lib)
Output:
1 Gate Level Netlist(.v)

Example: Logic Synthesis
Now that we have a working code, convert into hardware

Standard Cell Libraries
Collection of pre-designed gates
simple logic functions
and, or, xor, not, nand, nor
complex logic functions
adders, and-or-invert
sequential elements
latches, flip-flops
different drive strengths
Each cell has at least 2-4
variations with different
current driving capabilities
.

Standard Cells - 2

Standard Cell Rows

Intro Flow First Front Back PVR Final Goals Floor Power Place CTS Rout Extr Opt
Table of Contents
1 Introduction
4 Front-end
5 Back-end Design
7 Final Words

Back-end Design
Now that we have a netlist, let us convert it to a physical layout

What Is Floorplanning?
Definition: Process of
derivingthe die size,
allocating space forsoft
blocks, planning power,
andmacro placement.
Example: The three blocks
of the chip were
floorplanned to minimize the
distance between the I/Os
of the blocks and their
interfaces to the chip. This
reduces the routing between
the blocks and, thus,
improves the timing and
routability of the design.
. Ahmed Abdelazeem Introduction to ASIC Design

Floorplanning: Input and Output
Inputs:
1 Gate Level Netlist
2 Constraints in Synopsys
Design Constraints (SDC)
3 Logical Timing Libraries
in Liberty (.lib)
4 Physical Libraries in LEF
format
5 Floorplan constraints and
script in TCL
Outputs:
1 Floorplanned design in
the Verilog language
(logical connectivity data)
or other HDL + DEF
(physical data)

Floorplaning
How will the chip look
Determine the total
area/geometry of the chip
Place the I/O cells
Place pre-designed macro
blocks
Leave room for routing,
optimizations, power
connections

Floorplaning
How will the chip look
Determine the total
area/geometry of the chip
Place the I/O cells
Place pre-designed macro
blocks
Leave room for routing,
optimizations, power
connections
iterative process, can not
determine the perfect
floorplan from the beginning

Power Planning

What Is Placement?
Definition: Process of
placing the standard cells in
a floorplanned design.
Example: After the chip
was floorplanned, we
performed placement and
discovered the floorplan was
too small to fit all of the
cells and macros in the
design.
Question: How can we
avoid this problem?
.

Placing Standard Cells
NP hard problem
Critical path is minimum
Long interconnections on the critical path add capacitance
The design is routable
Not all placements can be routed.
The area is minimum
The routing overhead inreases area.

What is Clock Tree Synthesis
Definition: Process
ofinserting buffers in the
clockpath, with the goal
ofminimizing clock skew
andlatency to optimize
timing
Example: We ran clock
treesynthesis on the
exampleblock and saw a
large clockskew due to bad
clockconstraints. We ended
up re-running clock tree
synthesiswith better
constraints to getan optimal
result.
. Ahmed Abdelazeem Introduction to ASIC Design

Clock Distribution
Clock is the most critical signal
Standard digital systems rely on the clock signal being
present everywhere on the chip at the same time: skew
Clock signal has to be connected to all flip-flops: high fan out
Specialized tools insert multi level buffers (to drive the load)
and balance the timing by ensuring the same wire length for
all connection

Clock Distribution
Clock is the most critical signal
Standard digital systems rely on the clock signal being
present everywhere on the chip at the same time: skew
Clock signal has to be connected to all flip-flops: high fan out
Specialized tools insert multi level buffers (to drive the load)
and balance the timing by ensuring the same wire length for
all connection
The following example is a 200 MHz 3D image renderer with
roughly 3 million transistors. The clock distribution has:
1 10.928 flip-flops
2 9 level clock tree
3 478 buffers in the clock tree
4 34 cm total clock wiring

What Is Route?
Definition: Process of connecting
the pins of the standard cells,
macros, and I/Os of a digital
design to specific metal layers in
the process technology to match
the schematic
Example: We ran a preliminary
route on the example block and
saw that routing congestion was an
issue. To fix it, we re-ran
placement with a placement
density screen to force a lower
utilization in that area and allow
for more routing resources.
.

Routing
Determine interconnection
Multiple (3-9) metal routing
layers. Signals on different
layers do not intersect.
Vias to interconnect metals
on adjacent layers.
The longer the
interconnection:
The more the capacitance
The slower the connection
The more the power
consumption
Thin wires, vias add
resistance

Extraction
Definition: Process of calculating
the parasitic resistance and
capacitance of the interconnect of
the physical design
Example: Extraction can be
performed at various parts of the
design with varying accuracy. The
most accurate results are achieved
when extraction is performed on a
fully routed design, because all of
the nets are of known metal type
and length. There are no
.

Extraction
Timing information depends on interconnect
Once the physical design is complete, everything about the
interconnection network is known. It is possible to extract parasitic
capacitance for the interconnection
Wire capacitance
Wire to wire capacitance
Wire - via resistance
The extracted information can be used to extract timing
information. It can be stored in special files (SDF, SPEF) and can
be used by circuit simulators.

Optimization
Final timing with parasitics
Parasitics may influence timing severely. It is possible to make
local optimizations to combat additional capacitance:
Buffers are added to long connections
Driver strength of the standard cells is adjusted
Incremental change of placement
Critical paths are resynthesized

Intro Flow First Front Back PVR Final PVR DRC LVS EMIR STA Formality Tape-out
Table of Contents
1 Introduction
4 Front-end
5 Back-end Design
7 Final Words

What Is Design/Physical Verification?
Definition: Layout versus schematic (LVS)and
design rule check (DRC) and power (IR drop
and EM) are signoff checks run to ensure the
integrity, functionality, and manufacturability of
the chip.
LVS is a comparison of transistor-level SPICE
netlist vs. GDSII to ensure the connectivity of
the design.
DRC is a detailed check of the physical design
against the process technology rules.
IR drop is a detailed check of the chip’s power
plan to ensure that the supply voltages do not
drop below accepted levels.
EM is a detailed check to ensure that the
current density in all parts of the design does
not exceed accepted levels.
.

DRC: Input and Output, Format
Input
GDSII
Rule deck
Output
DRC reports

Design Rule Check
Production rules
Every physical layer has limits
that are determined by the
production flow. These include
MMinimum spacing
Minimum width
Minimum coverage
Minimum area

LVS: Input and Output, Format
Input
Gate Level Netlist
GDSII
Rule deck
SPICE libraries
Output
LVS reports

Layout Versus Schematic
Is the layout equivalent to schematic
The physical layout contains only geometric information
The devices (transistors) and interconnections are extracted.
This is the extracted netlist
The extracted netlist is compared to the initial netlist that we
started with.
Shorts between layers can be detected in this stage.
Very important step, this step tells us that the chip is good
to go.

Power Grid Analysis, IR Drop, and EM: Input and Output
Input
Gate Level Netlist + DEF
Power characterized libraries in
tool-specific
Timing libraries in Liberty (.lib)
Timing constraints in SDC
Extraction data in SPEF format
Timing windows file (TWF)
Value-change-dump file
(optional)
Output
IR drop reports
EM reports

Static Time Analysis Input and Output
Input
Routed Gate Level Netlist
Timing libraries in Liberty
(.lib)
Timing constraints in
SDC
SPEF, SDF, and
incremental SDF
Timing windows file
(TWF)
Value-change-dump file
(optional)
Output
Timing reports, including
noise-on-delay effects

Formal Verification Input and Output
Input
Reference Design (RTL
Code)
Implementation Design
(Gate-Level Netlist)
Setup Verification Format
Output
Reports

Chip is Finished, Now Time For Fun

Tape-out
Final stage of the design
In old times, the design data was transferred using magnetic
tapes, hence the name
The geometric data is electronically transfered to the
production site
Usually there will be an independent DRC check if problems
are found, we get asked to correct the problems
Then we wait 10-14 weeks for production.
Tape-out dates are well-known in advance, and are not
negotiable. You have to finish by the given date, no mercy!

Intro Flow First Front Back PVR Final Chip Testing Summary Nice
Table of Contents
1 Introduction
4 Front-end
5 Back-end Design
7 Final Words

Your Very Own Chip

Testing
Now that we have our chip back
Does it really work ?

Summary of the Design Flow

A Good Looking Chip Will Always Work

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ASIC Design Flow

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