associative mapping combined paging with segmentation.pptx
- 1. Associative Mapping The TLB only contains some of the page table entries so we cannot simply index into the TLB based on page number each TLB entry must include the page number as well as the complete page table entry The processor is equipped with hardware that allows it to interrogate simultaneously a number of TLB entries to determine if there is a match on page number • Dr Vatan sehrawat • Asst. Professor, Computer Science & engg department • RPSCET, Balana, Mahendragarh • vatansehrawat@gmail.com • 8059211113
- 2. Page Table Virtual Address Page # Offset 5 502 37 37 19 511 37 27 5 211 14 1 90 37 502 Frame # Offset Real Address (a) Direct mapping Page # PT Entries Virtual Address Page # Offset 5 502 Translation Lookaside Buffer 37 502 Frame # Offset Real Address (b) Associative mapping Figure 8.8 Direct Versus Associative Lookup for Page Table Entries
- 3. Virtual Address Page # Offset TLB Operation Figure 8.9 Translation Lookaside Buffer and Cache Operation Page Table Main Memory TLB miss Miss Hit Value TLB hit TLB Tag Remainder Real Address Cache Operation Cache + Value
- 4. Page Size The smaller the page size, the lesser the amount of internal fragmentation however, more pages are required per process more pages per process means larger page tables for large programs in a heavily multiprogrammed environment some portion of the page tables of active processes must be in virtual memory instead of main memory the physical characteristics of most secondary-memory devices favor a larger page size for more efficient block transfer of data
- 5. P (a) Page Size Figure 8.10 Typical Paging Behavior of a Program Page Fault Rate N W (b) Number of Page Frames Allocated Page Fault Rate P = size of entire process W = working set size N = total number of pages in process
- 6. Computer Page Size Atlas Honeywell-Multics 512 48-bit words 1024 36-bit words IBM 370/XA and 370/ESA VAX family 4 Kbytes 512 bytes IBM AS/400 DEC Alpha MIPS UltraSPARC Pentium IBM POWER Itanium 512 bytes 8 Kbytes 4 Kbytes to 16 Mbytes 8 Kbytes to 4 Mbytes 4 Kbytes or 4 Mbytes 4 Kbytes 4 Kbytes to 256 Mbytes Table 8.3 Example Page Sizes
- 7. Page Size Contemporary programming techniques used in large programs tend to decrease the locality of references within a process the design issue of page size is related to the size of physical main memory and program size main memory is getting larger and address space used by applications is also growing most obvious on personal computers where applications are becoming increasingly complex
- 8. Segmentation Segmentation allows the programmer to view memory as consisting of multiple address spaces or segments Advantages: • simplifies handling of growing data structures • allows programs to be altered and recompiled independently • lends itself to sharing data among processes • lends itself to protection
- 9. Segment Organization Each segment table entry contains the starting address of the corresponding segment in main memory and the length of the segment A bit is needed to determine if the segment is already in main memory Another bit is needed to determine if the segment has been modified since it was loaded in main memory
- 10. Seg # Seg # Offset = d Virtual address Register Seg Table Ptr Segment table Physical address Length Base Segment Base + d d Figure 8.11 Address Translation in a Segmentation System + + Program Segmentation mechanism Main memory
- 11. Combined Paging and Segmentation In a combined paging/segmentation system a user’s address space is broken up into a number of segments. Each segment is broken up into a number of fixed-sized pages which are equal in length to a main memory frame Segmentation is visible to the programmer Paging is transparent to the programmer
- 12. Seg # Seg# Seg Table Ptr Virtual Address Page # Offset Segment Table Page Table Page Frame Frame # Offset Offset Figure 8.12 Address Translation in a Segmentation/Paging System + + Page# Program Segmentation Mechanism Paging Mechanism Main Memory
- 13. Segment Number Page Number Offset Virtual Address Segment Table Entry (c) Combined segmentation and paging Page Table Entry Frame Number P MOther Control Bits Length Segment Base Control Bits P= present bit M = Modified bit
- 14. Protection and Sharing Segmentation lends itself to the implementation of protection and sharing policies Each entry has a base address and length so inadvertent memory access can be controlled Sharing can be achieved by segments referencing multiple processes