EEP306: Binary phase shift keying
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The document describes an experiment on Binary Phase Shift Keying (BPSK) aiming to generate a BPSK signal and study synchronous demodulation along with phase ambiguities. It details the phase changes in BPSK signals, the impact of noise on demodulated bits, and observations regarding phase transitions and delays. Various figures illustrate the modulation process, the effects of frequency changes, and the challenges faced in retrieving the correct bit sequence.
EEP306: Binary phase shift keying
- 1. Experiment BPSK-Binary Phase Shift Keying Aim: To generate a binary phase shift keyed signal; band limiting. To study synchronous demodulation –phase ambiguities Introduction: In phase shift keying (PSK), the phase of a carrier is changed according to the modulating waveform which is a digital signal. In BPSK, the transmitted signal is a sinusoid of fixed amplitude. It has one fixed phase when the data is at one level and when the data is at the other level, phase is different by 180 degree. A Binary Phase Shift Keying(BPSK) signal can be defined as Where b(t) = +1 or -1, fc is the carrier frequency, and T is the bit duration. The received signal has the form = , where is the phase shift introduced by the channel. The signal b(t) is recovered in the demodulator. If synchronous demodulation is used, the waveform is required at the demodulator. The recovered carrier is multiplied with the received signal to generate The signal is passed through a low pass filter and high frequency component is dumped. If the channel is noisy; some of the demodulated bits will be in error.
- 2. Observations and remarks: A phase change of 180 degree at every bit transition is observed. Fig. 1 Fig. 2
- 3. The multiplier output after modulation and original sequence. Note that it is mulitplied with carrier wave. Fig. 3 The demodulated sequence and the original sequence. A small delay is notable. Fig. 4
- 4. On increasing the frequency of input we get following output Fig 5 The graph of demodulated signal before and after switching phase changer. Fig. 6
- 5. On increasing the frequency the delay is clearly visible. Fig 7 Also on changing the DECISION MAKER, we got error in retreiving bit sequence, after proper tuning we get the sequnece correctly