cmos design and analysis-UNIT1............

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
1
SUBJECT: VLSI DESIGN
III BTECH II SEM ECE
By
Y.Pradeep
Associate Professor
UNIT I
Lecture-11 : CMOS INVERTER ANALYSIS & DESIGN

CMOS INVERTER ANALYSIS & DESIGN
Let consider a CMOS
INVERTER general
arrangement and
characteristics as
shown
in the figure:
2

• We have seen that, the current/voltage relationships for
the MOSFET may be written as,
in linear region (or) resistive region (or) non-saturated
region saturation.
3





















2
V
V
V
V
L
W
K
I
2
ds
ds
t
gs
ds
  saturation
in
2
W
K
ds
I t
gs V
V
L



• In both cases ‘k’ is a technology-dependent parameter
such that
• The factor contributed by the geometry of the FET,
so in common practice we write
•
4
D
μ
ε
ε
k 0
in

L
W
L
W
K
β 
saturation
in
2
β
I
as
expressed
also
is
I t
gs
ds
V
V
ds








p
p
p
0
in
p
n
n
n
0
in
n
L
W
D
μ
ε
ε
β
,
L
W
D
μ
ε
ε
β
:
follows
as
are
PMOSFET
NMOSFET,
both
for the
β'
'
where



With regard to figures(a) and
(b)it may be seen that , the
COMOSinverter has‘5’distinct
regions of operation.
Region1:- this is the region at
which Vin = logic ‘o’
pMOSFET is fully
turned‘ON’nMOSFET is fully
turned ‘OFF’ results in no
current flow through the
inverter andVout =VDD.
5

Region5:- this is the region at
which Vin =logic ‘1’ pMOSFET
is fully turned 'OFF’, nMOSFET
is fully turned‘ON’.Again results
in no current flow through the
inverter and Vout = 0,which is
good logic ‘0’.
6

• Region2:- In this region the i/p
voltage has increased to a level
which just more than the threshold
voltage of FET.
• The nMOSFET conducts and has a
large voltage between source and
drain, so it is in saturation and acts
as constant current source.
• The pMOSFET is also conducting
but with only a small voltage across
it and is operated in resistive region.
• A small current now flows
through the inverter from VDD to
Vss .
7

Vout
Idsp
Idsn
VDD

• Region 4:- This is similar to region ‘2’but the roles of p
and n- FET’s are reversed.
• Current magnitude is small.
8
Vout
Idsp
Idsn
VDD

• Region 3:- This is the region at which both FET’s are in
saturation.
9
Vout
Idsp
Idsn
VDD

• The current in each FET
must be same since FET’s
are in series so Idsp = -Idsn.
• Where
10
2
n
dsn in
V
2
β
I 




 

tn
V
2
tp
V
dd
V
in
V
2
p
β
dsp
I 









11
   
   
 
 
)
1
.......(
1
V
V
β
β
V
V
V
V
V
2
β
V
V
V
2
β
I
I
that
know
we
2
1
2
1
tn
in
p
n
tp
DD
in
2
tn
in
n
2
tp
DD
in
p
dsn
dsp
p
n
p
n
tn
tp
DD
in
tn
p
n
tp
DD
in
p
n
in
V
V
V
V
V
V
V
V
V





























• But in this region both FET’s are in saturation
acts as two current sources in series results in
‘unstable’ condition.
• A change over from one logic level to other is
rapid in this region.

12
Sec
V
2
cm
480
p
μ
,
Sec
V
2
cm
1250
n
μ
where
n
L
n
W
2.5
p
L
p
W
finally,
n
L
n
W
n
μ
p
L
p
W
p
μ
p
n β
β
equal
are
factors
β'
'
two
which
at
point
the
only
is
This
2
V
V
V
which
at
point
the
about
l
symmetrica
is
and
levels
logic
the
between
occur
will
over
change
a
2
V
V
At
equ(1)]
in
ng
substituti
[after
V
V
then
β
β
If
DD
out
in
DD
in
tn
tp
p
n















15
BICMOS inverter contd…
• T1,T2 drives the o/p load.
• CL is charged towards
5v-VBE of T2.
• CL is charged towards 0v.














ON
T
ON
T
OFF
T
OFF
T
Vin
2
4
1
3
,
0















OFF
T
OFF
T
ON
T
ON
T
5V,
V
2
4
1
3
in

16
n-substrate
p+ n+ n+ n+
p+
p+
n-well
p-substrate
Vss
VDD
Vout
Vin
Rwell
Vsub
Rsub
Vwell
Transient
Current
flow
Latch-up – Generation of low impedance path between VDD and VSS
due to the interaction of parasitic ‘pnp’ and ‘npn’ BJT’s.

18
Latch-up in CMOS ckts
• Latch-up – Generation of low impedance path
between VDD and VSS due to the interaction of
parasitic ‘pnp’ and ‘npn’ BJT’s.

19
Latch-up in CMOS ckts contd…
• This is due to the transient current flow through the
substrate when
(i) Power up.
(ii) External voltages are applied.

20
• Due to the transient current flow Vsub will raise which
turns ‘ON’ the ‘npn’ transistor.
• When ‘npn’ is ‘ON’ it pulls the current through the Rwell
and lowers the Vwell value which turns ‘ON’ the ‘pnp’.
VDD
Rsub
Rwell
Vsub
Vwell

21
• A +ve feedback is established causing a large current flow
between VSS & VDD.
• This large current flow continues until the power supply turned
off or the power wires melt.
VDD
Rsub
Rwell
Vsub
Vwell

22
Latch-up prevention
• Use p+ guard rings connected to VSS around
NMOS, n+ guard rings connected to VDD around
PMOS to reduce Rwell, Rsub.
• Place substrate and well contacts as close as
possible to the source connections of MOS
transistors to reduce Rwell, Rsub.
• Reduce the gain of the parasitic transistors.

cmos design and analysis-UNIT1............

More Related Content

Similar to cmos design and analysis-UNIT1............ (20)

More from PradeepYata1 (16)

Recently uploaded (20)

cmos design and analysis-UNIT1............