1. 1
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: VLSI DESIGN
By
Y.Pradeep
Associate Professor
UNIT I
Lecture-9: “Determination of pull-up to pull-down ratio
(Zp.u/Zp.d) for an NMOS inverters”
3. 3
Agenda
Determination of pull-up to pull-down ratio (Zp.u/Zp.d) for an
NMOS inverter driven by another NMOS Inverter
Pull-up to pull-down ratio (Zp.u / Zp.u )foran NMOS inverter
driven through one or more pass transistors
4. 4
Determination of pull-up to pull-down ratio(Zp.u/Zp.d) for an
NMOS inverter driven by another NMOS inverter
Consider the arrangement shown below in which an inverter driven
from the o/p of another similar inverter.
Vin = Vout = Vinv ,where Vinv = 0.5VDD
Depletion mode Transistor Vgs = 0 under all conditions.
When cascading logic devices care must be taken to preserve integrity of
logic levels
i.e. design circuit so that Vin = Vout = Vinv
5. 5
Vin
o/p
Depletion NMOS as a load and
enhancement mode NMOS as as a driver
- NMOS inverters
Vout Vin
Vin = Vout = Vinv
VDD
VDD
6. 6
2
t
V
p.d
L
p.d
W
K
I
V
V
transistor
mode
t
enhancemen
for
2
td
V
p.u
L
p.u
W
K
I
V
V
0,
V
transistor
mode
depletion
for
2
t
V
gs
V
L
W
K
I
saturation
in
are
inverter
NMOS
of
s
transistor
Both
2
ds
inv
gs
2
ds
td
t
gs
2
ds
inv
V
Assume equal margins around inverter; Vinv = 0.5 Vdd
7. 7
2
2
.
1
.
1
,
.
.
.
,
.
.
.
2
.
.
2
.
. 2
2
td
V
u
p
Z
t
V
inv
V
d
p
Z
u
p
W
u
p
L
Z u
p
d
p
W
d
p
L
Z
where d
p
td
V
u
p
L
u
p
W
t
V
inv
V
d
p
L
d
p
W
K
same
are
currents
Since
K
(Convention Z = L/W)
9. 9
Pull-up to pull-down ratio(Zp.u / Zp.u )foran NMOS inverter
driven through one or more pass transistors
Consider the arrangement shown below. All pass transistor gates connected
to VDD so there is a loss of Vtp i.e Vin2 = VDD – Vtp. (Vtp = pass transistor Vt )
It is often the case that two inverters are connected via a series of switches (Pass
Transistors)
We are concerned that connection of transistors in series will degrade the logic
levels into Inverter 2.
14. 14
Consider inverter1:
Case1: Pull up Transistor, It is a D-NMOSFET where Vgs =0
So it is operated directly in saturation region.
2
V
L
W
K
V
V
&
0
2
V
V
L
W
K
td
2
p.u1
p.u1
1
td
t
gs
t
gs
2
p.u1
p.u1
1 saturation
ds-
I
V
I
I
but
15. 15
Case2:Pull down Transistor, It is a E-NMOSFET where
i/p = VDD 1st
operated in resistive region where Vds1 < VDD – Vt.
2
V
V
V
1
Z
k
1
I
V
R
V
2
V
V
V
L
W
K
ds1
t
DD
pd1
ds
ds1
1
2
ds1
ds1
t
DD
p.d1
p.d1
s I
I 1
d
NOTE: Vds1 is small so ignore
2
Vds1
17. 17
Consider inverter2:
Case1:Pull up Transistor, It is a D-NMOSFET where Vgs =0
So it is operated directly in saturation region.
2
V
Z
1
K
2
V
L
W
K
V
V
&
0
2
V
V
L
W
K
td
2
p.u2
2
td
2
p.u2
p.u2
2
td
t
gs
t
gs
2
p.u2
p.u2
1 saturation
ds-
I
I
V
I
I
or
but
18. 18
Case2: Pull down Transistor, It is a E-NMOSFET where
i/p = VDD - Vtp 1st
operated in resistive region where Vds1 < VDD – Vt.
2
V
V
V
1
Z
k
1
I
V
R
V
2
V
V
V
L
W
K
ds2
t
DD
pd2
ds
ds2
2
2
ds2
ds2
t
DD
p.d2
p.d2
s
Id
NOTE: Vds2 is small so ignore
2
Vds2
22. 22
Conclusion-2:
“An inverter driven through one or more pass transistors should
have a Zp.u/Zp.d ratio of ≥8/1.”
VDD
i/p
o/p
DNMOS inverter
VDD
i/p
o/p
DNMOS inverter
VDD
VDD
