1. DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
1
SUBJECT: CMOS VLSI DESIGN
III BTECH II SEM ECE
By
Y.Pradeep
Associate Professor
UNIT I
Lecture-12 : BICMOS inverter
Latch-up in CMOS ckts
2. 2
CMOS technology Bipolar technology
Low static power dissipation High power dissipation
High input impedance
(low drive current)
Low input impedance
(high drive current)
Scalable threshold voltage Low voltage swing logic
High noise margin Low noise margin
High packing density Low packing density
High delay sensitivity to load Low delay sensitivity to load
Low output drive current High output drive current
Low Km (gm a V;n) High Km (gm a evin)
Bidirectional capability
(drain_ and source are
interchangeable)
Essentially unidirectional
• A near ideal switching device • High f, at low currents
3. 3
BiCMOS (Bipolar CMOS) is a semiconductor technology that
combines bipolar and CMOS transistors into a single integrated
circuit. This technology combines the best features of both
technologies.
Benefits of BiCMOS
1.Speed: BiCMOS offers better speed than CMOS.
2.Power dissipation: BiCMOS has lower power dissipation
than bipolar, which makes it easier to design boards and
packages.
3.Design flexibility: BiCMOS has more design flexibility than
CMOS, which can lead to faster design cycles.
4.Analog performance: BiCMOS offers high performance
analog.
5.I/O speed: BiCMOS offers improved I/O speed.
6. 6
BICMOS inverter contd…
• T1,T2 drives the o/p load.
• CL is charged towards
5v-VBE of T2.
• CL is charged towards 0v.
ON
T
ON
T
OFF
T
OFF
T
Vin
2
4
1
3
,
0
OFF
T
OFF
T
ON
T
ON
T
5V,
V
2
4
1
3
in
7. 7
n-substrate
p+ n+ n+ n+
p+
p+
n-well
p-substrate
Vss
VDD
Vout
Vin
Rwell
Vsub
Rsub
Vwell
Transient
Current
flow
Latch-up – Generation of low impedance path between VDD and VSS
due to the interaction of parasitic ‘pnp’ and ‘npn’ BJT’s.
9. 9
Latch-up in CMOS ckts
• Latch-up – Generation of low impedance path
between VDD and VSS due to the interaction of
parasitic ‘pnp’ and ‘npn’ BJT’s.
• This is due to the transient current flow through the
substrate when
(i) Power up.
(ii) External voltages are applied.
10. 10
Latch-up in CMOS ckts contd…
• Due to the transient current flow Vsub will raise which
turns ‘ON’ the ‘npn’ transistor.
• When ‘npn’ is ‘ON’ it pulls the current through the Rwell
and lowers the Vwell value which turns ‘ON’ the ‘pnp’.
VDD
Rsub
Rwell
Vsub
Vwell
11. 11
Latch-up in CMOS ckts contd…
• A +ve feedback is established causing a large current flow
between VSS & VDD.
• This large current flow continues until the power supply turned
off or the power wires melt.
VDD
Rsub
Rwell
Vsub
Vwell
12. 12
Latch-up prevention
• Use p+ guard rings connected to VSS around
NMOS, n+ guard rings connected to VDD around
PMOS to reduce Rwell, Rsub.
• Place substrate and well contacts as close as
possible to the source connections of MOS
transistors to reduce Rwell, Rsub.
• Reduce the gain of the parasitic transistors.
