Computer System Architecture Lecture Note 3: computer architecture
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The document provides an overview of computer system architecture. It begins by defining computer architecture as the set of data types, operations, and features that are visible to a computer's users at a particular level of abstraction. The document then discusses why computer architecture is important for optimizing performance within cost constraints. It describes the basic components of a simple computer system, including the CPU, memory, I/O devices, and bus. The document explains in detail the role of the CPU, including its main components like the control unit, ALU, and registers. It provides examples of how a simple CPU would execute instructions on a 4-bit system. Finally, it illustrates how the bus is used to connect the CPU and other devices to allow
Computer System Architecture Lecture Note 3: computer architecture
- 1. CSC 203 1.5 Computer System Architecture Budditha Hettige Department of Statistics and Computer Science University of Sri Jayewardenepura
- 2. Computer ArchitectureComputer Architecture 2Computer System Architecture2011
- 3. What isWhat is Computer ArchitectureComputer Architecture?? • Set of data types, Operations, and features are call its architecture • It deals with those aspects that are visible to user of that level • Study of how to design those parts a computer is called Computer Architecture 3Computer System Architecture2011
- 4. WhyWhy Computer ArchitectureComputer Architecture • Maximum overall performance of system keeping within cost constraints • Bridge performance gap between slowest and fastest component in a computer • Architecture design – Search the space of possible design – Evaluate the performance of design choose – Identify bottlenecks, redesign and repeat process 4Computer System Architecture2011
- 5. Computer OrganizationComputer Organization • The Simple Computer concise with – CPU – I/O Devices – Memory – BUS (Connection method) 5Computer System Architecture2011
- 6. Simple ComputerSimple Computer 6Computer System Architecture2011
- 7. CPU – Central Processing UnitCPU – Central Processing Unit • Is the “Brain” • It Execute the program and stored in the main memory • Composes with several parts – Control Unit – Arithmetic and Logic Units – Registers 7Computer System Architecture2011
- 8. RegistersRegisters • High-speed memory • Top of the memory hierarchy, and provide the fastest way to access data • Store temporary results • Some useful registers – PC – Program counters • Point to the next instructions – IR - Instruction Register • Hold instruction currently being execute 8Computer System Architecture2011
- 9. Registers more…Registers more… • Types – User-accessible Registers – Data registers – Address registers – General purpose registers – Special purpose registers – Etc. 9Computer System Architecture2011
- 10. InstructionInstruction • Types – Data handling and Memory operations • Set, Move, Read, Write – Arithmetic and Logic • Add, subtract, multiply, or divide • Compare – Control flow • Complex instructions – Take many instructions on other computers • saving many registers on the stack at once • moving large blocks of memory 10Computer System Architecture2011
- 11. Parts of an instructionParts of an instruction • Opcode – Specifies the operation to be performed • Operands – Register values, – Values in the stack, – Other memory values, – I/O ports 11Computer System Architecture2011
- 12. Type of the operationType of the operation • Register-Register Operation – Add, subtract, compare, and logical operations • Memory Reference – All loads from memory • Multi Cycle Instructions – Integer multiply and divide and all floating-point operations 12Computer System Architecture2011
- 13. Fetch-Decode execute circleFetch-Decode execute circle • Instruction fetch – 32-bit instruction was fetched from the cache • Decode • Execute • Memory Access • Write back 13Computer System Architecture2011
- 14. Fetch-Decode execute circleFetch-Decode execute circle 14Computer System Architecture2011
- 15. MIcroprocessorsMIcroprocessors • Processors can be identify by two main parameters – Speed (MHz/ GHz) – Processor with • Data bus • Address bus • Internal registers 15Computer System Architecture2011
- 16. Data busData bus • Known as Front side bus, CPU bus and Processor side bus • Use between CPU and main chipset • Define a size of memory – 32 bit – 64 bit etc. 16Computer System Architecture2011
- 17. Data busData bus 17Computer System Architecture2011
- 18. I/O Ports with data transfer ratesI/O Ports with data transfer rates Controller Port / Device Typical Data Transfer Rate Super I/O PS/2 (keyboard / mouse) 2 KB/s Serial Port 25 KB/s Floppy Disk 125 KB/s Parallel Port 200 KB/s Southbridge Integrated Audio 1 MB/s Integrated LAN 12 MB/s USB 60 MB/s Integrated Video 133 MB/s IDE (HDD, DVD) 133 MB/s SATA (HDD, DVD) 300 MB/s 18Computer System Architecture2011
- 19. Address BusAddress Bus • Carries addressing information • Each wire carries a single bit • Width indicates maximum amount of RAM the processor can handle • Data bus and address bus are independent 19Computer System Architecture2011
- 20. How CPU works?How CPU works? • A Simple CPU – 4 Bit Address bus – Registers A, B and C (4 Bit) – 8 Bit Program ( 4 BIT Instruction, 4 BIT Data) 20Computer System Architecture2011
- 21. How CPU works?How CPU works? 2011 Computer System Architecture 21 A B C IP Instruction SET 0000 Sleep 0001 LOAD M → A 0010 LOAD M → B 0101 SET A → M 0110 SET B → M 1000 ADD A + B → C 1111 MOVE 1001 RESET IC ALUALU Register CRegister C Instruction CounterInstruction Counter
- 22. How CPU works?How CPU works? 2011 Computer System Architecture 22 A B C C 0 0 0 0 Instruction SET 0000 Sleep 0001 LOAD M → A 0010 LOAD M → B 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 0 0 0 0 6 IC 01
- 23. How CPU works?How CPU works? 2011 Computer System Architecture 23 A B C C 0 0 0 1 Instruction SET 0000 Sleep 0001 LOAD M → A 0010 LOAD M → B 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 0 0 0 0 6 0 0 1 0 IC 02
- 24. How CPU works?How CPU works? 2011 Computer System Architecture 24 A 0 0 1 0 B C C 0 0 1 0 Instruction SET 0000 Sleep 0001 LOAD M → A 0010 LOAD M → B 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 0 0 0 0 6 0 1 0 1IC 03
- 25. How CPU works?How CPU works? 2011 Computer System Architecture 25 A 0 0 1 0 B 0 1 0 1 C 0 1 1 1 C 1 0 0 0 Instruction SET 0000 Sleep 0001 LOAD M → A 0010 LOAD M → B 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 0 0 0 0 6 1 0 0 1 0 0 0 0 7 1 1 1 1 0 0 0 1 8 IC 04
- 26. How CPU works?How CPU works? 2011 Computer System Architecture 26 A 0 0 1 0 B 0 1 0 1 C 0 1 1 1 C 0 1 1 1 Instruction SET 0000 Sleep 1111 MOVE 1001 RESET 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 1 1 1 1 6 1 0 0 1 0 0 0 0 7 1 1 1 1 0 0 0 1 8 0 1 1 1 IC 05
- 27. How CPU works?How CPU works? 2011 Computer System Architecture 27 A 0 0 1 0 B 0 1 0 1 C 0 1 1 1 C 1 0 0 1 Instruction SET 0000 Sleep 1111 MOVE 1001 RESET 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 1 1 1 1 6 1 0 0 1 0 0 0 0 7 1 1 1 1 0 0 0 1 8 0 1 1 1 IC 06
- 28. How CPU works?How CPU works? 2011 Computer System Architecture 28 A 0 0 0 0 B 0 0 0 0 C 0 0 0 0 C 0 0 0 0 Instruction SET 0000 Sleep 1111 MOVE 1001 RESET 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 1 1 1 1 6 1 0 0 1 0 0 0 0 7 1 1 1 1 0 0 0 1 8 IC 06
- 29. How CPU works?How CPU works? 2011 Computer System Architecture 29 A 0 0 0 0 B 0 0 0 0 C 0 0 0 0 C 1 1 1 1 Instruction SET 0000 Sleep 1111 MOVE 1001 RESET 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 1 1 1 1 6 1 0 0 1 0 0 0 0 7 1 1 1 1 0 0 0 1 8 IC 07
- 30. How CPU works?How CPU works? 2011 Computer System Architecture 30 A 0 0 0 0 B 0 0 0 0 C 0 0 0 0 C 0 0 0 0 Instruction SET 0000 Sleep 1111 MOVE 1001 RESET 0101 SET A → M 0110 SET B → M 0111 SET C → M 1000 ADD A + B → C 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 0 3 0 0 1 0 0 1 0 1 4 1 0 0 0 0 0 0 0 5 0 1 1 1 1 1 1 1 6 1 0 0 1 0 0 0 0 7 1 1 1 1 0 0 0 1 8 IC 01
- 31. How BUS System works?How BUS System works? 2011 Computer System Architecture 31 DATA BUS CPU Device ADevice A Device BDevice B Device CDevice C ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS
- 32. How BUS System worksHow BUS System works 2011 Computer System Architecture 32 DATA BUS ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS
- 33. How BUS System worksHow BUS System works 2011 Computer System Architecture 33 DATA BUS CPU Device ADevice A Device BDevice B Device CDevice C ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS ADDRESS BUS 4 BIT DATA BUS 4 BIT CONTROL BUS 2 BIT
- 34. How BUS System worksHow BUS System works 2011 Computer System Architecture 34 DATA BUS ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0100 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0010 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0001
- 35. How BUS System worksHow BUS System works 2011 Computer System Architecture 35 DATA BUS ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0100 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0010 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0001 0 0 0 00 0 0 00 0 0 0 0 00 0
- 36. How BUS System worksHow BUS System works 2011 Computer System Architecture 36 DATA BUS ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0100 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0010 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0001 0 1 0 00 1 0 00 0 0 0 0 00 0
- 37. How BUS System worksHow BUS System works 2011 Computer System Architecture 37 DATA BUS ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0100 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0010 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0001 0 1 0 00 1 0 01 01 0 1 01 0
- 38. How BUS System worksHow BUS System works 2011 Computer System Architecture 38 DATA BUS ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0100 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0010 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0001 0 0 1 00 0 1 01 01 0 0 00 0
- 39. How BUS System worksHow BUS System works 2011 Computer System Architecture 39 DATA BUS ADDRESS BUSADDRESS BUS CONTROL BUSCONTROL BUS CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0100 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0010 CONTROL 2 BIT 01 – READ, 10 – Write ADDRESS 0001 0 0 1 00 0 1 01 01 0 0 10 1