Cs1104 11
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The document discusses different types of sequential logic circuits used for memory elements, including latches and flip-flops. It describes pulse-triggered latches like the S-R and D latches, and edge-triggered flip-flops such as the S-R, D, J-K, and T flip-flops. It provides their characteristic tables and discusses how their output states change based on input signals and the clock pulse.
Cs1104 11
- 1. LATCHES AND FLIP FLOPS
- 2. CS1104-11 Lecture 11: Sequential Logic: Latches & Flip-flops 2 Lecture 11: Sequential Logic Latches & Flip-flops Introduction Memory Elements Pulse-Triggered Latch S-R Latch Gated S-R Latch Gated D Latch Edge-Triggered Flip-flops S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop Asynchronous Inputs
- 3. CS1104-11 Introduction 3 Introduction A sequential circuit consists of a feedback path, and employs some memory elements. Combinational logic Memory elements Combinational outputs Memory outputs External inputs Sequential circuit = Combinational logic + Memory Elements
- 4. CS1104-11 Introduction 4 Introduction There are two types of sequential circuits: synchronous: outputs change only at specific time asynchronous: outputs change at any time Multivibrator: a class of sequential circuits. They can be: bistable (2 stable states) monostable or one-shot (1 stable state) astable (no stable state) Bistable logic devices: latches and flip-flops. Latches and flip-flops differ in the method used for changing their state.
- 5. CS1104-11 S-R Latch 5 S-R Latch Complementary outputs: Q and Q'. When Q is HIGH, the latch is in SET state. When Q is LOW, the latch is in RESET state. For active-HIGH input S-R latch (also known as NOR gate latch), R=HIGH (and S=LOW) RESET state S=HIGH (and R=LOW) SET state both inputs LOW no change both inputs HIGH Q and Q' both LOW (invalid)!
- 6. CS1104-11 S-R Latch 6 S-R Latch For active-LOW input S'-R' latch (also known as NAND gate latch), R'=LOW (and S'=HIGH) RESET state S'=LOW (and R'=HIGH) SET state both inputs HIGH no change both inputs LOW Q and Q' both HIGH (invalid)! Drawback of S-R latch: invalid condition exists and must be avoided.
- 7. CS1104-11 S-R Latch 7 S-R Latch Characteristics table for active-high input S-R latch: Characteristics table for active-low input S'-R' latch: S R Q Q' 0 0 NC NC No change. Latch remained in present state. 1 0 1 0 Latch SET. 0 1 0 1 Latch RESET. 1 1 0 0 Invalid condition. S' R' Q Q' 1 1 NC NC No change. Latch remained in present state. 0 1 1 0 Latch SET. 1 0 0 1 Latch RESET. 0 0 1 1 Invalid condition. S R Q Q' S R Q Q'
- 8. CS1104-11 Gated S-R Latch 8 Gated S-R Latch S-R latch + enable input (EN) and 2 NAND gates → gated S-R latch. S R Q Q' EN S EN R Q Q'
- 9. CS1104-11 Gated S-R Latch 9 Gated S-R Latch Outputs change (if necessary) only when EN is HIGH. Under what condition does the invalid state occur? Characteristic table: Q(t) S R Q(t+1) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 indeterminate 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 indeterminate EN=1 S R Q(t+1) 0 0 Q(t) No change 0 1 0 Reset 1 0 1 Set 1 1 indeterminate Q(t+1) = S + R'.Q S.R = 0
- 10. CS1104-11 Gated D Latch 10 Gated D Latch Make R input equal to S' → gated D latch. D latch eliminates the undesirable condition of invalid state in the S-R latch. D EN Q Q' D Q Q' EN
- 11. CS1104-11 Gated D Latch 11 Gated D Latch When EN is HIGH, D=HIGH → latch is SET D=LOW → latch is RESET Hence when EN is HIGH, Q ‘follows’ the D (data) input. Characteristic table: When EN=1, Q(t+1) = D EN D Q(t+1) 1 0 0 Reset 1 1 1 Set 0 X Q(t) No change
- 12. CS1104-11 Edge-Triggered Flip-flops 12 Edge-Triggered Flip-flops Flip-flops: synchronous bistable devices Output changes state at a specified point on a triggering input called the clock. Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal. Positive edges Negative edges Clock signal
- 13. CS1104-11 Edge-Triggered Flip-flops 13 Edge-Triggered Flip-flops S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the clock input. S C R Q Q' S C R Q Q' D C Q Q' D C Q Q' J C K Q Q' J C K Q Q' Positive edge-triggered flip-flops Negative edge-triggered flip-flops
- 14. CS1104-11 SR Flip-flop 14 S-R Flip-flop S-R flip-flop: on the triggering edge of the clock pulse, S=HIGH (and R=LOW) SET state R=HIGH (and S=LOW) RESET state both inputs LOW no change both inputs HIGH invalid Characteristic table of positive edge-triggered S-R flip- flop: X = irrelevant (“don’t care”) ↑ = clock transition LOW to HIGH S R CLK Q(t+1) Comments 0 0 X Q(t) No change 0 1 ↑ 0 Reset 1 0 ↑ 1 Set 1 1 ↑ ? Invalid
- 15. CS1104-11 SR Flip-flop 15 S-R Flip-flop It comprises 3 parts: a basic NAND latch a pulse-steering circuit a pulse transition detector (or edge detector) circuit The pulse transition detector detects a rising (or falling) edge and produces a very short-duration spike.
- 16. CS1104-11 D Flip-flop 16 D Flip-flop D flip-flop: single input D (data) D=HIGH SET state D=LOW RESET state Q follows D at the clock edge. Convert S-R flip-flop into a D flip-flop: add an inverter. A positive edge-triggered D flip- flop formed with an S-R flip-flop. S C R Q Q' CLK D D CLK Q(t+1) Comments 1 ↑ 1 Set 0 ↑ 0 Reset ↑ = clock transition LOW to HIGH
- 17. CS1104-11 J-K Flip-Ffop 17 J-K Flip-flop J-K flip-flop: Q and Q' are fed back to the pulse- steering NAND gates. No invalid state. Include a toggle state. J=HIGH (and K=LOW) SET state K=HIGH (and J=LOW) RESET state both inputs LOW no change both inputs HIGH toggle
- 18. CS1104-11 J-K Flip-flop 18 J-K Flip-flop J-K flip-flop. Characteristic table. J Q Q' CLK Pulse transition detector K J K CLK Q(t+1) Comments 0 0 ↑ Q(t) No change 0 1 ↑ 0 Reset 1 0 ↑ 1 Set 1 1 ↑ Q(t)' Toggle Q J K Q(t+1) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 Q(t+1) = J.Q' + K'.Q
- 19. CS1104-11 T Flip-flop 19 T Flip-flop T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together. Characteristic table. T CLK Q(t+1) Comments 0 ↑ Q(t) No change 1 ↑ Q(t)' Toggle Q T Q(t+1) 0 0 0 0 1 1 1 0 1 1 1 0 Q(t+1) = T.Q' + T'.Q T Q Q' CLK Pulse transition detector J C K Q Q' CLK T
- 20. End of segment