![Chapter 1
Introduction
Research and engineering work throughout the first half of the twentieth century led
to the invention of the first metal-oxide-semiconductor field-effect transistor (MOS-
FET) [95], which is the dominating building block for digital systems to date. The
invention of MOSFETs enabled the digital revolution and heralded the beginning
of the information age. The composition of MOSFETs facilitated the realization
of the first integrated circuits and, shortly after, of microprocessors. Gordon E.
Moore, a co-founder of Intel Corporation, was the first person to actively study
the rapid progression in the fabrication of these processors. As early as 1965, he
predicted a temporal development, which was later named Moore’s law in his honor.
He postulated that the transistor density, and, thus, the computational power, of
microchips would double every 18–24 months [129].
For decades, this law remained valid, partially becoming a self-fulfilling
prophecy in the industry. However, any exponential growth must eventually arrive
at an impassable barrier due to its inability to exceed the limitations imposed by
physics. In recent years, a flattening of the growth of transistor density could be
observed. One of the main limiting factors in present complementary metal-oxide-
semiconductor (CMOS) [198] scaling is, in fact, energy dissipation. Even though
Robert H. Dennard and his coauthors postulated in 1974 that the energy density
of MOSFETs would stay constant with miniaturization [45], this principle, often
referred to as Dennard scaling, is outweighed by leakage and parasitic effects
occurring at current process nodes [54]. Consequently, the thermal density of
modern processors strictly limits frequency scaling and prevents the simultaneous
utilization of certain chip regions to avoid overheating. The areas forced to be
inactive are commonly called Dark Silicon [54, 175]. Estimates suggest that for
any technology node below 8 nm, which corresponds to current fabrications, at least
50% of a chip’s area has to be dark [54].
Nonetheless, to enable technologies such as artificial intelligence, autonomous
driving, and immersive virtual reality, more powerful computational systems will
be continuously needed. However, due to the discussed effects and the increasing
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022
M. Walter et al., Design Automation for Field-coupled Nanotechnologies,
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![2 1 Introduction
ubiquity of digital systems, worldwide energy consumption allotted to information
and telecommunication is growing rapidly. Some scenarios predict that the sector
could reach as much as 51% of global electricity usage by 2030 and, thereby,
contribute up to 23% of the globally released greenhouse gases [7].
Therefore, current research aims to establish new materials and building blocks
that enable extremely low-power computational paradigms, hence, facilitating
further miniaturization and large-scale integration by a reduction of on-chip thermal
density while reducing overall worldwide power consumption in an attempt to
engage climate change.
Field-coupled nanocomputing (FCN) [6] is a class of post-CMOS emerging
nanotechnologies that conduct computations without the flow of electric current but
via the repulsion of physical fields. FCN does not utilize transistors but elementary
devices called cells, which are building blocks with enhancements in terms of
energy dissipation and feature size. Certain implementations indicate the possibility
to realize nanometer cells [90, 147] with energy dissipation below the Landauer
limit [97, 104, 110, 120, 178] or clock frequencies in the terahertz range [176].
Inspired by the mathematical model of cellular automata [177], in 1993,
Craig S. Lent and his coauthors proposed the concept of Quantum-dot Cellular
Automata (QCA) [113, 115, 116]. QCA is an FCN technology, for which several
physical implementations have been discussed in the literature, e.g., semiconduc-
tors [143, 166–168, 178], nanomagnets [13, 37, 138], molecules [21, 30, 108, 109],
and silicon dangling bonds [75, 83, 201]. Essential to all implementations is the
concept of positional information encoding and in-memory computation due to
the bistable confinement of charges. A charged cell influences adjacent ones and
enforces them to polarize accordingly [197]. Due to the bistable charge distribution,
binary values can be encoded and transmitted via repulsion [114, 116]. Topological
arrangements of cells into patterned arrays yield wire segments, majority gates, and
inverters, i.e., universal building blocks of combinational circuitry [112, 180]. These
characteristics make FCN technologies promising candidates for the augmentation
or substitution of MOSFETs. Furthermore, multiple institutes, e.g., the Department
of Nanoscale Information and Communications Technology at the University of
Alberta or the Research Group of Microsystems and Nanotechnology at the Uni-
versity of British Columbia, as well as the research enterprise Quantum Silicon Inc.,
are actively investigating physical implementations of FCN technologies.
However, in the FCN domain, a multitude of novel design challenges arise
that differ in their nature from the ones enforced in most CMOS technologies:
clocking is a necessity for both combinational and sequential FCN circuits alike
because it stabilizes signals and directs information flow [80, 113]. Nonetheless, the
clocking paradigm itself leads to the emergence of data synchronization issues that
require careful attention in order not to accidentally induce unintended, or worse,
undefined, behavior. Furthermore, wire segments and gates are created from the
same building blocks and, thus, share the same area requirements and signal delay
properties. Additionally, FCN technologies are considered to be planar with limited
wire crossing capabilities, which quickly convolutes placement and routing.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-18-320.jpg)
![1 Introduction 3
These challenges directly influence the obtainment of FCN circuit layouts
from specifications. While large FCN systems like arithmetic circuits [144],
processors [55], and FPGAs [98] have previously been envisioned, these have
been generated manually. However, practically relevant circuits exceed human-
graspable complexity, which excludes this practice from the large-scale design
of FCN layouts. Although there are some algorithmic solutions available, these
approaches produce results of limited quality and do not scale [27, 34, 57, 181].
Due to their peculiarity in terms of design constraints, conventional physical
design algorithms cannot be applied to the FCN domain. In other words, design
automation for an entire class of highly promising nanotechnologies that could
potentially enable a future of powerful and green computational devices is still in its
infancy.
This book considers the main tasks in the area of design automation for FCN
technologies that must be proficiently understood to enable large-scale composition
of elementary building blocks to obtain correct systems from given function
specifications. To this end, a holistic design flow is presented that covers
• exact and scalable placement and routing,
• one-pass logic synthesis,
• novel clocking mechanisms for data synchronization, and
• formal verification for obtained circuit layouts.
Additionally, theoretical groundwork is presented that lays the foundation for any
algorithmic consideration in the future. Furthermore, an open-source and publicly
available FCN design framework called fiction, which contains implementations of
all discussed techniques, is presented, thus, supporting open research by making all
claims throughout this book reproducible.
More precisely, this work makes contributions to the following topics.
Theoretical Groundwork (Chap. 3)
Decades of theoretical investigation led to the consolidation of knowledge in the
area of physical design for CMOS circuitry [94, 106]. The first step toward a similar
comprehensive theoretical understanding in the FCN domain is provided [189].
Therefore, the placement and routing problem is formally defined in two variants:
once as a decision problem and once as an optimization problem. Both of them are
proven to be intractable under the assumption P = NP. Along with the initial
definitions, several adjustments are made to factor in real-world design decisions. It
is also proven that for these configurations, the complexities remain unchanged. To
the best of the authors’ knowledge, no such exploration has been conducted before
while taking the peculiar FCN constraints into account.
Exact Placement and Routing (Chap. 4)
The inferred intractability of said problems is taken as a justification for the
application of formal methods. An exact algorithm for placement and routing of
FCN circuit layouts based on SMT solving is presented [188]. Henceforth, for
the first time, the obtainment of minimal layouts, in terms of area, from given
logic network specifications becomes feasible. For the realization of the presented](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-19-320.jpg)
![4 1 Introduction
method, the findings from Chap. 3 are utilized to construct iterative, incremental,
and parallel SMT formulations that encode the placement and routing problem.
Various parameters allow for the usage of predefined clocking schemes as well as
the toggling of global synchronization, wire crossings, and border I/O pins, and the
application of secondary optimization criteria. Thereby, sophisticated design space
exploration becomes possible.
Scalable Placement and Routing (Chap. 5)
While the exact algorithm for placement and routing generates solutions of optimum
quality in terms of the circuit layout area, its scalability is inherently limited by
the problem’s intractability. Limiting factors of the problem domain and existing
algorithms are identified to present an approximation via utilization of graph-
theoretical findings [15, 16, 53]. By restricting certain degrees of freedom like the
underlying clocking scheme and logic network structure, a scalable algorithm for
placement and routing emerges that offers polynomial complexity in both time and
space without the loss of Boolean expressive power [190, 192]. It, thereby, enables
the automatic design of circuit layouts for logic networks with tens of thousands
of nodes within seconds. Thus, compared to former state-of-the-art algorithms, a
scalability improvement of several orders of magnitude is achieved.
One-Pass Synthesis (Chap. 6)
Since logic networks are usually obtained by conventional logic synthesis
approaches, they are optimized with respect to abstract or conventional cost metrics
such as the number of gates, area, depth, etc. that, however, do not apply to FCN
circuit layouts in the same way. Final FCN costs highly depend on the utilized
clocking scheme and the network structure. Consequently, using logic networks as
an intermediate step frequently leads to a substantial quality loss. These obstacles
are addressed by proposing a one-pass synthesis scheme for FCN circuit layouts
that conducts logic synthesis and physical design holistically in a single run and
which does not rely on logic networks as an intermediate step [194]. The deductive
power of satisfiability solvers is used once more. At the same time, the presented
approach also offers a high degree of flexibility and can be parameterized with
various design features, such as wire crossings, gate libraries, and clocking schemes
to restrict or loosen certain constraints and, thereby, leverage the required runtime
overhead.
Exploiting Clocks for Synchronization (Chap. 7)
Signal synchronization in FCN is one of the most fundamental differences compared
to CMOS technologies. To this end, a detailed investigation reveals that certain
synchronization restrictions are, in fact, not mandatory but mere optional constraints
of valid combinational and sequential FCN circuit layouts [162, 164]. A methodol-
ogy, for driving and stalling primary inputs, is discussed, which enables the correct
operation of layouts formerly assumed to be defective. Furthermore, the exploitation
of external clock generators as a technology extension to the FCN concept is
presented. Via the introduction of asymmetric memory clocks, layout tiles can be
transformed into synchronization elements that stall signals over multiple clock](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-20-320.jpg)
![1 Introduction 5
cycles as verified with a physics simulator, thus, facilitating novel methodologies for
FCN circuit layout design [161, 200]. A case study demonstrates the utilization of
synchronization elements as the missing link between conventional physical design
algorithms and the FCN domain. Henceforth, synchronization elements might have
a substantial and significant impact on future research in the field as they finally
enable the application of decades of research results on automatic design techniques
to FCN technologies.
Formal Verification (Chap. 8)
Since conventional methods used for the verification of CMOS circuitry do not
apply to the FCN domain due to signal synchronization differences, a novel
technique is introduced [193]. It enhances said conventional methods to adapt
them to FCN circuit layouts. As a representative verification problem, equivalence
checking is examined. Via a combination of a conventional SAT encoding using
miter structures and a novel ILP encoding for signal synchronization, a methodology
emerges that can verify the correctness of FCN circuit layouts with millions of tiles
within minutes. Furthermore, it yields synchronization values for primary inputs to
balance desynchronized layouts and computes overall delay.
fiction: A Holistic Open-Source Framework (Chap. 9)
Finally, an extensible open-source framework for design automation of FCN circuit
layouts is presented that is publicly available on GitHub [66, 191]. The fiction
framework was developed alongside the research for this book. The presented
algorithms are implemented within the said framework to support open research
and to make all claims reproducible. To facilitate future research in this field, fiction
provides core data types needed by a multitude of design automation algorithms,
e.g., logic networks, FCN layouts on different abstraction levels, clocking schemes,
and gate libraries. Furthermore, file input and output functionalities are given that
allow convenient exchange with logic synthesis and physical simulation tools. For
experimental evaluations, fiction provides rich scripting and logging functionalities.
Thereby, it is providing a comprehensive sandbox for designers, researchers, and
developers in the FCN domain.
In summation, the contributions made in this book create a comprehensive design
flow for FCN technologies. In contrast to prior work in the domain, this enables the
automatic synthesis, placement, routing, clocking, formal verification, and physical
simulation of circuit layouts from logical specifications [187]. Furthermore, theo-
retical groundwork assists future research in the field by identification of obstacles
and opportunities. Finally, the holistic design framework fiction serves as an open-
source sandbox for designers, researchers, and algorithm developers by providing
implementations of all presented approaches.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-21-320.jpg)
![Chapter 2
Preliminaries
In an effort to establish this book as a stand-alone work, this chapter introduces
important fundamentals and notations necessary for the comprehension of this
endeavor. First, Sect. 2.1 goes over various forms of logic representations and data
structures. These form the basis for considerations throughout all the remaining
chapters. Next, Sect. 2.2 discusses satisfiability problems of prepositional and first-
order logic together with optimized solvers for practical applications. Algorithms
presented in three chapters throughout this work make heavy use of respective
solving engines and require this previous knowledge. Finally, Sect. 2.3 introduces
the technology class concept that is field-coupled nanocomputing from both a
physical and a more formal point of view. Field-coupled nanocomputing is the host
technology for all algorithms presented in this work and thereby its focal point.
2.1 Logic Representations
The Boolean calculus formulated by George Boole in 1847 (and later named in his
honor) provides the basis for all digital computer systems to this date, by allowing
to describe, manipulate, and reason about logical functions [22]. In the following,
Boolean functions are introduced in Sect. 2.1.1. Subsequently, two representations
for Boolean functions are discussed, namely truth tables in Sect. 2.1.2 and logic
networks in Sect. 2.1.3.
2.1.1 Boolean Functions
The aforementioned Boolean calculus defines algebraic structures.
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022
M. Walter et al., Design Automation for Field-coupled Nanotechnologies,
https://doi.org/10.1007/978-3-030-89952-3_2
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![8 2 Preliminaries
Definition 2.1 Given a finite set S, two binary functions · : S × S → S and + :
S × S → S, and one unary function ¬ : S → S, the tuple (S, ·, +, ¬) is called a
Boolean algebra iff the following constraints hold for all a, b, c ∈ S:
a · b = b · a a + b = b + a
a · (b + c) = (a · b) + (a · c) a + (b · c) = (a + b) · (a + c)
∃1 ∈ S : a · 1 = a ∃0 ∈ S : a + 0 = a
∃0 ∈ S : a · ¬a = 0 ∃1 ∈ S : a + ¬a = 1.
These constraints are referred to as commutativity, distributivity, neutrality, and
complementarity.
The definition as given here is based on an addition to Boolean calculus by
Edward V. Huntington [85, 86]. Further properties of Boolean algebras can be
immediately derived from this definition, including but not limited to associativity,
idempotence, extremality, involution, duality, absorption, and De Morgan’s laws
[85, 86].
As done in Definition 2.1, the infix notation can be used for the functions of
Boolean algebras for convenient readability. Further common notations include the
usage of ∧ and ∨ instead of · and + as well as a instead of ¬a.
In general, the term Boolean algebra often refers to the special two-element
Boolean algebra.
Definition 2.2 The tuple (B, ·, +, ¬), where B := {0, 1}, and
a · b := 1 ⇐⇒ a = b = 1,
a + b := 0 ⇐⇒ a = b = 0,
¬a := 1 ⇐⇒ a = 0,
is a Boolean algebra and is called two-element Boolean algebra. Its functions are
usually referred to as conjunction (AND), disjunction (OR), and negation (NOT).
Elements of the Boolean set B are called Boolean variables or binary digits (bits).
In propositional logic, the zero element 0 ∈ B is interpreted as false, while the
one element 1 ∈ B is interpreted as true.
A benefit of using algebraic notation is the intuitive inference of operation order
when omitting brackets.
Functions defined on sets of Boolean variables are called Boolean functions.
Definition 2.3 A function f : Bn → B, where n ∈ N, is called a Boolean function.
Conjunction, disjunction, and negation are Boolean functions. Analogously, a
function f : Bn → Bm, where n, m ∈ N, is called multi-output Boolean function
and can be interpreted as f = (f1, . . . , fm), where fi : Bn → B, for all 1 ≤ i ≤ m.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-23-320.jpg)
![10 2 Preliminaries
Fig. 2.1 Truth tables of common Boolean functions
As a direct consequence of the rather lengthiness of truth table descriptions as
binary strings, they can be translated into decimal or, more commonly, hexadecimal
notation.
Example 2.3 Given binary, decimal, and hexadecimal notations, the conjunction in
Fig. 2.1a can be represented as 10002 = 810 = 816, the disjunction in Fig. 2.1b
can be represented as 11102 = 1410 = e16, and the negation in Fig. 2.1c can be
represented as 012 = 110 = 116.
Hexadecimal notation is generally prefixed with a 0x and not suffixed with
an indexed 16 in the computer science domain to ensure ASCII compatibility.
Consequently, the resulting representations from the previous example are 0x8,
0xe, and 0x1.
2.1.3 Logic Networks
The truth table representation of Boolean functions grows exponentially in size with
respect to their dimension n. It is, therefore, only suited to denote rather small
functions. To overcome this restriction, various other forms of Boolean function
representations have been proposed over the decades.
One that has proven especially useful is the notion of logic networks [42].
Informally, a logic network is a graph-like structure with function labels assigned to
its nodes. Thereby, it resembles a combinational circuit but abstracts from physical
behavior and only considers the logic level.
A common formal definition was introduced by Donald E. Knuth as he described
Boolean chains [100].
Definition 2.6 A Boolean chain of a multi-output Boolean function f : Bn → Bm
over the variables x1, . . . , xn is a sequence of r steps (xn+1, . . . , xn+r). Each step
combines two arbitrary preceding ones, where x1, . . . , xn are considered designated
primary inputs. Each combination of two steps is defined as xi = xj(i)◦i xk(i), where
n + 1 ≤ i ≤ n + r, and 1 ≤ j(i), k(i) i. The operator ◦i is an arbitrary binary
Boolean function. Finally, for 1 ≤ j ≤ m, it must hold that fj (x1, . . . , xn) = xl(j),
where 0 ≤ l(j) ≤ n + r.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-25-320.jpg)
![2.1 Logic Representations 11
Fig. 2.2 A 5-step Boolean
chain f (x1, x2, x3)
Example 2.4 Let n = 3, then the 5-step Boolean chain
x4 = x1 ∧ x2
x5 = x1 ∧ x3
x6 = x2 ∧ x3
x7 = x4 ∨ x5
x8 = x6 ∨ x7
f = x8
is depicted in Fig. 2.2.
While this definition is elegant, it is also overly restrictive as it allows steps
to represent binary functions exclusively. Therefore, in the following, a custom
definition is given, which is inspired by [74].
Definition 2.7 A logic network is a Boolean chain, where each of the r steps xi has
an arity δi assigned, such that xi = φi(xj(i,1), . . . , xj(i,δi)) for n + 1 ≤ i ≤ n + r,
and 1 ≤ j(i, d) i, with 1 ≤ d ≤ δi. Here, φi refers to an arbitrary δi-ary Boolean
function, thus, relaxing the strict binary computation constraint in each step.
In this work, steps are referred to as (logic) nodes with their set being denoted
as and the set of primary inputs being denoted as I, with ∩ I = ∅. A
connection xj(i,d) between some node xi and one of its predecessors xj , where
xi = φi(xj(i,1), . . . , xj(i,δi)), is called a signal. The set of all signals is denoted as
. The designated signals computing the functions fj are referred to as primary
outputs, whose set is denoted as O, with ∩ O = ∅. Thereby, as aforementioned,
a logic network can be interpreted as a directed acyclic graph N = (, I, , O).
Furthermore, the notation x ∈ N is used to refer to some node x ∈ of N, and
the notation |N| is used to refer to the number of all logic nodes r. Since this book
considers symmetric functions for logic nodes exclusively for all purposes, without
loss of generality, the notation (xj , xi) is used to refer to a signal xj(i,d), i.e., a
connection from node xj to node xi toward the primary outputs.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-26-320.jpg)
![12 2 Preliminaries
Various types of logic networks have been proposed in the literature. For
instance, AND-Inverter Graphs (AIGs) [102] restrict the permitted node functions
to conjunction and negation, while Majority-Inverter Graphs (MIGs) [4] are
restricted to the majority function and negation. Furthermore, compound structures
exist, e.g., XOR-AND(-Inverter) Graphs (XAGs) [77], which rely on exclu-
sive disjunction, conjunction, and negation, as well as XOR-Majority(-Inverter)
Graphs (XMGs) [72], which are constructed from exclusive disjunction, majority,
and negation.1
Definition 2.8 Majority of three, or simply majority (MAJ), is a ternary Boolean
function denoted as a, b, c := ab + ac + bc, i.e., as the name suggests, the
function evaluates to the majority value of its three variables. Its truth table is 0xe8.
Consequentially, a, b, 0 = ab and a, b, 1 = a + b.
The Boolean chain defined in Example 2.4 and depicted in Fig. 2.2 represents
the majority function.
Definition 2.9 The exclusive disjunction (XOR) is a binary Boolean function
denoted as a ⊕ b := (a + b) · (¬a + ¬b). Its truth table is 0x6.
AIGs, MIGs, XAGs, and XMGs all possess a property called universality, that
is, these data structures are capable of representing every Boolean function by
composing their elementary operators. The task of determining a logic network
that implements some given specification is called logic synthesis (cf. [42] for an
overview).
As mentioned initially, in practice, logic networks are used as representa-
tives for combinational circuits that are to be fabricated for some technology,
e.g., using metal-oxide-semiconductor field-effect transistor (MOSFET) elements,
which are the dominating building blocks for integrated circuits today [95].
A corresponding large-scale fabrication process is complementary metal-oxide-
semiconductor (CMOS) technology [198].
Since logic networks are non-canonical, various implementations for a given
specification exist. Considering that nodes can perform the identity function, it
becomes apparent that an infinite number of different logic networks exist that all
compute the same Boolean function. In case a specialized network is considered that
does not permit identity nodes, the same argumentation holds for pairs of successive
inverters or similar structures that collapse to the identity.
Based on this deliberation and the widely accepted assumption that the task of
obtaining optimum logic networks is NP-complete [93], logic synthesis algorithms
usually yield approximate solutions with respect to some aforementioned cost
1 Usually, these data structures are restricted to their respective binary functions without explicit
negation nodes but with the option to negate signals via a polarization flag. Thereby, simplifying
implementation and saving memory as each node can be of fixed fan-in and the polarization flag
can be encoded in the memory address. A designated constant x0 = 0 ensures universality.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-27-320.jpg)
![2.2 Satisfiability Solvers 13
metrics. These are, for instance, their number of nodes, their number of inverters, or
their depth.
Logic synthesis and in particular logic networks play a major role in this book.
Logic networks are used as the main representational form of Boolean functions
throughout this work.
2.2 Satisfiability Solvers
Many practically relevant problems in numerous domains are NP-hard. Intuitively
speaking, this means that no efficient algorithm exists that could solve all instances
of such problems on a conventional computer system unless P = NP. Examples
for NP-hard problems include model checking, planning, and formal verification
[44]. Nevertheless, exact solutions to certain instances of these problems are of
major interest, because the alternative is to rely on approximations of mediocre
quality in the best case. In the worst case, no approximations to the problem in
question are known.
In the recent decades, the usage of satisfiability solvers emerged to tackle
formerly intractable problems. These are highly optimized implementations of
theorem-proving algorithms addressing, for instance, the satisfiability problem in
propositional logic, first-order logic, and many other variations (cf. [19] for an
overview).
Figure 2.3 visualizes the concept of utilizing such engines for the obtainment of
problem solutions. The process contains the following three steps: (1) a problem
instance is encoded as an instance of a satisfiability problem in such a way that they
are equisatisfiable, i.e., there exists a solution to the original problem instance iff
there exists a solution to the satisfiability problem instance, (2) the newly created
instance is passed to a specialized solver that returns an assignment to each variable
in the encoding if such a solution exists or UNSAT, otherwise, (3) a solution to the
original problem is extracted from the assignment.
However, the most sophisticated algorithms cannot break complexity barriers
on conventional computers unless P = NP. Nevertheless, the optimization
techniques built into satisfiability solvers enable a drastically improved average case
performance. Thereby, modern solvers are able to handle instances with hundreds of
thousands of variables and millions of constraints without enumerating entire search
spaces [137].
Section 2.2.1 goes over Boolean satisfiability, i.e., the satisfiability problem
of propositional logic, while Sect. 2.2.2 discusses satisfiability modulo theories,
i.e., satisfiability of first-order logic. Respective solving engines are used in three
chapters of this work and require the previous knowledge.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-28-320.jpg)
![14 2 Preliminaries
Fig. 2.3 Application of satisfiability solvers
2.2.1 Boolean Satisfiability (SAT)
The preceding section introduced propositional logic in the form of Boolean
algebra. Some data structures for the representation of Boolean functions have
been discussed alongside. The Boolean satisfiability problem (SAT) reasons about
Boolean functions being non-antilogies.
Definition 2.10 Given a Boolean function : Bn → B, called instance, in some
logic representation. SAT returns true iff an assignment to exists such that the
function evaluates to 1, i.e., ∃α = (x1, . . . , xn) ∈ Bn : (α) = 1.
Depending on the given representation of , the computational complexity of
determining SAT varies. Stephen A. Cook showed that SAT is NP-complete in the
general case in 1971 [35]. SAT remains NP-complete when passing as CNF but
is in P when passing as DNF.
Example 2.5 Let D = (¬a · b · ¬c) + (¬a · b · c) + (a · ¬b · c) + (a · b · c) in DNF.
A satisfying assignment to D can be determined by satisfying any of its clauses,
e.g., the first one by setting a → 0, b → 1, and c → 0. In fact, there is exactly one
satisfying assignment per clause.
Let C = (¬a + ¬b + c) · (a + b + c) · (a + b + ¬c) · (¬a + b + c) in CNF.
It becomes apparent that applying the same approach to C leads to a conflict.
Assigning a → 0, b → 0, and c → 1 satisfies the first clause but unsatisfies the
third one. Since each clause of a CNF must be satisfied in order to satisfy the overall
formula, the assignment is not valid. In the worst case, all possible 2n assignments
must be investigated to find a fulfilling solution.
As mentioned above, algorithmic procedures and tools tackling the SAT problem
are in development since the 1960s [40, 41]. However, SAT solving is still an](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-29-320.jpg)
![2.2 Satisfiability Solvers 15
active research field with numerous efficient tools developed as late as in the
2000s, e.g., [8, 17, 52, 199]. The reason for their practical effectiveness despite
the NP-completeness of SAT is a combination of various incorporated techniques.
Among these are heuristic decision procedures [69] to analyze in which order to
assign values to variables, more efficient Boolean constraint propagation [130]
that implies the consequences of unit clauses to detect conflicts early, conflict
clauses [125] that are gradually learned by the solver while processing the instance
and assist in restricting the search space, and non-chronological backtracking [125]
that allows efficiently reverting unsatisfying assignments and, thereby, cut large
parts off the search space.
2.2.2 Satisfiability Modulo Theories (SMT)
While the preceding section introduced the satisfiability problem of propositional
logic, this section covers the respective problem of first-order logic. In the following,
first-order logic is briefly introduced first before discussing its satisfiability problem
and respective solvers.
The language of first-order logic is defined syntactically using symbols, terms,
and expressions. This section covers the most relevant parts necessary for this work.
The definitions in this section are based on [50].
Definition 2.11 The following elements are valid symbols in first-order logic:
∀, ∃, ∧, ∨, ¬, ≡, ⇒, ⇐⇒, :, (, ). Additionally, sets of variable symbols V, con-
stant symbols C, function symbols F, and relation symbols R can be defined as
well.
Definition 2.12 Each variable symbol and constant symbol is a term. If f is an
n-ary function symbol and if t1, . . . , tn are terms, then f (t1, . . . , tn) is a term.
Definition 2.13 If t1 and t2 are terms, then t1 ≡ t2 is an expression. If R is an n-ary
relation symbol and if t is a term, then Rt is an expression. If ϕ is an expression,
then ¬ϕ is an expression as well. If ϕ and ψ are expressions, then also (ϕ ∧ ψ),
(ϕ ∨ ψ), (ϕ ⇒ ψ), and (ϕ ⇐⇒ ψ) are expressions. If ϕ is an expression and
if x is a variable symbol, then ∀x : ϕ and ∃x : ϕ are expressions.
Example 2.6 Let x ∈ V be a variable symbol and ≤ ∈ R a binary relation symbol.
∀x : ≤ (x, x) is a valid expression.
If, furthermore, x, y ∈ V are variable symbols, then
∀x : ∀y : ∀z : ((≤ (x, y) ∧ ≤ (y, z)) ⇒ ≤ (y, z))
is a valid expression.
Thus far, this syntax is not associated with any semantics. In the following, a
structure is defined to interpret first-order logic via a signature.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-30-320.jpg)
![2.2 Satisfiability Solvers 17
I | t1 ≡ t2 ⇐⇒ I(t1) = I(t2)
I | f t1, . . . , tn ⇐⇒ f A
(I(t1), . . . , I(tn))
I | Rt1, . . . , tn ⇐⇒ RA
(I(t1), . . . , I(tn))
I | ¬ϕ ⇐⇒ not I | ϕ
I | (ϕ ∧ ψ) ⇐⇒ I | ϕ and I | ψ
I | (ϕ ∨ ψ) ⇐⇒ I | ϕ or I | ψ
I | (ϕ ⇒ ψ) ⇐⇒ if I | ϕ, then also I | ψ
I | (ϕ ⇐⇒ ψ) ⇐⇒ I | ϕ if and only if I | ψ
I | ∀x : ϕ ⇐⇒ I
a
x
| ϕ for all a ∈ A
I | ∃x : ϕ ⇐⇒ there exists some a ∈ A with I
a
x
| ϕ.
For some set of expressions , the notation I | means that ∀ϕ ∈ : I | ϕ
holds.
The satisfiability problem of first-order logic, also called satisfiability modulo
theories (SMT), asks whether a given set of expressions is satisfiable under given
theories [10].
Definition 2.18 Let be a set of expressions formulated in the language of first-
order logic. The set is called an instance. SMT returns true iff ∃I : I | .
Given theories restrict the structure A ∈ I. For instance, the theory of quantifier-
free linear integer arithmetic (QF_LIA) allows integer variable values and linear
arithmetic functions +, −, . . . as well as the relation ≤. The theory of equality and
uninterpreted functions (EUF) allows arbitrary linear and nonlinear functions and
the theory of quantifier-free bit vectors (QF_BV) allows variable interpretation in the
form of vectors of Boolean values together with respective functions for addition,
subtraction, etc.
Since the full expressive power of first-order logic is not necessarily respected,
the complexity of the associated satisfiability problem varies based on the theories
used. For instance, EUF is decidable in polynomial time, while QF_LIA and QF_BV
are both NP-complete. Any theory allowing quantifiers is undecidable in the
general case [10].
For the ease of readability, common notation conventions for elements of the
language of first-order logic are applied in this work. These include the usage of
infix notation, the usage of the equal sign instead of the equivalence operator, and
the separation of quantified variables with commas.
Example 2.8 Let = {ϕ1, ϕ2, ϕ3, ϕ4}, where](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-32-320.jpg)
![2.3 Field-coupled Nanocomputing (FCN) 19
to exclude this assignment in the future. The subsequent proposed assignment could
be ϕ
1 → 1, ϕ
2 → 1, ϕ
3 → 1, ϕ
4 → 1, which is investigated for consistency
by the theory solver once more. As a consequence, the expression is found to be
satisfiable conflict-free for the interpretation I = (A, β), with β(x) = (−5) and
β(y) = (−10). Thus, I | holds.
This procedure is commonly referred to as lazy SMT solving [10, 158] and is
utilized in most solvers to date. In contrast, eager SMT solving breaks theories down
to SAT as much as possible, which is also called bit-blasting [10].
2.3 Field-coupled Nanocomputing (FCN)
Field-coupled nanocomputing (FCN) is a class of post-CMOS emerging nanotech-
nologies that establish a novel paradigm for realizing integrated circuits with
enhancements in terms of energy dissipation and feature size [6]. FCN acts as an
umbrella term for various implementations that all share similar properties.
Since its conceptualization in 1993, the concept of Quantum-dot Cellular
Automata (QCA) [113, 115, 116] is arguably the most extensively researched
FCN approach. QCA utilize nanoscale devices called cells, which are arranged
in specific topological structures to realize circuitry. QCA systems transmit and
compute information without the flow of electric current. Instead, they utilize the
repulsion of local fields. Several physical implementations have been proposed to
realize QCA, e.g., semiconductors [143, 166–168, 178], nanomagnets [13, 37, 138],
and molecules [21, 30, 108, 109], which all possess specific assets and drawbacks.
While semiconductor QCA systems were successfully fabricated using lithogra-
phy processes [122, 165–167], they are highly sensitive to external disturbances,
thus, requiring cryogenic operation [111]. However, they have been proposed
as a contestant for enabling interoperability of quantum computers [134] and
conventional CMOS technology [49].
Magnetic QCA, nowadays called Nanomagnet Logic (NML) [145], incorporate
single-domain magnets to realize non-volatile devices operating at room temper-
ature [13, 37, 138]. However, NML elements require more area overhead than
other FCN technologies and are limited to clock frequencies of only several hundred
megahertz [136].
Molecular QCA is another promising room temperature candidate but provides
significantly smaller feature sizes that might allow for nanometer devices [20, 90,
147]. Additionally, clock frequencies for this implementation are expected to be
possible in the terahertz range [176]. Unfortunately, fabrication of molecular QCA
is in its infancy with no standardized processes having yet been determined [92,
147].
Even though all contestants allow operations with a remarkably low energy
dissipation that is a number of magnitudes below current MOSFET technologies
[160, 163, 176] and possess logic-in-memory capabilities [96, 117, 140, 173] in](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-34-320.jpg)
![20 2 Preliminaries
addition to their technology-specific properties, large-scale device fabrication is yet
to establish.
However, recent developments in hydrogen lithography enable the creation of
dangling bonds (DBs) on silicon surfaces [1, 2, 84, 141], thereby providing a
highly promising DB-QCA implementation that can potentially be integrated with
MOSFETs and, thus, exploit existing fabrication processes [75, 83, 201].
FCN technologies are the core subject of this book. Even though this work
focuses on algorithmic considerations, the concepts and functionalities of FCN are
introduced in the following sections in an effort to keep this work self-contained.
Further elaborations on the physics involved can be found in the respectively cited
primary literature. Throughout this work, QCA are used as representatives for all
FCN technologies under consideration because they are the most common. Without
loss of generality, this running example shall not favor any specific technological
implementation.
In Sect. 2.3.1, the properties of single FCN cells are reviewed, while Sect. 2.3.2
discusses their arrangement in patterned arrays to realize logic gates. Subsequently,
Sect. 2.3.3 goes over the necessity of clocking, which allows the conceptualization
of larger-scale circuit layouts as elaborated in Sect. 2.3.4.
2.3.1 Cells
As [111] points out, QCA are inspired by and named after the mathematical model
of cellular automata [177] for discrete computation, where the state of each cell
at some time point is determined by the state of its neighbors at the preceding time
point, according to a set of rules. Arguably, the most prominent example of cellular
automata is Conway’s Game of Life proposed by John H. Conway in 1970 and
popularized by [62].
The principles of QCA can be abstracted via description of such mathematical
models as it is discussed in the following.
The basic element of QCA technologies is the cell, which is a device suitable
for positional bit encoding and computation. To this end, four (or six) quantum
dots, which are entities able to confine electric charges, are grouped together in
a quadratically shaped frame sitting on a substrate, hence, composing a QCA
cell [114]. With the quantum dots arranged in the corners (and the center) of the
square, and two charges inserted into the system, Coulomb interaction leads to the
emergence of exactly two stable polarization states and one unexcited state [197].
If the system is excited, the mutual charge repulsion leads to the occupation
of antipodal quantum dots via tunneling, i.e., the charges stabilize on either the
diagonal or antidiagonal.
Example 2.10 Figure 2.4a depicts three QCA cells with the respective aforemen-
tioned charge distributions leading to the polarizations commonly denoted as (from
left to right) P = −1 and P = +1 [116] as well as the unexcited state P = 0 [109].](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-35-320.jpg)
![2.3 Field-coupled Nanocomputing (FCN) 21
Fig. 2.4 Elementary QCA cell devices. (a) Polarization states. (b) Wire segment
In this figure, quantum dots are visualized as circles and occupying charges as black
bullets. The bistable polarizations of QCA cells represent Boolean 0 and 1 states,
respectively [114], while the unexcited state represents null with no retrievable
information to it.2
Several cells that are arranged in close proximity influence each other’s polariza-
tions and, thus, create a tendency to propagate information. This observation leads
to the consequential construction of wire segments.
Example 2.11 A QCA wire segment is depicted in Fig. 2.4b [112]. Assuming an
initial and fixed polarization of the leftmost cell, its impact disturbs the metastability
of adjacent cells and forces them to align their polarizations accordingly, thus,
propagating the signal through the wire, and, eventually, to the rightmost cell.
NML implementation behaves in accordance with the model discussed here.
Instead of quantum dots, its cells consist of single-domain nanomagnets and,
hence, assume magnetizations instead of polarizations [13]. Additionally, wires of
nanomagnets invert their transmitted signal in each step [38]. However, this poses
no limitation on their applicability since an odd number of cells can be assumed to
compensate for this effect.
2.3.2 Gates
More complex topological structures than those of QCA cell wire segments can be
envisioned. In [180], first implementations of logic functions were proposed by
arranging QCA cells in specific ways, which are called gates.
Example 2.12 The structure shown in Fig. 2.5a is called an inverter or a NOT gate
and performs the negation of the signal a applied to the leftmost cell. The inverted
signal is exhibited on the right as ¬a. Applied information is first passed one cell
to the right and then copied to two paths where it is further propagated to the right.
Finally, the inversion happens via the diagonals, of which two symmetric ones are
2 To reiterate, the depiction as four-dot QCA cells is, without loss of generality, used as a running
example visualization and shall not favor any specific technological implementation.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-36-320.jpg)
![22 2 Preliminaries
Fig. 2.5 QCA gates implementing Boolean functions. (a) Negation. (b) Majority
Fig. 2.6 Constant cells enabling AND and OR gates. (a) Conjunction. (b) Disjunction
required for equally reliable output readings for both possible input signals [180].
However, inverters with a single diagonal interaction have been proposed as well
[116].
The QCA arrangement in Fig. 2.5b implements the majority function
(cf. Sect. 2.1.3) of the top a, left b, and bottom c cell and is, hence, called a
MAJ gate. The three input cell polarizations compete for the center cell, where the
highest combined force wins [180]. The result is then propagated to the right. In
this case, a = 0, b = 1, c = 1 = 1.
As discussed in Sect. 2.1.3, the combination of majority and negation functions
leads to the emergence of Boolean universality. To this end, constant signal cells that
possess only one logic state have been proposed [180]. These can be implemented
using cells with merely two quantum dots, hence, enabling the apparent creation
of structures realizing Boolean conjunction and disjunction, which are called AND
gates and OR gates, respectively.
Example 2.13 An AND gate and an OR gate are depicted in Fig. 2.6. The constant
cells are located at the top and are depicted in black with the remaining two quantum
dots visualized as white bullets. When excited, these dots are always occupied
by charges, thus, leading to a fixed polarization. Thereby, the gate in Fig. 2.6a
computes a = 1, b = 1, 0 = ab = 1, while the gate in Fig. 2.6b computes
a = 1, b = 0, 1 = a + b = 1.
In contrast to logic networks, which are merely mathematical models, QCA cells,
and thus gates, are physical entities. That is, they have definite locations onto which](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-37-320.jpg)
![2.3 Field-coupled Nanocomputing (FCN) 23
Fig. 2.7 Further QCA wire entities. (a) Bent wire. (b) Fan-out
they are placed. Consequently, signal distribution is a critical factor, because it
requires the placement of wire routes, which themselves take up space. Therefore,
further wire structures have been developed that allow both signal transportation
around corners and signal duplication [116, 202].
Example 2.14 These structures are depicted in Fig. 2.7. The bent wire segment
shown in Fig. 2.7a is able to transport a value to a perpendicular route, while the
fan-out visualized in Fig. 2.7b copies the applied signal onto two data paths: one
following its original trajectory and another one perpendicular to it.
Every depicted QCA structure can be fabricated in four different orientations:
(1) exactly as shown, (2) rotated by 90°, (3) rotated by 180°, and (4) rotated
by 270°, hence allowing flexibility in device composition. However, QCA is
considered a planar technology, where cell placement is possible in two dimensions
exclusively. QCA’s planarity imposes harsh restrictions on the feasibility of a certain
functionality. To overcome this obstacle, signal distribution networks have been
proposed, which are logical structures built from gates and are able to shift input
vectors to outputs at different relative locations [179]. However, such networks
require large amounts of cells and, thereby, cause a tremendous area overhead that
scales with the number of inputs distributed.
A more elegant solution is the utilization of cells with quantum dot arrangements
rotated by 45°, which enable coplanar wire crossings [180]. Since normally
oriented cells do not interfere with rotated ones, and vice versa, wires of these
two cell types can cross through each other without signal disturbance on either
path [180]. A coplanar wire crossing is depicted in Fig. 2.8a.3 The noninterference
of normal and rotated cells causes a drawback of this implementation as well: extra
cells and area are required for an arrangement that converts a non-rotated signal
into a rotated one that can eventually cross through a regular wire. Furthermore,
the passing rotated wire separates the cells of the regular wire, which weakens its
signal and makes it more prone to disturbance [195]. Finally, coplanar cells are
3 In [180], inverting wires are proposed that utilize an even number of rotated cells. A similar
mechanism can be found in NML wires [38] as elaborated in the preceding section. In DB-QCA,
an inverting wire could be demonstrated with regular half cells, i.e., without the need for rotated
cells or large inverter structures [132].](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-38-320.jpg)
![24 2 Preliminaries
Fig. 2.8 Wire crossings. (a) Coplanar. (b) Second layer
more sensitive to cell displacement fabrication defects than normal cells are [156]
and, thus, necessitate high precision of corresponding manufacturing processes.
A different approach aims at the reduction of corresponding convolution by the
introduction of multiple layers for cell placement [67]. An according second-layer
crossing is depicted from a two-point perspective in Fig. 2.8b. For visual guidance,
the cells of the ground-layer wire segment have been tinted gray. As it can be seen,
this crossing does not require rotated cells but involves the addition of inter-layer via
cells for signal transport into the second layer and back to ground layer. Physically,
these cells are not distinguished from regular cells besides their positioning but are
differentiated in the figure as squares with a large circle inside. The crossing cells,
which are also regular cells, are highlighted by a cross symbol. Second-layer cells
require fabrication overhead and, depending on cell dimensions, multiple stacked
via cells to increase distance from the ground layer to prevent any crosstalk [156].
It is believed that the multi-layer approach is more likely to yield stable wire
crossing signals than the coplanar implementation [195]. Consequently, without
loss of generality, the remainder of this work utilizes second-layer crossings for
visualizations.
In either case, additional expenditure has to be provided if crossings are to be
realized. Therefore, several works suggest reducing wire crossings in an attempt to
lower fabrication costs, e.g., [33, 131].
The QCA gates and wire structures discussed in this section have been proposed
in a similar form for other FCN technologies as well. For instance, [39, 87, 185, 186]
provide implementations of NML gates, while magnetic wire crossings are intro-
duced in [136, 146]. As difference to QCA implementations, nanomagnets with
non-rectangular geometries, the so-called slanted-edge magnets, can be employed
that allow the construction of logic gates with reduced cell count due to their
preference for a certain magnetization [135]. However, as a mere fabrication
characteristic, this circumstance does not alter the applicability of logic-level
considerations. Finally, corresponding DB-QCA implementations of logic gates can
be found in [83, 132].](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-39-320.jpg)
![2.3 Field-coupled Nanocomputing (FCN) 25
2.3.3 Clocking
A QCA wire with an applied input signal cell polarization on either side has exactly
one ground state, namely the according polarization of all other wire cells [115],
e.g., as shown in Fig. 2.4b. Other states are theoretically possible as well, but they,
consequentially, have higher energy levels due to unavoidable opposite polarizations
of at least two adjacent cells. The energy difference between the ground state and
the first excited state is called kink energy [115, 116]. Even though the kink energy
does not decrease with an increasing amount of cells in the wire, the excited states
become increasingly degenerate, i.e., they are more likely to occur in any system at
nonzero temperature [115]. Such kink states express incorrect computation and are
not limited to wires but can arise in any QCA system.
Naturally, this phenomenon limits the amount of cells possible to realize and
the operational temperature of any system fabricated from QCA. To overcome
this restriction, first proposals included the interlacing of QCA with conventional
circuitry that should have acted as latches to buffer computation results obtained
from QCA before feeding them to subsequent QCA stages [115].
However, it was found that the obstacle could be circumvented without the inte-
gration of MOSFET components by separating QCA systems into small decoupled
regions that could only interact on activation of external signals [80]. First attempts
proposed to raise and lower the inter-dot quantum tunneling barriers to transition
cells in a region between the null ground state and the polarized excited states,
thus, coupling and decoupling them from the other parts of the system [113].
Modern approaches rely on increasing and decreasing the energy level of the null
state, which makes it less or more likely to occur, rather than influencing inter-dot
tunneling as it is easier to realize; however, the effect is identical [80, 111, 120].
The discussed principle is referred to as clocking, with the external coupling
signal being the clock [80, 113]. Even though the term is utilized in CMOS
technology as well, its functionality and its purpose differ in the FCN domain.
Both combinational and sequential QCA systems need to be clocked to ensure
signal stability and data flow directions. A clock signal is usually created by an
external clock generator and distributed to the cells through the device substrate
using embedded electrodes [80]. These create electric fields (or magnetic ones in
case of NML [39]) that gradually excite and de-excite the cells in the respectively
controlled region.4
This gradual change can be realized via trapezoidal field intensity modulation
that can be split into four clock phases of length π
2 , which are called switch, hold,
release, and relax, forming a single 2π clock cycle [80]. Cells in the hold phase
are excited and are fixed in either polarization state, while cells in the relax phase
are in the unexcited ground state null. The switch and release phases are gradual
changes between the two other ones. To properly transmit information from one
4 For molecular implementations, [120] provides valuable graphs that vividly illustrate the field
forces, charge distributions, and energy levels of the respective cell states involved.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-40-320.jpg)
![26 2 Preliminaries
Fig. 2.9 QCA wire segment partitioned into clock zones
Fig. 2.10 QCA clock curves and data propagation
cell region to another, four of these trapezoidal clock signals can be utilized, each
with a π
2 offset to their respective preceding one and numbered 1 to 4. Commonly,
NML omits the relax phase and, thereby, only possesses three clock numbers [145].
Cells are grouped together in clock zones controlled by either of the available
clock signals. This way, information can be transmitted from cells controlled by
clock 1 to cells controlled by clock 2, from there to clock 3, to clock 4, and, finally,
back to clock 1 again. Consequently, a pipeline-like behavior of data propagation
emerges.
A QCA wire segment partitioned into clock zones is depicted in Fig. 2.9. The
cell color, the clock zone shade, and the number in the bottom right corner give
redundant indication of the clock controlling the respective zone. Within one full
clock cycle, applied information can be propagated through four clock zones, e.g.,
from the leftmost one indicated by 1 to clock zone 4.
Example 2.15 The stacked diagrams in Fig. 2.10 visualize the clock phases and
resulting data propagation in a partitioned wire. The time is plotted on the shared x-
axis, while each of the four stacked diagrams possesses its own y-axis displaying
clocking field strength. Each of the four clock curves corresponds to the clock
zone on their left. The QCA cells drawn alongside the curves reflect the gradual](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-41-320.jpg)
![2.3 Field-coupled Nanocomputing (FCN) 27
polarization changes of the cells in the respectively controlled clock zone. The
dashed lines separate the x-axis into clock phases. To reiterate, four clock phases
are equal to one clock cycle.
Clock zone 1 starts with a raising clock field, which is the switch phase. The
polarization gradually emerges and stabilizes at the peak, where it is kept in the
subsequent hold phase. At this time point, the adjacent clock zone 2 is in the switch
phase. Its cells are being influenced by the ones from clock zone 1, which are kept
stable. Consequently, the cell polarizations in clock zone 2 align accordingly. For
clock zone 1, the falling slope starts in the third phase, which is the release phase.
Since its information was successfully transmitted to clock zone 2, it is not needed
any longer and the cells can start to de-excite. The final phase before repetition is
the relax phase, in which the cells remain in the null state.
The discussed clocking mechanism is known as Landauer clocking.5 According
to Landauer’s principle, every irreversible computation dissipates energy of at least
W = kB ln 2 per bit erased as heat, where kB is the Boltzmann constant and
T is the surrounding temperature [104]. This principle does not apply to signal
transmissions in QCA wires because no information is being erased [105, 110].
However, any of the gates discussed in the preceding section inevitably dissipates
energy in accordance with Landauer’s principle, when operated using Landauer
clocking [12, 110].
Energy dissipation is one of the key limiting factors of conventional CMOS
scaling, often resulting in Dark Silicon, that is, the obstruction of circuitry to utilize
the entirety of integrated logic simultaneously to prevent burning out [54, 175].
Thereby, MOSFET chips fall way behind their theoretically ideal computational
capabilities due to thermal restraints. Since FCN technologies theoretically allow
for substantially higher device densities, the heat dissipation problem intensifies
even though QCA technologies inherently consume considerably less energy than
MOSFETs [107, 160]. An estimation given in [110] illustrates the situation’s
significance: the authors assume an average footprint per molecular QCA cell of
1 nm × 1 nm and a clock frequency of 100 GHz. They elaborate that this would
lead to a density of 1014 cells per cm2. Additionally, the authors continue, if each
cell were to dissipate merely 0.1 eV per clock period, the system’s power density
would be 160 kW per cm2, which is magnitudes higher than that of a nuclear
fission reactor’s core and would, consequently, virtually immediately vaporize the
system [110].
However, it was shown that utilizing the same four external clock signals to
implement a quasi-adiabatic clocking mechanism, which is referred to as Bennet
clocking, an arbitrarily small amount of energy dissipation can be accomplished,
also for irreversible computations, thus, resolving concerns regarding thermal den-
sity [97, 110, 120, 178]. This capability of sub-Landauer computation is achieved by
altering the clock waves in such a way that signals are kept stable until some desired
5 To the best of the authors’ knowledge, the term was coined in [110].](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-42-320.jpg)
![28 2 Preliminaries
computation has been performed and are subsequently erased in reverse order of
computation [110]. The effective clock rate of a Bennet-clocked system is at least
halved due to the necessary forward and backward signal propagation. Furthermore,
its pipelining capabilities are reduced as only one signal vector can be transmitted
through the system at any time. Since the device architecture itself requires no
adjustments for this change, a Landauer-clocked system could, theoretically, be
switched over to a Bennet-clocked one at any time [110].
The advent of clocking allowed envisioning arbitrarily large QCA systems,
e.g., arithmetic circuits [144], processors [55], and FPGAs [98]. However,
no universal consent for the minimum and maximum clock zone size to use
could be established. Values ranged from single cells up to several hundred ones
controlled by the same clock signal. Since the state-of-the-art physical simulator
QCADesigner [196] supports arbitrary clock zone geometries, little discourse
was held about the technical feasibility. Nevertheless, to reiterate, clock fields are
generated by electrodes that are buried in the substrate and must be fabricated as
well. To support said arbitrary clock zone geometries, it must be feasible to fabricate
electrodes of the size of single QCA cells, hence, this scheme was named cell-based
design. Due to the nanometer cell dimensions of molecular QCA and DB-QCA, this
paradigm is unlikely to be realistic [20].
To the best of the authors’ knowledge, the works [14] and [82] were the first to
propose a different approach that is now referred to as tile-based design: instead of
assigning clock zones arbitrarily, these works suggest relying on regularly arranged
square clock tiles, which could host 5 × 5 and 3 × 3 QCA cells, respectively,
and constructing all gates and wires within these regions. Simulations, which were
taking entanglement of individual quantum-dot cells into account, suggest that it
might be unrealistic for clocked tiles larger than 5×5 cells to propagate information
correctly [174]. Physical clock networks were proposed later in [20]. Recently, [31]
and [149] also confirmed via physical simulations that cell-based clocking should
certainly no longer be pursued.
Example 2.16 Figure 2.11a depicts a QCA structure with cell-based clock assign-
ment indicated by the colors. As can be seen, this approach can lead to various clock
zone geometries of arbitrary size, which are unlikely to be fabricable [20, 31, 149].
In contrast, Fig. 2.11b depicts a single tile-based clock zone of size 5 × 5 cells.
Possible cell positions within the tile are indicated in gray. The QCA wires in
Figs. 2.9 and 2.10 utilize the same tile-based design paradigm with tiles of size
5 × 5 cells.
Various clock zone arrangements, commonly referred to as clock topologies or
clocking schemes, for the tile-based design paradigm have been proposed in the
literature. They act as floor plans for cell placement.
Figure 2.12 depicts cutouts of size 4×4 tiles of three common clocking schemes
usually, but not exclusively, used for QCA technologies. Clocking schemes can be
extrapolated seamlessly in all directions, but each of them provides different assets
and drawbacks. Each tile in these clocking schemes is uniformly sized and can hold
up to a fixed amount of cells, e.g., 3 × 3 or 5 × 5.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-43-320.jpg)
![2.3 Field-coupled Nanocomputing (FCN) 29
Fig. 2.11 Cell-based vs. tile-based design paradigm. (a) Cell-based clock assignment resulting in
clock zones of various geometries. (b) Possible cell locations indicated in a 5 × 5 tile-based clock
zone
Fig. 2.12 Clocking schemes for FCN technologies. (a) 2DDWave [184]. (b) USE [28].
(c) RES [70]
Example 2.17 In Fig. 2.12a, the 2DDWave clocking scheme is sketched. It forms
one of the simplest floor plans, where each antidiagonal is assigned the same clock
number. This way, the incoming information flow to a tile is solely possible from
the northern and western directions, while the outgoing information flow from a tile
always has to utilize the eastern or southern directions. This inherently restricts the
scheme in multiple ways, since, e.g., (1) sequential systems cannot be realized due
to the lack of feedback loops and (2) neither MAJ gates nor 3-output fan-outs are
possible due to the maximum input and output degree of 2 for each tile. The latter
issue occurs in the USE clocking scheme sketched in Fig. 2.12b as well. While USE
does allow feedback, its tiles’ maximum input and output degree is also limited to
2. The RES scheme sketched in Fig. 2.12c overcomes this restriction and allows for
feedback, MAJ gates, and 3-output fan-outs in certain tiles. However, due to the
increased degree in some tiles, the degree in other tiles must, naturally, be lower
as this still is a two-dimensional grid structure. Therefore, FCN systems tend to
become more widespread in the RES scheme and, consequently, have higher area
costs and longer critical paths as confirmed by an experimental evaluation [70].
While predefined clocking schemes seem to impose a restriction on the freedom
of cell placement, contrarily, allow to abstract from cell dynamics and to consider](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-44-320.jpg)
![30 2 Preliminaries
Fig. 2.13 The QCA ONE gate library [148]. (a) MAJ. (b) AND. (c) OR. (d) Inverter. (e) Straight
wire. (f) Bent wire. (g) Fan-out. (h) Crossing
the FCN concept on the logic level. To this end, several gate libraries have been
proposed that provide carefully simulated implementations of elementary Boolean
functions, e.g., [68, 132, 148]. These libraries have been designed in such a way
that their basic gates are of uniform size and, thereby, fit on one tile each. In the
remainder of this work, without loss of generality, the 5×5 QCA ONE gate library is
used as a running example for visualizations [148]. Its elementary gates are depicted
in Fig. 2.13. To this end, each gate is visualized on an arbitrarily clocked tile. As a
matter of course, all gates can be used with any clock number.
Some approaches, furthermore, allow the routing of multiple wire segments
through the same tile as long as they bypass each other with a spacing of at least one
cell [57]. This concept is sometimes referred to as multi-wire routing.
More complex gates, e.g., XOR, can be assembled from these elementary
building blocks as demonstrated in [148]. That is, given some Boolean function
in terms of a logic network, an FCN system realizing that function can be obtained
by mapping the logic network’s nodes onto a clocking scheme, connecting them
with their signals accordingly, and applying an FCN gate library for technology
mapping.
2.3.4 Circuit Layouts
The task of assembling FCN cells by arrangement in the plane and, thereby, realizing
certain functionality defined by a specification is called physical design, as known
from conventional VLSI. Commonly, said specification is given in terms of a logic
network. The resulting assembled FCN system is called an FCN circuit layout,](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-45-320.jpg)
![32 2 Preliminaries
data flow directions, it is possible that tiles, despite being adjacent, cannot exchange
information. Two tiles t1 and t2 are adjacent if {t1, t2} ∈ A. The set of all outgoing
tiles to which some tile t can pass information is denoted t+, while the set of all
incoming tiles from which some tile t can accept information is denoted t−. It holds
that ∀t, t ∈ L : t ∈ t+ ⇐⇒ {t, t} ∈ A∧(c(t)−c(t)) mod clk = 1. Analogously,
∀t, t ∈ L : t ∈ t− ⇐⇒ {t, t} ∈ A ∧ (c(t) − c(t)) mod clk = 1. To this end, clk
is a constant defining the maximum clock number, e.g., clk = 4 in a QCA context
and clk = 3 for NML.7 Correspondingly, the notations A+ and A− are used to refer
to all outgoing and incoming adjacencies in a clocked layout, respectively.
To the best of the authors’ knowledge, FCN circuit layouts have not been
formally defined in the literature. Therefore, the detailed restrictions for the non-
trivial p, r, and c are given in Sect. 3.1 as a contribution of this book. An illustration
is given in the following example for intuition already.
Example 2.18 The logic network depicted in Fig. 2.14a represents the 1-bit multi-
plexer (2:1 MUX) function. It is a ternary Boolean function defined as f = as +bs.
Thereby, it implements an if s then b else a. Its primary input s fans out to
two consecutive nodes, namely, x4 and x6. To realize such a condition in FCN
technologies, a fan-out wire as shown in Figs. 2.7b and 2.13g has to be utilized.
Figure 2.14b displays a functionally equivalent logic network, where the primary
input’s fan-out was substituted by a designated fan-out node labeled F. Figure 2.14c
shows a mapping of said substituted logic network onto a 3 × 3 tiles clocked layout.
Finally, technology mapping using the QCA ONE library yields the FCN circuit
layout visualized in Fig. 2.14d. Primary input cells are colored blue, and the primary
output cell is colored orange.
While the process of technology mapping is rather trivial, the placement and
routing of logic networks is not.8 Since the conceptualization of FCN, many circuit
layouts have been generated manually from logical descriptions, e.g., as aforemen-
tioned, [55, 98, 144]. In most cases, however, practically relevant circuits exceed
human-graspable complexity, which excludes this practice from large-scale design
of FCN layouts. Although there are some algorithmic solutions available, these
approaches produce results of limited quality and do not scale [27, 34, 57, 181].
The planar nature of FCN technologies with only limited capabilities for wire
crossings is a restricting factor in the physical design of circuit layouts that
challenges placement and routing algorithms. However, it is not the only one. As
thoroughly reviewed in the preceding section, the necessity for clocking in both
combinational and sequential circuit layouts leads to the emergence of a striking
property, namely the inherent need for signal synchronization.
7 From a technical perspective, it makes sense to enforce clk ≥ 3 because no directed information
flow is possible otherwise.
8 Formal proofs for this conjecture are given in Sect. 3.2.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-47-320.jpg)
![Chapter 3
Theoretical Groundwork
Physical design bridges the gap between mostly pure logical specifications and
physically fabricable circuitry. The conventional VLSI design flow contains place-
ment, signal routing, clock tree insertion, and timing closure. The underlying
formal problems of these steps have been extensively studied over the past decades,
which have led to academic findings and the discovery of applicable algorithms
(cf. [94, 106] for an overview).
However, these problems are yet to be theoretically investigated for the FCN
domain. A handful of rather greedy solutions are available to tackle the domain-
specific physical design problems with their tightened routing and synchronization
constraints, e.g., [27, 34, 57, 181]. Due to the lack of clear establishment of the
underlying formal problems at the time, these solutions suffer from scalability or
quality issues. It is therefore unknown whether these impairments were caused by
insufficient methodology or complexity reasons.
Theoretical findings aid in the development of efficient algorithms or reveal
that such algorithms do not exist. Also in the latter case, valuable knowledge is
acquired: (1) one can stop wasting resources on trying to find efficient methods
or on running greedy approaches, (2) the formal problem definition acquired in
the process provides a specification for tackling the intractable problem with
satisfiability engines (cf. Chap. 4), and (3) similarities to other (possibly well-
studied) problems become apparent so that findings of their approximations can
be utilized (cf. Chap. 5).
This chapter provides a fundamental basis for any future theoretical and practical
work in the field [189]. In Sect. 3.1, a formal and sound definition of the tile-
based placement and routing problem for FCN circuit layouts is given. Section 3.2
presents intractability proofs (under the assumption P = NP) for the decision and
the optimization variant of the problem in question for various configurations, i.e.,
the relaxation of certain requirements based on real-world design decisions. The
theoretical findings established in this chapter are directly applied in Chaps. 4, 5,
and 6 that present exact, scalable, and one-pass solutions, respectively.
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022
M. Walter et al., Design Automation for Field-coupled Nanotechnologies,
https://doi.org/10.1007/978-3-030-89952-3_3
37](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-51-320.jpg)
![38 3 Theoretical Groundwork
3.1 FCN Placement and Routing Problem Definition
In this section, a formal definition of the placement and routing problem for tile-
based gate-level FCN circuit layouts is given [189]. As reviewed in Sect. 2.3,
placement, signal routing, and timing closure are highly interdependent in the FCN
domain. For this reason, they can be best formulated as a joint problem. First,
the decision problem variant is introduced and then extended to an optimization
problem.
Definition 3.1 Let the decision problem of tile-based gate-level FCN placement
and routing be called FCNPR. Its inputs are an empty, unclocked layout L =
(G, N, p, r, c) of fixed size, i. e., |L| tiles, and a constant clk ∈ N that represents the
number of clock phases in the technology. To keep this problem definition as generic
as possible, here, G is not restricted to a grid graph or any regular topological shape.
There must, however, be a relation A ⊆ T × T that defines adjacency between the
tiles. The logic network N can represent any Boolean function but it is assumed that
there exists a gate library that contains uniform single-tile implementations of all
utilized logic node types. Alternatively, N has first to be substituted to conform to
this restriction.
FCNPR evaluates to true for L and clk iff there exists a 3-tuple of injective
mappings (p, r, c), where p : → T is the gate placement, r : → PL is the
wire routing,1 and c : T → {1, . . . , clk} is the clock number assignment, such that
the following constraints hold:
1. Routing constraint: Each signal connecting the nodes xi and xj in the logic
network is routed on the layout in such a way that it starts at the tile t1, where xi is
placed, ends at the tile tn where xj is placed, and does not cross any gate (crossing
other wire segments, however, is allowed). This can be formally expressed as
∀σ = (xi, xj ) ∈ : ((r(σ) = τ = {t1, . . . , tl}) ⇒ (t1 = p(xi) ∧ tl =
p(xj ))) ∧ ∀x ∈ N : p(x) /
∈ τ {t1, tl}.
2. Local Synchronization Constraint: For each routed signal, the clock numbers
must be assigned to the affected tiles such that they are consecutively numbered.
This can be formulated as: ∀σ = (xi, xj ) ∈ : (r(σ) = {t1, . . . , tl}) ⇒
∀k ∈ {2, . . . , l} : ((c(tk) − c(tk−1)) mod clk = 1).
3. Global Synchronization Constraint: All two paths in the logic network, starting
at some primary inputs and sharing a common last node, must pass through the
same amount of tiles when routed on the layout to compensate delay differences.
This can be formally expressed as: ∀p1, p2 ∈ PN (x), p1 = {xi, . . . , x}, and
p2 = {xj , . . . , x} : |r(xi, x)| + c(p(xi)) = |r(xj , x)| + c(p(xj )), where ∀x ∈
N : (x, xi), (x, xj ) /
∈ , and p1, p2 are disjoint except for x. Additionally, PN
is defined analogously to PL, while |P| denotes the length of a path P.
1 Let PL denote the set of all cycle-free paths in L and let paths be ordered (multi-)sets of tiles.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-52-320.jpg)
![40 3 Theoretical Groundwork
FCNPR’s NP-hardness is shown next by a polynomial-time reduction from the
well-known Hamiltonian path problem (HPP) to FCNPR.
Definition 3.3 HPP is a decision problem that was shown to be NP-complete [63].
It receives a (directed) graph G = (V, E) as input. Its output is true iff there exists
a path in G that contains each vertex exactly once.
Lemma 3.2 FCNPR is NP-hard.
Proof To a given instance of HPP, an instance of FCNPR is constructed in
polynomial time, so that they are equisatisfiable, i. e., a polynomial-time reduction
HPP ≤P FCNPR is conducted. It follows directly that iff an oracle provided a
solution for the FCNPR instance, a solution for the HPP instance can be deduced.
Thus, HPP cannot be harder than FCNPR. The reduction is as follows.
Given a directed graph G = (V, E) with m vertices. It is to be decided
whether HPP returns true for G, i. e., if G is an element of the language LHPP.
Construct a logic network N = (, I, , O) in a way that = V , I = {x1},
= {(x1, x2), (x2, x3), . . . , (xm−1, xm)}, and O = {f }, with f = xm, xi ∈ ∪ I,
i. e., a chain of all m nodes.2 This can be done in linear time. In the following,
G serves as a layout for N. Since the number of G’s vertices and N’s nodes is
identical, a bijective gate placement p is possible. It is, thus, also is injective by
definition and, consequently, satisfies FCNPR’s requirement. If the wire routing r
can be employed while meeting the routing constraint, a Hamiltonian path has been
found. This means, if the nodes are placed in a way that they are directly adjacent
on the layout if they are adjacent in the logic network, the routing constraint can be
fulfilled. Nonetheless, the local synchronization constraint must be met as well, to
truly satisfy FCNPR. If the embedding is possible thus far, c can be chosen so that
the tile onto which node xi is placed is assigned clock number i mod clk, because
propagating information through a chain is exclusively possible this way. Finally,
the global synchronization constraint is trivially satisfied because there are no two
paths that are disjoint except for their last node in the logic network.
As a consequence, HPP holds for G iff FCNPR holds for G with N, i. e., iff it is
possible to embed the m-node chain in G. Thus, FCNPR is NP-hard.
Example 3.1 To provide a visual intuition of how the node chain embedding works,
which is the core of the reduction, the task of finding a Hamiltonian path in a 3 × 3
grid graph is considered as an example. The graph consists of 9 vertices, i.e., a 9-
node chain is created, like the one shown in Fig. 3.1a. If it is possible to embed
this chain in the grid graph, i. e., determining mappings p and r, a Hamiltonian
path has been found that starts at the vertex where the first node is placed and
ends at the vertex where the last node is placed. This is depicted in Fig. 3.1b. As it
can be seen, determining the clocking c becomes trivial afterward by consecutively
clock-numbering along with the chain, hence, satisfying the local synchronization
2 It is assumed that there is a respective node supported by a gate library. Thus for, the identity
function, i. e., wire segments, or inverters can be employed.](https://image.slidesharecdn.com/18800132-250610051112-8e3bfb94/85/Design-Automation-For-Fieldcoupled-Nanotechnologies-Marcel-Walter-54-320.jpg)
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GOVERNOR OF EQUATORIA
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Design Automation For Fieldcoupled Nanotechnologies Marcel Walter
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- 5. MarcelWalter RobertWille Frank SillTorres Rolf Drechsler Design Automation for Field-coupled Nanotechnologies
- 6. Design Automation for Field-coupled Nanotechnologies
- 7. Marcel Walter • Robert Wille • Frank Sill Torres Rolf Drechsler Design Automation for Field-coupled Nanotechnologies
- 8. Marcel Walter University of Bremen Bremen, Germany Robert Wille Johannes Kepler University Linz, Austria Frank Sill Torres German Aerospace Center (DLR) Bremerhaven, Germany Rolf Drechsler University of Bremen and DFKI GmbH Bremen, Germany ISBN 978-3-030-89951-6 ISBN 978-3-030-89952-3 (eBook) https://doi.org/10.1007/978-3-030-89952-3 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
- 9. Dedicated to the loving memory of Barbara Walter (1932–2019) Thank you, Grandma. Yours, Marcel.
- 10. Preface Since the invention of integrated digital circuits, which heralded the beginning of the information age, their fabrication capabilities underwent rapid progress. Considering their transistor density doubled every few years since the 1960s, the physical limits of miniaturization will soon be reached. Consequently, novel paradigms are needed to enable computation-intensive future-oriented technologies such as artificial intelligence, autonomous driving, and immersive virtual reality. Field-coupled nanocomputing (FCN) is a class of post-CMOS emerging inte- grated circuit technologies that includes contestants with enhancements in terms of energy dissipation and feature size. Certain implementations indicate the possibility to realize molecular-sized elementary devices with ultra-low energy dissipation or clock frequencies in the terahertz range. Despite their promising characteristics, sophisticated automatic design methods are yet to be established. Due to the peculiarity and specificity of the FCN technologies’ design constraints, conventional physical design algorithms cannot be applied. In other words, design automation for an entire class of highly promising nanotechnologies that could potentially enable a future of powerful and green computational devices is still in its infancy. This book considers the main tasks in the area of design automation for FCN technologies that must be proficiently understood to enable large-scale composition of elementary building blocks to obtain correct systems from given function specifications. To this end, a holistic design flow is presented that covers • Exact and scalable placement and routing • One-pass logic synthesis • Novel clocking mechanisms for data synchronization • Formal verification for obtained circuit layouts Additionally, theoretical groundwork is presented that lays the foundation for any algorithmic consideration in the future. Furthermore, an open-source and publicly available FCN design framework called fiction, which contains implementations of all discussed techniques, is presented. vii
- 11. viii Preface The presented approaches address obstacles that have existed since the concep- tualization of the FCN paradigm and could not be resolved since then. Thereby, this book substantially advances the state of the art in design automation for FCN technologies. Bremen, Germany Marcel Walter Linz, Austria Robert Wille Bremerhaven, Germany Frank Sill Torres Bremen, Germany Rolf Drechsler June 2021
- 12. Acknowledgments Neither this book nor the included research work would have been possible without the support of exceptional people and institutions. We would like to seize the opportunity to express our gratitude towards them. We are exceptionally grateful for the wonderful colleagues we have been fortunate to work with in the Research Group for Computer Architecture (AGRA) at the University of Bremen, and to the University of Bremen itself. Special thanks to authors of all the chapters that provided a sturdy foundation to the work and research portrayed in this book. Furthermore, our gratitude extends to all the researchers currently utilizing the fiction framework in their work. It is an honor to assist in the extension of the domain of field-coupled nanotechnologies. In addition, we want to especially acknowledge Gregor Kuhn, who beautifully implemented the SVG layout export. Many thanks also go to Mario Kneidinger, Till Schlechtweg, and Fabrizio Riente for code contributions. Also, we would like to thank Mathias Soeken for allowing the use of parts of his code in fiction. Adjacently, we give our thanks to Nikolaj Bjørner for implementing particular feature requests into the Z3 SMT solver, and Alan Mishchenko for his guidance and for sharing his knowledge about incremental satisfiability solving. Furthermore, we would like to thank José Augusto M. Nacif for providing the logic networks that he used as benchmarks in his works, which enabled the performance of comparative experimental evaluations. Moreover, we would like to offer our gratitude to those outside of our specific working environment who provided unwavering support in the creation of this book and the work contained within it. Specifically, Bella Gardner, Stefan Hillmich, Rune Krauß, and Dan Sörgel as well as Antje and Richard Heinemann. ix
- 13. x Acknowledgments For funding, we thank the Collaborative Research Center (Sonderforschungsbe- reich) 1320 EASE – Everyday Activity Science and Engineering. Finally, we thank Springer Nature and especially Charles “Chuck” Glaser for publishing this work. Bremen, Germany Marcel Walter Linz, Austria Robert Wille Bremerhaven, Germany Frank Sill Torres Bremen, Germany Rolf Drechsler June 2021
- 14. Contents 1 Introduction ................................................................. 1 2 Preliminaries ................................................................ 7 2.1 Logic Representations ................................................. 7 2.1.1 Boolean Functions............................................. 7 2.1.2 Truth Tables.................................................... 9 2.1.3 Logic Networks................................................ 10 2.2 Satisfiability Solvers ................................................... 13 2.2.1 Boolean Satisfiability (SAT) .................................. 14 2.2.2 Satisfiability Modulo Theories (SMT) ........................ 15 2.3 Field-coupled Nanocomputing (FCN) ................................ 19 2.3.1 Cells............................................................ 20 2.3.2 Gates ........................................................... 21 2.3.3 Clocking ....................................................... 25 2.3.4 Circuit Layouts ................................................ 30 3 Theoretical Groundwork .................................................. 37 3.1 FCN Placement and Routing Problem Definition .................... 38 3.2 Intractability Proofs for FCN Placement and Routing ............... 39 3.3 Summary and Future Work............................................ 44 4 Exact Placement and Routing ............................................. 47 4.1 General Idea............................................................ 48 4.2 Formulation as an SMT Problem ...................................... 49 4.2.1 Global Synchronization ....................................... 54 4.2.2 Predefined Clocking Schemes ................................ 55 4.2.3 Wire Crossings ................................................ 56 4.2.4 Border I/O Pins ................................................ 58 4.2.5 Secondary Optimization Criteria ............................. 59 4.3 Incremental and Parallel Solving ..................................... 61 4.3.1 Incremental Solving ........................................... 61 4.3.2 Parallel Solving................................................ 66 xi
- 15. xii Contents 4.4 Experimental Results .................................................. 69 4.4.1 Implementation and Setup .................................... 69 4.4.2 Quality Comparison Against State-of-the-Art Algorithms .. 70 4.4.3 Design Space Exploration..................................... 73 4.4.4 Benefit of Incremental Solving ............................... 74 4.5 Summary and Future Work............................................ 77 5 Scalable Placement and Routing.......................................... 79 5.1 The Impact of Logic Network Preprocessing ........................ 80 5.2 Relation to Orthogonal Graph Drawing .............................. 83 5.3 Addressing FCN Design Constraints ................................. 85 5.4 Resulting Algorithm ................................................... 88 5.5 Experimental Results .................................................. 92 5.5.1 Implementation and Setup .................................... 92 5.5.2 Scalability Comparison Against State-of-the-Art Algorithms ..................................................... 92 5.6 Summary and Future Work............................................ 96 6 One-Pass Synthesis ......................................................... 99 6.1 Shortcomings of Two-Step Physical Design ......................... 100 6.2 General Idea............................................................ 102 6.3 Formulation as a SAT Problem ........................................ 103 6.4 Experimental Results .................................................. 107 6.4.1 Implementation and Setup .................................... 107 6.4.2 Quality Comparison Against Placement and Routing ....... 108 6.4.3 Generating a Design Library.................................. 110 6.4.4 Further Benefits of the One-pass Scheme .................... 112 6.5 Summary and Future Work............................................ 113 7 Exploiting Clocks for Synchronization ................................... 115 7.1 Global Synchronization Revisited .................................... 116 7.1.1 Combinational Circuits ....................................... 116 7.1.2 Sequential Circuits ............................................ 119 7.2 Synchronization Elements............................................. 121 7.2.1 Basic Latch .................................................... 121 7.2.2 D Latch ........................................................ 124 7.3 Experimental Results .................................................. 126 7.3.1 Implementation and Setup .................................... 127 7.3.2 Relieving Global Synchronization............................ 129 7.3.3 Adapting Conventional Methods to FCN .................... 131 7.4 Summary and Future Work............................................ 133 8 Formal Verification ......................................................... 135 8.1 Problem Discussion and General Idea ................................ 136 8.2 Verification Approach ................................................. 138 8.2.1 Miter Structure ................................................ 138 8.2.2 Enforcing Proper Synchronization ........................... 139
- 16. Contents xiii 8.2.3 Resulting Equivalence Checking Process .................... 143 8.3 Experimental Results .................................................. 145 8.3.1 Implementation and Setup .................................... 145 8.3.2 Validation of Physical Design Algorithms ................... 145 8.4 Summary and Future Work............................................ 148 9 fiction: A Holistic Open-Source Framework............................. 151 9.1 Related Work on FCN Design Tools.................................. 152 9.1.1 QCADesigner.................................................. 152 9.1.2 ToPoliNano and MagCAD .................................... 152 9.1.3 NMLSim ....................................................... 153 9.1.4 Ropper ......................................................... 154 9.1.5 SiQAD ......................................................... 154 9.2 The User’s Perspective ................................................ 155 9.2.1 The Command-Line Interface ................................ 155 9.2.2 Specifications to Be Realized ................................. 157 9.2.3 Physical Design................................................ 158 9.2.4 Validation and Verification.................................... 160 9.2.5 Scripting for Experimental Evaluations ...................... 162 9.2.6 Full User Documentation ..................................... 163 9.3 The Developer’s Perspective .......................................... 173 9.3.1 Third-Party Libraries .......................................... 174 9.3.2 Architecture and Data Types.................................. 177 9.3.3 Implementing a Naive Placer ................................. 180 9.4 Summary and Future Work............................................ 182 10 Summary and Conclusions ................................................ 185 References......................................................................... 187
- 17. Chapter 1 Introduction Research and engineering work throughout the first half of the twentieth century led to the invention of the first metal-oxide-semiconductor field-effect transistor (MOS- FET) [95], which is the dominating building block for digital systems to date. The invention of MOSFETs enabled the digital revolution and heralded the beginning of the information age. The composition of MOSFETs facilitated the realization of the first integrated circuits and, shortly after, of microprocessors. Gordon E. Moore, a co-founder of Intel Corporation, was the first person to actively study the rapid progression in the fabrication of these processors. As early as 1965, he predicted a temporal development, which was later named Moore’s law in his honor. He postulated that the transistor density, and, thus, the computational power, of microchips would double every 18–24 months [129]. For decades, this law remained valid, partially becoming a self-fulfilling prophecy in the industry. However, any exponential growth must eventually arrive at an impassable barrier due to its inability to exceed the limitations imposed by physics. In recent years, a flattening of the growth of transistor density could be observed. One of the main limiting factors in present complementary metal-oxide- semiconductor (CMOS) [198] scaling is, in fact, energy dissipation. Even though Robert H. Dennard and his coauthors postulated in 1974 that the energy density of MOSFETs would stay constant with miniaturization [45], this principle, often referred to as Dennard scaling, is outweighed by leakage and parasitic effects occurring at current process nodes [54]. Consequently, the thermal density of modern processors strictly limits frequency scaling and prevents the simultaneous utilization of certain chip regions to avoid overheating. The areas forced to be inactive are commonly called Dark Silicon [54, 175]. Estimates suggest that for any technology node below 8 nm, which corresponds to current fabrications, at least 50% of a chip’s area has to be dark [54]. Nonetheless, to enable technologies such as artificial intelligence, autonomous driving, and immersive virtual reality, more powerful computational systems will be continuously needed. However, due to the discussed effects and the increasing © The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 M. Walter et al., Design Automation for Field-coupled Nanotechnologies, https://doi.org/10.1007/978-3-030-89952-3_1 1
- 18. 2 1 Introduction ubiquity of digital systems, worldwide energy consumption allotted to information and telecommunication is growing rapidly. Some scenarios predict that the sector could reach as much as 51% of global electricity usage by 2030 and, thereby, contribute up to 23% of the globally released greenhouse gases [7]. Therefore, current research aims to establish new materials and building blocks that enable extremely low-power computational paradigms, hence, facilitating further miniaturization and large-scale integration by a reduction of on-chip thermal density while reducing overall worldwide power consumption in an attempt to engage climate change. Field-coupled nanocomputing (FCN) [6] is a class of post-CMOS emerging nanotechnologies that conduct computations without the flow of electric current but via the repulsion of physical fields. FCN does not utilize transistors but elementary devices called cells, which are building blocks with enhancements in terms of energy dissipation and feature size. Certain implementations indicate the possibility to realize nanometer cells [90, 147] with energy dissipation below the Landauer limit [97, 104, 110, 120, 178] or clock frequencies in the terahertz range [176]. Inspired by the mathematical model of cellular automata [177], in 1993, Craig S. Lent and his coauthors proposed the concept of Quantum-dot Cellular Automata (QCA) [113, 115, 116]. QCA is an FCN technology, for which several physical implementations have been discussed in the literature, e.g., semiconduc- tors [143, 166–168, 178], nanomagnets [13, 37, 138], molecules [21, 30, 108, 109], and silicon dangling bonds [75, 83, 201]. Essential to all implementations is the concept of positional information encoding and in-memory computation due to the bistable confinement of charges. A charged cell influences adjacent ones and enforces them to polarize accordingly [197]. Due to the bistable charge distribution, binary values can be encoded and transmitted via repulsion [114, 116]. Topological arrangements of cells into patterned arrays yield wire segments, majority gates, and inverters, i.e., universal building blocks of combinational circuitry [112, 180]. These characteristics make FCN technologies promising candidates for the augmentation or substitution of MOSFETs. Furthermore, multiple institutes, e.g., the Department of Nanoscale Information and Communications Technology at the University of Alberta or the Research Group of Microsystems and Nanotechnology at the Uni- versity of British Columbia, as well as the research enterprise Quantum Silicon Inc., are actively investigating physical implementations of FCN technologies. However, in the FCN domain, a multitude of novel design challenges arise that differ in their nature from the ones enforced in most CMOS technologies: clocking is a necessity for both combinational and sequential FCN circuits alike because it stabilizes signals and directs information flow [80, 113]. Nonetheless, the clocking paradigm itself leads to the emergence of data synchronization issues that require careful attention in order not to accidentally induce unintended, or worse, undefined, behavior. Furthermore, wire segments and gates are created from the same building blocks and, thus, share the same area requirements and signal delay properties. Additionally, FCN technologies are considered to be planar with limited wire crossing capabilities, which quickly convolutes placement and routing.
- 19. 1 Introduction 3 These challenges directly influence the obtainment of FCN circuit layouts from specifications. While large FCN systems like arithmetic circuits [144], processors [55], and FPGAs [98] have previously been envisioned, these have been generated manually. However, practically relevant circuits exceed human- graspable complexity, which excludes this practice from the large-scale design of FCN layouts. Although there are some algorithmic solutions available, these approaches produce results of limited quality and do not scale [27, 34, 57, 181]. Due to their peculiarity in terms of design constraints, conventional physical design algorithms cannot be applied to the FCN domain. In other words, design automation for an entire class of highly promising nanotechnologies that could potentially enable a future of powerful and green computational devices is still in its infancy. This book considers the main tasks in the area of design automation for FCN technologies that must be proficiently understood to enable large-scale composition of elementary building blocks to obtain correct systems from given function specifications. To this end, a holistic design flow is presented that covers • exact and scalable placement and routing, • one-pass logic synthesis, • novel clocking mechanisms for data synchronization, and • formal verification for obtained circuit layouts. Additionally, theoretical groundwork is presented that lays the foundation for any algorithmic consideration in the future. Furthermore, an open-source and publicly available FCN design framework called fiction, which contains implementations of all discussed techniques, is presented, thus, supporting open research by making all claims throughout this book reproducible. More precisely, this work makes contributions to the following topics. Theoretical Groundwork (Chap. 3) Decades of theoretical investigation led to the consolidation of knowledge in the area of physical design for CMOS circuitry [94, 106]. The first step toward a similar comprehensive theoretical understanding in the FCN domain is provided [189]. Therefore, the placement and routing problem is formally defined in two variants: once as a decision problem and once as an optimization problem. Both of them are proven to be intractable under the assumption P = NP. Along with the initial definitions, several adjustments are made to factor in real-world design decisions. It is also proven that for these configurations, the complexities remain unchanged. To the best of the authors’ knowledge, no such exploration has been conducted before while taking the peculiar FCN constraints into account. Exact Placement and Routing (Chap. 4) The inferred intractability of said problems is taken as a justification for the application of formal methods. An exact algorithm for placement and routing of FCN circuit layouts based on SMT solving is presented [188]. Henceforth, for the first time, the obtainment of minimal layouts, in terms of area, from given logic network specifications becomes feasible. For the realization of the presented
- 20. 4 1 Introduction method, the findings from Chap. 3 are utilized to construct iterative, incremental, and parallel SMT formulations that encode the placement and routing problem. Various parameters allow for the usage of predefined clocking schemes as well as the toggling of global synchronization, wire crossings, and border I/O pins, and the application of secondary optimization criteria. Thereby, sophisticated design space exploration becomes possible. Scalable Placement and Routing (Chap. 5) While the exact algorithm for placement and routing generates solutions of optimum quality in terms of the circuit layout area, its scalability is inherently limited by the problem’s intractability. Limiting factors of the problem domain and existing algorithms are identified to present an approximation via utilization of graph- theoretical findings [15, 16, 53]. By restricting certain degrees of freedom like the underlying clocking scheme and logic network structure, a scalable algorithm for placement and routing emerges that offers polynomial complexity in both time and space without the loss of Boolean expressive power [190, 192]. It, thereby, enables the automatic design of circuit layouts for logic networks with tens of thousands of nodes within seconds. Thus, compared to former state-of-the-art algorithms, a scalability improvement of several orders of magnitude is achieved. One-Pass Synthesis (Chap. 6) Since logic networks are usually obtained by conventional logic synthesis approaches, they are optimized with respect to abstract or conventional cost metrics such as the number of gates, area, depth, etc. that, however, do not apply to FCN circuit layouts in the same way. Final FCN costs highly depend on the utilized clocking scheme and the network structure. Consequently, using logic networks as an intermediate step frequently leads to a substantial quality loss. These obstacles are addressed by proposing a one-pass synthesis scheme for FCN circuit layouts that conducts logic synthesis and physical design holistically in a single run and which does not rely on logic networks as an intermediate step [194]. The deductive power of satisfiability solvers is used once more. At the same time, the presented approach also offers a high degree of flexibility and can be parameterized with various design features, such as wire crossings, gate libraries, and clocking schemes to restrict or loosen certain constraints and, thereby, leverage the required runtime overhead. Exploiting Clocks for Synchronization (Chap. 7) Signal synchronization in FCN is one of the most fundamental differences compared to CMOS technologies. To this end, a detailed investigation reveals that certain synchronization restrictions are, in fact, not mandatory but mere optional constraints of valid combinational and sequential FCN circuit layouts [162, 164]. A methodol- ogy, for driving and stalling primary inputs, is discussed, which enables the correct operation of layouts formerly assumed to be defective. Furthermore, the exploitation of external clock generators as a technology extension to the FCN concept is presented. Via the introduction of asymmetric memory clocks, layout tiles can be transformed into synchronization elements that stall signals over multiple clock
- 21. 1 Introduction 5 cycles as verified with a physics simulator, thus, facilitating novel methodologies for FCN circuit layout design [161, 200]. A case study demonstrates the utilization of synchronization elements as the missing link between conventional physical design algorithms and the FCN domain. Henceforth, synchronization elements might have a substantial and significant impact on future research in the field as they finally enable the application of decades of research results on automatic design techniques to FCN technologies. Formal Verification (Chap. 8) Since conventional methods used for the verification of CMOS circuitry do not apply to the FCN domain due to signal synchronization differences, a novel technique is introduced [193]. It enhances said conventional methods to adapt them to FCN circuit layouts. As a representative verification problem, equivalence checking is examined. Via a combination of a conventional SAT encoding using miter structures and a novel ILP encoding for signal synchronization, a methodology emerges that can verify the correctness of FCN circuit layouts with millions of tiles within minutes. Furthermore, it yields synchronization values for primary inputs to balance desynchronized layouts and computes overall delay. fiction: A Holistic Open-Source Framework (Chap. 9) Finally, an extensible open-source framework for design automation of FCN circuit layouts is presented that is publicly available on GitHub [66, 191]. The fiction framework was developed alongside the research for this book. The presented algorithms are implemented within the said framework to support open research and to make all claims reproducible. To facilitate future research in this field, fiction provides core data types needed by a multitude of design automation algorithms, e.g., logic networks, FCN layouts on different abstraction levels, clocking schemes, and gate libraries. Furthermore, file input and output functionalities are given that allow convenient exchange with logic synthesis and physical simulation tools. For experimental evaluations, fiction provides rich scripting and logging functionalities. Thereby, it is providing a comprehensive sandbox for designers, researchers, and developers in the FCN domain. In summation, the contributions made in this book create a comprehensive design flow for FCN technologies. In contrast to prior work in the domain, this enables the automatic synthesis, placement, routing, clocking, formal verification, and physical simulation of circuit layouts from logical specifications [187]. Furthermore, theo- retical groundwork assists future research in the field by identification of obstacles and opportunities. Finally, the holistic design framework fiction serves as an open- source sandbox for designers, researchers, and algorithm developers by providing implementations of all presented approaches.
- 22. Chapter 2 Preliminaries In an effort to establish this book as a stand-alone work, this chapter introduces important fundamentals and notations necessary for the comprehension of this endeavor. First, Sect. 2.1 goes over various forms of logic representations and data structures. These form the basis for considerations throughout all the remaining chapters. Next, Sect. 2.2 discusses satisfiability problems of prepositional and first- order logic together with optimized solvers for practical applications. Algorithms presented in three chapters throughout this work make heavy use of respective solving engines and require this previous knowledge. Finally, Sect. 2.3 introduces the technology class concept that is field-coupled nanocomputing from both a physical and a more formal point of view. Field-coupled nanocomputing is the host technology for all algorithms presented in this work and thereby its focal point. 2.1 Logic Representations The Boolean calculus formulated by George Boole in 1847 (and later named in his honor) provides the basis for all digital computer systems to this date, by allowing to describe, manipulate, and reason about logical functions [22]. In the following, Boolean functions are introduced in Sect. 2.1.1. Subsequently, two representations for Boolean functions are discussed, namely truth tables in Sect. 2.1.2 and logic networks in Sect. 2.1.3. 2.1.1 Boolean Functions The aforementioned Boolean calculus defines algebraic structures. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 M. Walter et al., Design Automation for Field-coupled Nanotechnologies, https://doi.org/10.1007/978-3-030-89952-3_2 7
- 23. 8 2 Preliminaries Definition 2.1 Given a finite set S, two binary functions · : S × S → S and + : S × S → S, and one unary function ¬ : S → S, the tuple (S, ·, +, ¬) is called a Boolean algebra iff the following constraints hold for all a, b, c ∈ S: a · b = b · a a + b = b + a a · (b + c) = (a · b) + (a · c) a + (b · c) = (a + b) · (a + c) ∃1 ∈ S : a · 1 = a ∃0 ∈ S : a + 0 = a ∃0 ∈ S : a · ¬a = 0 ∃1 ∈ S : a + ¬a = 1. These constraints are referred to as commutativity, distributivity, neutrality, and complementarity. The definition as given here is based on an addition to Boolean calculus by Edward V. Huntington [85, 86]. Further properties of Boolean algebras can be immediately derived from this definition, including but not limited to associativity, idempotence, extremality, involution, duality, absorption, and De Morgan’s laws [85, 86]. As done in Definition 2.1, the infix notation can be used for the functions of Boolean algebras for convenient readability. Further common notations include the usage of ∧ and ∨ instead of · and + as well as a instead of ¬a. In general, the term Boolean algebra often refers to the special two-element Boolean algebra. Definition 2.2 The tuple (B, ·, +, ¬), where B := {0, 1}, and a · b := 1 ⇐⇒ a = b = 1, a + b := 0 ⇐⇒ a = b = 0, ¬a := 1 ⇐⇒ a = 0, is a Boolean algebra and is called two-element Boolean algebra. Its functions are usually referred to as conjunction (AND), disjunction (OR), and negation (NOT). Elements of the Boolean set B are called Boolean variables or binary digits (bits). In propositional logic, the zero element 0 ∈ B is interpreted as false, while the one element 1 ∈ B is interpreted as true. A benefit of using algebraic notation is the intuitive inference of operation order when omitting brackets. Functions defined on sets of Boolean variables are called Boolean functions. Definition 2.3 A function f : Bn → B, where n ∈ N, is called a Boolean function. Conjunction, disjunction, and negation are Boolean functions. Analogously, a function f : Bn → Bm, where n, m ∈ N, is called multi-output Boolean function and can be interpreted as f = (f1, . . . , fm), where fi : Bn → B, for all 1 ≤ i ≤ m.
- 24. 2.1 Logic Representations 9 Boolean functions can be denoted in a manifold of ways. Common representa- tions are conjunctive normal form (CNF) and disjunctive normal form (DNF). Definition 2.4 A Boolean function notated as a conjunction of disjunction terms is said to be in conjunctive normal form. This is equivalent to the scheme i j (¬)xij , where i, j ∈ N and xij ∈ B. Disjunction terms are also called clauses and are disjunctions of literals. Literals are negated or non-negated Boolean variables. Analogously, a Boolean function notated as a disjunction of conjugation terms is said to be in disjunctive normal form. This is equivalent to the scheme i j (¬)xij , where i, j ∈ N and xij ∈ B. Here, conjunction terms are also called clauses and are conjunctions of literals. Literals are negated or non-negated Boolean variables. All Boolean functions can be denoted in both CNF and DNF. 2.1.2 Truth Tables Since Boolean functions are defined on the finite set B, it is possible to enumerate their respective domain in a finite number of steps. Definition 2.5 An ordered listing of all elements of the domain with their corre- spondences, i.e., images, in the codomain of a Boolean function, is called a truth table. Example 2.1 Truth tables for the Boolean functions conjunction, disjunction, and negation are depicted in Fig. 2.1. The left parts of the truth tables enumerate their respective domains, while the right parts depict their images. Given the truth table representation, it becomes apparent that it is possible to not only enumerate their domains but to enumerate Boolean functions themselves as well. Interpreting the right side of a truth table as a binary string (with the top bit being the LSB), the original Boolean function can be reconstructed unambiguously. Example 2.2 The truth tables in Fig. 2.1a and b have binary representations 1000 and 1110, respectively. The truth table in Fig. 2.1c has binary representation 01. A binary string of length l encodes a Boolean function f : Bn → B, where n = log2(l). Multi-output Boolean functions can be encoded as a tuple of binary strings, each of length l = 2n.
- 25. 10 2 Preliminaries Fig. 2.1 Truth tables of common Boolean functions As a direct consequence of the rather lengthiness of truth table descriptions as binary strings, they can be translated into decimal or, more commonly, hexadecimal notation. Example 2.3 Given binary, decimal, and hexadecimal notations, the conjunction in Fig. 2.1a can be represented as 10002 = 810 = 816, the disjunction in Fig. 2.1b can be represented as 11102 = 1410 = e16, and the negation in Fig. 2.1c can be represented as 012 = 110 = 116. Hexadecimal notation is generally prefixed with a 0x and not suffixed with an indexed 16 in the computer science domain to ensure ASCII compatibility. Consequently, the resulting representations from the previous example are 0x8, 0xe, and 0x1. 2.1.3 Logic Networks The truth table representation of Boolean functions grows exponentially in size with respect to their dimension n. It is, therefore, only suited to denote rather small functions. To overcome this restriction, various other forms of Boolean function representations have been proposed over the decades. One that has proven especially useful is the notion of logic networks [42]. Informally, a logic network is a graph-like structure with function labels assigned to its nodes. Thereby, it resembles a combinational circuit but abstracts from physical behavior and only considers the logic level. A common formal definition was introduced by Donald E. Knuth as he described Boolean chains [100]. Definition 2.6 A Boolean chain of a multi-output Boolean function f : Bn → Bm over the variables x1, . . . , xn is a sequence of r steps (xn+1, . . . , xn+r). Each step combines two arbitrary preceding ones, where x1, . . . , xn are considered designated primary inputs. Each combination of two steps is defined as xi = xj(i)◦i xk(i), where n + 1 ≤ i ≤ n + r, and 1 ≤ j(i), k(i) i. The operator ◦i is an arbitrary binary Boolean function. Finally, for 1 ≤ j ≤ m, it must hold that fj (x1, . . . , xn) = xl(j), where 0 ≤ l(j) ≤ n + r.
- 26. 2.1 Logic Representations 11 Fig. 2.2 A 5-step Boolean chain f (x1, x2, x3) Example 2.4 Let n = 3, then the 5-step Boolean chain x4 = x1 ∧ x2 x5 = x1 ∧ x3 x6 = x2 ∧ x3 x7 = x4 ∨ x5 x8 = x6 ∨ x7 f = x8 is depicted in Fig. 2.2. While this definition is elegant, it is also overly restrictive as it allows steps to represent binary functions exclusively. Therefore, in the following, a custom definition is given, which is inspired by [74]. Definition 2.7 A logic network is a Boolean chain, where each of the r steps xi has an arity δi assigned, such that xi = φi(xj(i,1), . . . , xj(i,δi)) for n + 1 ≤ i ≤ n + r, and 1 ≤ j(i, d) i, with 1 ≤ d ≤ δi. Here, φi refers to an arbitrary δi-ary Boolean function, thus, relaxing the strict binary computation constraint in each step. In this work, steps are referred to as (logic) nodes with their set being denoted as and the set of primary inputs being denoted as I, with ∩ I = ∅. A connection xj(i,d) between some node xi and one of its predecessors xj , where xi = φi(xj(i,1), . . . , xj(i,δi)), is called a signal. The set of all signals is denoted as . The designated signals computing the functions fj are referred to as primary outputs, whose set is denoted as O, with ∩ O = ∅. Thereby, as aforementioned, a logic network can be interpreted as a directed acyclic graph N = (, I, , O). Furthermore, the notation x ∈ N is used to refer to some node x ∈ of N, and the notation |N| is used to refer to the number of all logic nodes r. Since this book considers symmetric functions for logic nodes exclusively for all purposes, without loss of generality, the notation (xj , xi) is used to refer to a signal xj(i,d), i.e., a connection from node xj to node xi toward the primary outputs.
- 27. 12 2 Preliminaries Various types of logic networks have been proposed in the literature. For instance, AND-Inverter Graphs (AIGs) [102] restrict the permitted node functions to conjunction and negation, while Majority-Inverter Graphs (MIGs) [4] are restricted to the majority function and negation. Furthermore, compound structures exist, e.g., XOR-AND(-Inverter) Graphs (XAGs) [77], which rely on exclu- sive disjunction, conjunction, and negation, as well as XOR-Majority(-Inverter) Graphs (XMGs) [72], which are constructed from exclusive disjunction, majority, and negation.1 Definition 2.8 Majority of three, or simply majority (MAJ), is a ternary Boolean function denoted as a, b, c := ab + ac + bc, i.e., as the name suggests, the function evaluates to the majority value of its three variables. Its truth table is 0xe8. Consequentially, a, b, 0 = ab and a, b, 1 = a + b. The Boolean chain defined in Example 2.4 and depicted in Fig. 2.2 represents the majority function. Definition 2.9 The exclusive disjunction (XOR) is a binary Boolean function denoted as a ⊕ b := (a + b) · (¬a + ¬b). Its truth table is 0x6. AIGs, MIGs, XAGs, and XMGs all possess a property called universality, that is, these data structures are capable of representing every Boolean function by composing their elementary operators. The task of determining a logic network that implements some given specification is called logic synthesis (cf. [42] for an overview). As mentioned initially, in practice, logic networks are used as representa- tives for combinational circuits that are to be fabricated for some technology, e.g., using metal-oxide-semiconductor field-effect transistor (MOSFET) elements, which are the dominating building blocks for integrated circuits today [95]. A corresponding large-scale fabrication process is complementary metal-oxide- semiconductor (CMOS) technology [198]. Since logic networks are non-canonical, various implementations for a given specification exist. Considering that nodes can perform the identity function, it becomes apparent that an infinite number of different logic networks exist that all compute the same Boolean function. In case a specialized network is considered that does not permit identity nodes, the same argumentation holds for pairs of successive inverters or similar structures that collapse to the identity. Based on this deliberation and the widely accepted assumption that the task of obtaining optimum logic networks is NP-complete [93], logic synthesis algorithms usually yield approximate solutions with respect to some aforementioned cost 1 Usually, these data structures are restricted to their respective binary functions without explicit negation nodes but with the option to negate signals via a polarization flag. Thereby, simplifying implementation and saving memory as each node can be of fixed fan-in and the polarization flag can be encoded in the memory address. A designated constant x0 = 0 ensures universality.
- 28. 2.2 Satisfiability Solvers 13 metrics. These are, for instance, their number of nodes, their number of inverters, or their depth. Logic synthesis and in particular logic networks play a major role in this book. Logic networks are used as the main representational form of Boolean functions throughout this work. 2.2 Satisfiability Solvers Many practically relevant problems in numerous domains are NP-hard. Intuitively speaking, this means that no efficient algorithm exists that could solve all instances of such problems on a conventional computer system unless P = NP. Examples for NP-hard problems include model checking, planning, and formal verification [44]. Nevertheless, exact solutions to certain instances of these problems are of major interest, because the alternative is to rely on approximations of mediocre quality in the best case. In the worst case, no approximations to the problem in question are known. In the recent decades, the usage of satisfiability solvers emerged to tackle formerly intractable problems. These are highly optimized implementations of theorem-proving algorithms addressing, for instance, the satisfiability problem in propositional logic, first-order logic, and many other variations (cf. [19] for an overview). Figure 2.3 visualizes the concept of utilizing such engines for the obtainment of problem solutions. The process contains the following three steps: (1) a problem instance is encoded as an instance of a satisfiability problem in such a way that they are equisatisfiable, i.e., there exists a solution to the original problem instance iff there exists a solution to the satisfiability problem instance, (2) the newly created instance is passed to a specialized solver that returns an assignment to each variable in the encoding if such a solution exists or UNSAT, otherwise, (3) a solution to the original problem is extracted from the assignment. However, the most sophisticated algorithms cannot break complexity barriers on conventional computers unless P = NP. Nevertheless, the optimization techniques built into satisfiability solvers enable a drastically improved average case performance. Thereby, modern solvers are able to handle instances with hundreds of thousands of variables and millions of constraints without enumerating entire search spaces [137]. Section 2.2.1 goes over Boolean satisfiability, i.e., the satisfiability problem of propositional logic, while Sect. 2.2.2 discusses satisfiability modulo theories, i.e., satisfiability of first-order logic. Respective solving engines are used in three chapters of this work and require the previous knowledge.
- 29. 14 2 Preliminaries Fig. 2.3 Application of satisfiability solvers 2.2.1 Boolean Satisfiability (SAT) The preceding section introduced propositional logic in the form of Boolean algebra. Some data structures for the representation of Boolean functions have been discussed alongside. The Boolean satisfiability problem (SAT) reasons about Boolean functions being non-antilogies. Definition 2.10 Given a Boolean function : Bn → B, called instance, in some logic representation. SAT returns true iff an assignment to exists such that the function evaluates to 1, i.e., ∃α = (x1, . . . , xn) ∈ Bn : (α) = 1. Depending on the given representation of , the computational complexity of determining SAT varies. Stephen A. Cook showed that SAT is NP-complete in the general case in 1971 [35]. SAT remains NP-complete when passing as CNF but is in P when passing as DNF. Example 2.5 Let D = (¬a · b · ¬c) + (¬a · b · c) + (a · ¬b · c) + (a · b · c) in DNF. A satisfying assignment to D can be determined by satisfying any of its clauses, e.g., the first one by setting a → 0, b → 1, and c → 0. In fact, there is exactly one satisfying assignment per clause. Let C = (¬a + ¬b + c) · (a + b + c) · (a + b + ¬c) · (¬a + b + c) in CNF. It becomes apparent that applying the same approach to C leads to a conflict. Assigning a → 0, b → 0, and c → 1 satisfies the first clause but unsatisfies the third one. Since each clause of a CNF must be satisfied in order to satisfy the overall formula, the assignment is not valid. In the worst case, all possible 2n assignments must be investigated to find a fulfilling solution. As mentioned above, algorithmic procedures and tools tackling the SAT problem are in development since the 1960s [40, 41]. However, SAT solving is still an
- 30. 2.2 Satisfiability Solvers 15 active research field with numerous efficient tools developed as late as in the 2000s, e.g., [8, 17, 52, 199]. The reason for their practical effectiveness despite the NP-completeness of SAT is a combination of various incorporated techniques. Among these are heuristic decision procedures [69] to analyze in which order to assign values to variables, more efficient Boolean constraint propagation [130] that implies the consequences of unit clauses to detect conflicts early, conflict clauses [125] that are gradually learned by the solver while processing the instance and assist in restricting the search space, and non-chronological backtracking [125] that allows efficiently reverting unsatisfying assignments and, thereby, cut large parts off the search space. 2.2.2 Satisfiability Modulo Theories (SMT) While the preceding section introduced the satisfiability problem of propositional logic, this section covers the respective problem of first-order logic. In the following, first-order logic is briefly introduced first before discussing its satisfiability problem and respective solvers. The language of first-order logic is defined syntactically using symbols, terms, and expressions. This section covers the most relevant parts necessary for this work. The definitions in this section are based on [50]. Definition 2.11 The following elements are valid symbols in first-order logic: ∀, ∃, ∧, ∨, ¬, ≡, ⇒, ⇐⇒, :, (, ). Additionally, sets of variable symbols V, con- stant symbols C, function symbols F, and relation symbols R can be defined as well. Definition 2.12 Each variable symbol and constant symbol is a term. If f is an n-ary function symbol and if t1, . . . , tn are terms, then f (t1, . . . , tn) is a term. Definition 2.13 If t1 and t2 are terms, then t1 ≡ t2 is an expression. If R is an n-ary relation symbol and if t is a term, then Rt is an expression. If ϕ is an expression, then ¬ϕ is an expression as well. If ϕ and ψ are expressions, then also (ϕ ∧ ψ), (ϕ ∨ ψ), (ϕ ⇒ ψ), and (ϕ ⇐⇒ ψ) are expressions. If ϕ is an expression and if x is a variable symbol, then ∀x : ϕ and ∃x : ϕ are expressions. Example 2.6 Let x ∈ V be a variable symbol and ≤ ∈ R a binary relation symbol. ∀x : ≤ (x, x) is a valid expression. If, furthermore, x, y ∈ V are variable symbols, then ∀x : ∀y : ∀z : ((≤ (x, y) ∧ ≤ (y, z)) ⇒ ≤ (y, z)) is a valid expression. Thus far, this syntax is not associated with any semantics. In the following, a structure is defined to interpret first-order logic via a signature.
- 31. 16 2 Preliminaries Definition 2.14 A signature S := (S, σ) consists of the set of symbols S := V ∪ C ∪ F ∪ R and the function σ : S → N, which assigns an arity to each symbol in S. This is defined as ∀v ∈ V : σ(v) = 0, ∀c ∈ C : σ(c) = 0, ∀f ∈ F : σ(f ) ∈ N, and ∀R ∈ R : σ(R) ∈ N. Definition 2.15 A structure A over a signature S is a non-empty set A with one element vA ∈ A for each variable symbol v ∈ V, one element cA ∈ A for each constant symbol c ∈ S, one function f A : An → A for each function symbol f ∈ S with σ(f ) = n, and one relation RA ⊆ An for each relation symbol R ∈ S with σ(R) = n. Thereby, a structure assigns real variables, constants, functions, and relations to their respective symbols. It becomes, thus, possible to interpret expressions formulated in first-order logic and reason about their satisfiability. Definition 2.16 An interpretation of an expression is defined as I := (A, β) consisting of a structure A over a signature S and a function β : {vi | i ∈ N} → A. While expressions define syntactically valid elements of the language, signatures provide mathematical objects that are described by the expressions. Structures map said objects to the expressions. An interpretation assigns values of set A to variables via the function β. Commonly, with an abuse of notation, the assignment of an interpretation is also denoted I. If v is a variable, so is I(v) = β(v). If c is a constant symbol, so is I(c) = cA. If f is a function symbol with σ(f ) = n and if t1, . . . , tn are terms, then I(f t1, . . . , tn) = f A (I(t1), . . . , I(tn)) holds. Example 2.7 Let β(vi) = i ∈ Z, and let I = (Z ∪ {+, −, ≤}, β) be an interpretation. The term t = (+v4 − v2) is interpreted as follows: I(t) = I(+v4 − v2) = +A (I(v4), −A (I(v2)) = 4 + (−2) = 2. If an assignment changes at position x and if x is mapped to a ∈ A, then β a x denotes the changed assignment I a x := (A, β a x ). To assign a logical value to an expression, it is necessary to interpret logical symbols as well. To this end, the notion of a model is introduced. Definition 2.17 An interpretation I = (A, β) over a signature S is a model for an expression ϕ, denoted I | ϕ, iff
- 32. 2.2 Satisfiability Solvers 17 I | t1 ≡ t2 ⇐⇒ I(t1) = I(t2) I | f t1, . . . , tn ⇐⇒ f A (I(t1), . . . , I(tn)) I | Rt1, . . . , tn ⇐⇒ RA (I(t1), . . . , I(tn)) I | ¬ϕ ⇐⇒ not I | ϕ I | (ϕ ∧ ψ) ⇐⇒ I | ϕ and I | ψ I | (ϕ ∨ ψ) ⇐⇒ I | ϕ or I | ψ I | (ϕ ⇒ ψ) ⇐⇒ if I | ϕ, then also I | ψ I | (ϕ ⇐⇒ ψ) ⇐⇒ I | ϕ if and only if I | ψ I | ∀x : ϕ ⇐⇒ I a x | ϕ for all a ∈ A I | ∃x : ϕ ⇐⇒ there exists some a ∈ A with I a x | ϕ. For some set of expressions , the notation I | means that ∀ϕ ∈ : I | ϕ holds. The satisfiability problem of first-order logic, also called satisfiability modulo theories (SMT), asks whether a given set of expressions is satisfiable under given theories [10]. Definition 2.18 Let be a set of expressions formulated in the language of first- order logic. The set is called an instance. SMT returns true iff ∃I : I | . Given theories restrict the structure A ∈ I. For instance, the theory of quantifier- free linear integer arithmetic (QF_LIA) allows integer variable values and linear arithmetic functions +, −, . . . as well as the relation ≤. The theory of equality and uninterpreted functions (EUF) allows arbitrary linear and nonlinear functions and the theory of quantifier-free bit vectors (QF_BV) allows variable interpretation in the form of vectors of Boolean values together with respective functions for addition, subtraction, etc. Since the full expressive power of first-order logic is not necessarily respected, the complexity of the associated satisfiability problem varies based on the theories used. For instance, EUF is decidable in polynomial time, while QF_LIA and QF_BV are both NP-complete. Any theory allowing quantifiers is undecidable in the general case [10]. For the ease of readability, common notation conventions for elements of the language of first-order logic are applied in this work. These include the usage of infix notation, the usage of the equal sign instead of the equivalence operator, and the separation of quantified variables with commas. Example 2.8 Let = {ϕ1, ϕ2, ϕ3, ϕ4}, where
- 33. 18 2 Preliminaries ϕ1 = (2 · x + y = z), ϕ2 = (z ≤ x + y), ϕ3 = (x + 8 ≤ z), ϕ4 = (z + 3 ≤ y). Let I = (A, β) be an interpretation such that I | under the theory of linear integer arithmetic. The selection of theory defines A A := Z ∪ {+, ·, ≤, =}. If β is selected such that β(x) = (−2), β(y) = 10, and β(z) = 6, then I | holds. Similar to the satisfiability problem of propositional logic, highly optimized solving procedures also exist for the satisfiability problem of first-order logic that are able to determine models for instances. Since SMT is undecidable in the general case, these engines can and will eventually fail on increasingly complex theories and increasingly large instances. Internally, SMT solvers utilize SAT solvers in combination with special theory solvers per utilized theory. The SAT solver interprets a passed SMT instance as a kind of Boolean expression and tries to assign logical values to sub-expressions such that the instance evaluates to 1. Since each Boolean sub-expression represents a(n) (sub-)expression in first-order logic, the proposed assignments are passed to a special theory solver to be checked for consistency. If a conflict emerges, it is fed back to the SAT solver, which adds it to the instance in the form of a conflict clause and proposes a new assignment. Example 2.9 Let = {ϕ1, ϕ2, ϕ3, ϕ4} be an SMT instance, where ϕ1 = (4 ≤ x ϕ 1 ∨ y + 2 ≤ 8 ϕ 1 ), ϕ2 = (x + y ≤ 11 ϕ 2 ∨ x ≤ y ϕ 2 ), ϕ3 = (10 ≤ y ϕ 3 ∨ 5 ≤ x − y ϕ 3 ), ϕ4 = (2 · x = y ϕ 4 ∨ x = y ϕ 4 ). An SMT solver interprets as ϕ1 ∧ ϕ2 ∧ ϕ3 ∧ ϕ4 = (ϕ 1 ∨ ϕ 1 ) ∧ (ϕ 2 ∨ ϕ 2 ) ∧ (ϕ 3 ∨ ϕ 3 ) ∧ (ϕ 4 ∨ ϕ 4 ), which structurally resembles a CNF. This expression is passed to an internal SAT solver that could propose the assignment ϕ 1 → 1, ϕ 2 → 1, ϕ 3 → 1, ϕ 4 → 1. The SAT solver interprets the sub-expressions as Boolean variables without any SMT interpretation context. Since the expression ϕ 1 ∧ ϕ 2 ∧ ϕ 3 ∧ ϕ 4 requires the theory of linear integer arithmetic, the SMT solver passes it to a specialized solver for this very theory that interprets the expression and detects a contradiction. Next, the SAT solver is notified that this variable assignment is unsatisfiable, whereupon it adds ϕ5 := (¬ϕ 1∨¬ϕ 2∨¬ϕ 3 ∨¬ϕ 4 ) as a conflict clause to the instance
- 34. 2.3 Field-coupled Nanocomputing (FCN) 19 to exclude this assignment in the future. The subsequent proposed assignment could be ϕ 1 → 1, ϕ 2 → 1, ϕ 3 → 1, ϕ 4 → 1, which is investigated for consistency by the theory solver once more. As a consequence, the expression is found to be satisfiable conflict-free for the interpretation I = (A, β), with β(x) = (−5) and β(y) = (−10). Thus, I | holds. This procedure is commonly referred to as lazy SMT solving [10, 158] and is utilized in most solvers to date. In contrast, eager SMT solving breaks theories down to SAT as much as possible, which is also called bit-blasting [10]. 2.3 Field-coupled Nanocomputing (FCN) Field-coupled nanocomputing (FCN) is a class of post-CMOS emerging nanotech- nologies that establish a novel paradigm for realizing integrated circuits with enhancements in terms of energy dissipation and feature size [6]. FCN acts as an umbrella term for various implementations that all share similar properties. Since its conceptualization in 1993, the concept of Quantum-dot Cellular Automata (QCA) [113, 115, 116] is arguably the most extensively researched FCN approach. QCA utilize nanoscale devices called cells, which are arranged in specific topological structures to realize circuitry. QCA systems transmit and compute information without the flow of electric current. Instead, they utilize the repulsion of local fields. Several physical implementations have been proposed to realize QCA, e.g., semiconductors [143, 166–168, 178], nanomagnets [13, 37, 138], and molecules [21, 30, 108, 109], which all possess specific assets and drawbacks. While semiconductor QCA systems were successfully fabricated using lithogra- phy processes [122, 165–167], they are highly sensitive to external disturbances, thus, requiring cryogenic operation [111]. However, they have been proposed as a contestant for enabling interoperability of quantum computers [134] and conventional CMOS technology [49]. Magnetic QCA, nowadays called Nanomagnet Logic (NML) [145], incorporate single-domain magnets to realize non-volatile devices operating at room temper- ature [13, 37, 138]. However, NML elements require more area overhead than other FCN technologies and are limited to clock frequencies of only several hundred megahertz [136]. Molecular QCA is another promising room temperature candidate but provides significantly smaller feature sizes that might allow for nanometer devices [20, 90, 147]. Additionally, clock frequencies for this implementation are expected to be possible in the terahertz range [176]. Unfortunately, fabrication of molecular QCA is in its infancy with no standardized processes having yet been determined [92, 147]. Even though all contestants allow operations with a remarkably low energy dissipation that is a number of magnitudes below current MOSFET technologies [160, 163, 176] and possess logic-in-memory capabilities [96, 117, 140, 173] in
- 35. 20 2 Preliminaries addition to their technology-specific properties, large-scale device fabrication is yet to establish. However, recent developments in hydrogen lithography enable the creation of dangling bonds (DBs) on silicon surfaces [1, 2, 84, 141], thereby providing a highly promising DB-QCA implementation that can potentially be integrated with MOSFETs and, thus, exploit existing fabrication processes [75, 83, 201]. FCN technologies are the core subject of this book. Even though this work focuses on algorithmic considerations, the concepts and functionalities of FCN are introduced in the following sections in an effort to keep this work self-contained. Further elaborations on the physics involved can be found in the respectively cited primary literature. Throughout this work, QCA are used as representatives for all FCN technologies under consideration because they are the most common. Without loss of generality, this running example shall not favor any specific technological implementation. In Sect. 2.3.1, the properties of single FCN cells are reviewed, while Sect. 2.3.2 discusses their arrangement in patterned arrays to realize logic gates. Subsequently, Sect. 2.3.3 goes over the necessity of clocking, which allows the conceptualization of larger-scale circuit layouts as elaborated in Sect. 2.3.4. 2.3.1 Cells As [111] points out, QCA are inspired by and named after the mathematical model of cellular automata [177] for discrete computation, where the state of each cell at some time point is determined by the state of its neighbors at the preceding time point, according to a set of rules. Arguably, the most prominent example of cellular automata is Conway’s Game of Life proposed by John H. Conway in 1970 and popularized by [62]. The principles of QCA can be abstracted via description of such mathematical models as it is discussed in the following. The basic element of QCA technologies is the cell, which is a device suitable for positional bit encoding and computation. To this end, four (or six) quantum dots, which are entities able to confine electric charges, are grouped together in a quadratically shaped frame sitting on a substrate, hence, composing a QCA cell [114]. With the quantum dots arranged in the corners (and the center) of the square, and two charges inserted into the system, Coulomb interaction leads to the emergence of exactly two stable polarization states and one unexcited state [197]. If the system is excited, the mutual charge repulsion leads to the occupation of antipodal quantum dots via tunneling, i.e., the charges stabilize on either the diagonal or antidiagonal. Example 2.10 Figure 2.4a depicts three QCA cells with the respective aforemen- tioned charge distributions leading to the polarizations commonly denoted as (from left to right) P = −1 and P = +1 [116] as well as the unexcited state P = 0 [109].
- 36. 2.3 Field-coupled Nanocomputing (FCN) 21 Fig. 2.4 Elementary QCA cell devices. (a) Polarization states. (b) Wire segment In this figure, quantum dots are visualized as circles and occupying charges as black bullets. The bistable polarizations of QCA cells represent Boolean 0 and 1 states, respectively [114], while the unexcited state represents null with no retrievable information to it.2 Several cells that are arranged in close proximity influence each other’s polariza- tions and, thus, create a tendency to propagate information. This observation leads to the consequential construction of wire segments. Example 2.11 A QCA wire segment is depicted in Fig. 2.4b [112]. Assuming an initial and fixed polarization of the leftmost cell, its impact disturbs the metastability of adjacent cells and forces them to align their polarizations accordingly, thus, propagating the signal through the wire, and, eventually, to the rightmost cell. NML implementation behaves in accordance with the model discussed here. Instead of quantum dots, its cells consist of single-domain nanomagnets and, hence, assume magnetizations instead of polarizations [13]. Additionally, wires of nanomagnets invert their transmitted signal in each step [38]. However, this poses no limitation on their applicability since an odd number of cells can be assumed to compensate for this effect. 2.3.2 Gates More complex topological structures than those of QCA cell wire segments can be envisioned. In [180], first implementations of logic functions were proposed by arranging QCA cells in specific ways, which are called gates. Example 2.12 The structure shown in Fig. 2.5a is called an inverter or a NOT gate and performs the negation of the signal a applied to the leftmost cell. The inverted signal is exhibited on the right as ¬a. Applied information is first passed one cell to the right and then copied to two paths where it is further propagated to the right. Finally, the inversion happens via the diagonals, of which two symmetric ones are 2 To reiterate, the depiction as four-dot QCA cells is, without loss of generality, used as a running example visualization and shall not favor any specific technological implementation.
- 37. 22 2 Preliminaries Fig. 2.5 QCA gates implementing Boolean functions. (a) Negation. (b) Majority Fig. 2.6 Constant cells enabling AND and OR gates. (a) Conjunction. (b) Disjunction required for equally reliable output readings for both possible input signals [180]. However, inverters with a single diagonal interaction have been proposed as well [116]. The QCA arrangement in Fig. 2.5b implements the majority function (cf. Sect. 2.1.3) of the top a, left b, and bottom c cell and is, hence, called a MAJ gate. The three input cell polarizations compete for the center cell, where the highest combined force wins [180]. The result is then propagated to the right. In this case, a = 0, b = 1, c = 1 = 1. As discussed in Sect. 2.1.3, the combination of majority and negation functions leads to the emergence of Boolean universality. To this end, constant signal cells that possess only one logic state have been proposed [180]. These can be implemented using cells with merely two quantum dots, hence, enabling the apparent creation of structures realizing Boolean conjunction and disjunction, which are called AND gates and OR gates, respectively. Example 2.13 An AND gate and an OR gate are depicted in Fig. 2.6. The constant cells are located at the top and are depicted in black with the remaining two quantum dots visualized as white bullets. When excited, these dots are always occupied by charges, thus, leading to a fixed polarization. Thereby, the gate in Fig. 2.6a computes a = 1, b = 1, 0 = ab = 1, while the gate in Fig. 2.6b computes a = 1, b = 0, 1 = a + b = 1. In contrast to logic networks, which are merely mathematical models, QCA cells, and thus gates, are physical entities. That is, they have definite locations onto which
- 38. 2.3 Field-coupled Nanocomputing (FCN) 23 Fig. 2.7 Further QCA wire entities. (a) Bent wire. (b) Fan-out they are placed. Consequently, signal distribution is a critical factor, because it requires the placement of wire routes, which themselves take up space. Therefore, further wire structures have been developed that allow both signal transportation around corners and signal duplication [116, 202]. Example 2.14 These structures are depicted in Fig. 2.7. The bent wire segment shown in Fig. 2.7a is able to transport a value to a perpendicular route, while the fan-out visualized in Fig. 2.7b copies the applied signal onto two data paths: one following its original trajectory and another one perpendicular to it. Every depicted QCA structure can be fabricated in four different orientations: (1) exactly as shown, (2) rotated by 90°, (3) rotated by 180°, and (4) rotated by 270°, hence allowing flexibility in device composition. However, QCA is considered a planar technology, where cell placement is possible in two dimensions exclusively. QCA’s planarity imposes harsh restrictions on the feasibility of a certain functionality. To overcome this obstacle, signal distribution networks have been proposed, which are logical structures built from gates and are able to shift input vectors to outputs at different relative locations [179]. However, such networks require large amounts of cells and, thereby, cause a tremendous area overhead that scales with the number of inputs distributed. A more elegant solution is the utilization of cells with quantum dot arrangements rotated by 45°, which enable coplanar wire crossings [180]. Since normally oriented cells do not interfere with rotated ones, and vice versa, wires of these two cell types can cross through each other without signal disturbance on either path [180]. A coplanar wire crossing is depicted in Fig. 2.8a.3 The noninterference of normal and rotated cells causes a drawback of this implementation as well: extra cells and area are required for an arrangement that converts a non-rotated signal into a rotated one that can eventually cross through a regular wire. Furthermore, the passing rotated wire separates the cells of the regular wire, which weakens its signal and makes it more prone to disturbance [195]. Finally, coplanar cells are 3 In [180], inverting wires are proposed that utilize an even number of rotated cells. A similar mechanism can be found in NML wires [38] as elaborated in the preceding section. In DB-QCA, an inverting wire could be demonstrated with regular half cells, i.e., without the need for rotated cells or large inverter structures [132].
- 39. 24 2 Preliminaries Fig. 2.8 Wire crossings. (a) Coplanar. (b) Second layer more sensitive to cell displacement fabrication defects than normal cells are [156] and, thus, necessitate high precision of corresponding manufacturing processes. A different approach aims at the reduction of corresponding convolution by the introduction of multiple layers for cell placement [67]. An according second-layer crossing is depicted from a two-point perspective in Fig. 2.8b. For visual guidance, the cells of the ground-layer wire segment have been tinted gray. As it can be seen, this crossing does not require rotated cells but involves the addition of inter-layer via cells for signal transport into the second layer and back to ground layer. Physically, these cells are not distinguished from regular cells besides their positioning but are differentiated in the figure as squares with a large circle inside. The crossing cells, which are also regular cells, are highlighted by a cross symbol. Second-layer cells require fabrication overhead and, depending on cell dimensions, multiple stacked via cells to increase distance from the ground layer to prevent any crosstalk [156]. It is believed that the multi-layer approach is more likely to yield stable wire crossing signals than the coplanar implementation [195]. Consequently, without loss of generality, the remainder of this work utilizes second-layer crossings for visualizations. In either case, additional expenditure has to be provided if crossings are to be realized. Therefore, several works suggest reducing wire crossings in an attempt to lower fabrication costs, e.g., [33, 131]. The QCA gates and wire structures discussed in this section have been proposed in a similar form for other FCN technologies as well. For instance, [39, 87, 185, 186] provide implementations of NML gates, while magnetic wire crossings are intro- duced in [136, 146]. As difference to QCA implementations, nanomagnets with non-rectangular geometries, the so-called slanted-edge magnets, can be employed that allow the construction of logic gates with reduced cell count due to their preference for a certain magnetization [135]. However, as a mere fabrication characteristic, this circumstance does not alter the applicability of logic-level considerations. Finally, corresponding DB-QCA implementations of logic gates can be found in [83, 132].
- 40. 2.3 Field-coupled Nanocomputing (FCN) 25 2.3.3 Clocking A QCA wire with an applied input signal cell polarization on either side has exactly one ground state, namely the according polarization of all other wire cells [115], e.g., as shown in Fig. 2.4b. Other states are theoretically possible as well, but they, consequentially, have higher energy levels due to unavoidable opposite polarizations of at least two adjacent cells. The energy difference between the ground state and the first excited state is called kink energy [115, 116]. Even though the kink energy does not decrease with an increasing amount of cells in the wire, the excited states become increasingly degenerate, i.e., they are more likely to occur in any system at nonzero temperature [115]. Such kink states express incorrect computation and are not limited to wires but can arise in any QCA system. Naturally, this phenomenon limits the amount of cells possible to realize and the operational temperature of any system fabricated from QCA. To overcome this restriction, first proposals included the interlacing of QCA with conventional circuitry that should have acted as latches to buffer computation results obtained from QCA before feeding them to subsequent QCA stages [115]. However, it was found that the obstacle could be circumvented without the inte- gration of MOSFET components by separating QCA systems into small decoupled regions that could only interact on activation of external signals [80]. First attempts proposed to raise and lower the inter-dot quantum tunneling barriers to transition cells in a region between the null ground state and the polarized excited states, thus, coupling and decoupling them from the other parts of the system [113]. Modern approaches rely on increasing and decreasing the energy level of the null state, which makes it less or more likely to occur, rather than influencing inter-dot tunneling as it is easier to realize; however, the effect is identical [80, 111, 120]. The discussed principle is referred to as clocking, with the external coupling signal being the clock [80, 113]. Even though the term is utilized in CMOS technology as well, its functionality and its purpose differ in the FCN domain. Both combinational and sequential QCA systems need to be clocked to ensure signal stability and data flow directions. A clock signal is usually created by an external clock generator and distributed to the cells through the device substrate using embedded electrodes [80]. These create electric fields (or magnetic ones in case of NML [39]) that gradually excite and de-excite the cells in the respectively controlled region.4 This gradual change can be realized via trapezoidal field intensity modulation that can be split into four clock phases of length π 2 , which are called switch, hold, release, and relax, forming a single 2π clock cycle [80]. Cells in the hold phase are excited and are fixed in either polarization state, while cells in the relax phase are in the unexcited ground state null. The switch and release phases are gradual changes between the two other ones. To properly transmit information from one 4 For molecular implementations, [120] provides valuable graphs that vividly illustrate the field forces, charge distributions, and energy levels of the respective cell states involved.
- 41. 26 2 Preliminaries Fig. 2.9 QCA wire segment partitioned into clock zones Fig. 2.10 QCA clock curves and data propagation cell region to another, four of these trapezoidal clock signals can be utilized, each with a π 2 offset to their respective preceding one and numbered 1 to 4. Commonly, NML omits the relax phase and, thereby, only possesses three clock numbers [145]. Cells are grouped together in clock zones controlled by either of the available clock signals. This way, information can be transmitted from cells controlled by clock 1 to cells controlled by clock 2, from there to clock 3, to clock 4, and, finally, back to clock 1 again. Consequently, a pipeline-like behavior of data propagation emerges. A QCA wire segment partitioned into clock zones is depicted in Fig. 2.9. The cell color, the clock zone shade, and the number in the bottom right corner give redundant indication of the clock controlling the respective zone. Within one full clock cycle, applied information can be propagated through four clock zones, e.g., from the leftmost one indicated by 1 to clock zone 4. Example 2.15 The stacked diagrams in Fig. 2.10 visualize the clock phases and resulting data propagation in a partitioned wire. The time is plotted on the shared x- axis, while each of the four stacked diagrams possesses its own y-axis displaying clocking field strength. Each of the four clock curves corresponds to the clock zone on their left. The QCA cells drawn alongside the curves reflect the gradual
- 42. 2.3 Field-coupled Nanocomputing (FCN) 27 polarization changes of the cells in the respectively controlled clock zone. The dashed lines separate the x-axis into clock phases. To reiterate, four clock phases are equal to one clock cycle. Clock zone 1 starts with a raising clock field, which is the switch phase. The polarization gradually emerges and stabilizes at the peak, where it is kept in the subsequent hold phase. At this time point, the adjacent clock zone 2 is in the switch phase. Its cells are being influenced by the ones from clock zone 1, which are kept stable. Consequently, the cell polarizations in clock zone 2 align accordingly. For clock zone 1, the falling slope starts in the third phase, which is the release phase. Since its information was successfully transmitted to clock zone 2, it is not needed any longer and the cells can start to de-excite. The final phase before repetition is the relax phase, in which the cells remain in the null state. The discussed clocking mechanism is known as Landauer clocking.5 According to Landauer’s principle, every irreversible computation dissipates energy of at least W = kB ln 2 per bit erased as heat, where kB is the Boltzmann constant and T is the surrounding temperature [104]. This principle does not apply to signal transmissions in QCA wires because no information is being erased [105, 110]. However, any of the gates discussed in the preceding section inevitably dissipates energy in accordance with Landauer’s principle, when operated using Landauer clocking [12, 110]. Energy dissipation is one of the key limiting factors of conventional CMOS scaling, often resulting in Dark Silicon, that is, the obstruction of circuitry to utilize the entirety of integrated logic simultaneously to prevent burning out [54, 175]. Thereby, MOSFET chips fall way behind their theoretically ideal computational capabilities due to thermal restraints. Since FCN technologies theoretically allow for substantially higher device densities, the heat dissipation problem intensifies even though QCA technologies inherently consume considerably less energy than MOSFETs [107, 160]. An estimation given in [110] illustrates the situation’s significance: the authors assume an average footprint per molecular QCA cell of 1 nm × 1 nm and a clock frequency of 100 GHz. They elaborate that this would lead to a density of 1014 cells per cm2. Additionally, the authors continue, if each cell were to dissipate merely 0.1 eV per clock period, the system’s power density would be 160 kW per cm2, which is magnitudes higher than that of a nuclear fission reactor’s core and would, consequently, virtually immediately vaporize the system [110]. However, it was shown that utilizing the same four external clock signals to implement a quasi-adiabatic clocking mechanism, which is referred to as Bennet clocking, an arbitrarily small amount of energy dissipation can be accomplished, also for irreversible computations, thus, resolving concerns regarding thermal den- sity [97, 110, 120, 178]. This capability of sub-Landauer computation is achieved by altering the clock waves in such a way that signals are kept stable until some desired 5 To the best of the authors’ knowledge, the term was coined in [110].
- 43. 28 2 Preliminaries computation has been performed and are subsequently erased in reverse order of computation [110]. The effective clock rate of a Bennet-clocked system is at least halved due to the necessary forward and backward signal propagation. Furthermore, its pipelining capabilities are reduced as only one signal vector can be transmitted through the system at any time. Since the device architecture itself requires no adjustments for this change, a Landauer-clocked system could, theoretically, be switched over to a Bennet-clocked one at any time [110]. The advent of clocking allowed envisioning arbitrarily large QCA systems, e.g., arithmetic circuits [144], processors [55], and FPGAs [98]. However, no universal consent for the minimum and maximum clock zone size to use could be established. Values ranged from single cells up to several hundred ones controlled by the same clock signal. Since the state-of-the-art physical simulator QCADesigner [196] supports arbitrary clock zone geometries, little discourse was held about the technical feasibility. Nevertheless, to reiterate, clock fields are generated by electrodes that are buried in the substrate and must be fabricated as well. To support said arbitrary clock zone geometries, it must be feasible to fabricate electrodes of the size of single QCA cells, hence, this scheme was named cell-based design. Due to the nanometer cell dimensions of molecular QCA and DB-QCA, this paradigm is unlikely to be realistic [20]. To the best of the authors’ knowledge, the works [14] and [82] were the first to propose a different approach that is now referred to as tile-based design: instead of assigning clock zones arbitrarily, these works suggest relying on regularly arranged square clock tiles, which could host 5 × 5 and 3 × 3 QCA cells, respectively, and constructing all gates and wires within these regions. Simulations, which were taking entanglement of individual quantum-dot cells into account, suggest that it might be unrealistic for clocked tiles larger than 5×5 cells to propagate information correctly [174]. Physical clock networks were proposed later in [20]. Recently, [31] and [149] also confirmed via physical simulations that cell-based clocking should certainly no longer be pursued. Example 2.16 Figure 2.11a depicts a QCA structure with cell-based clock assign- ment indicated by the colors. As can be seen, this approach can lead to various clock zone geometries of arbitrary size, which are unlikely to be fabricable [20, 31, 149]. In contrast, Fig. 2.11b depicts a single tile-based clock zone of size 5 × 5 cells. Possible cell positions within the tile are indicated in gray. The QCA wires in Figs. 2.9 and 2.10 utilize the same tile-based design paradigm with tiles of size 5 × 5 cells. Various clock zone arrangements, commonly referred to as clock topologies or clocking schemes, for the tile-based design paradigm have been proposed in the literature. They act as floor plans for cell placement. Figure 2.12 depicts cutouts of size 4×4 tiles of three common clocking schemes usually, but not exclusively, used for QCA technologies. Clocking schemes can be extrapolated seamlessly in all directions, but each of them provides different assets and drawbacks. Each tile in these clocking schemes is uniformly sized and can hold up to a fixed amount of cells, e.g., 3 × 3 or 5 × 5.
- 44. 2.3 Field-coupled Nanocomputing (FCN) 29 Fig. 2.11 Cell-based vs. tile-based design paradigm. (a) Cell-based clock assignment resulting in clock zones of various geometries. (b) Possible cell locations indicated in a 5 × 5 tile-based clock zone Fig. 2.12 Clocking schemes for FCN technologies. (a) 2DDWave [184]. (b) USE [28]. (c) RES [70] Example 2.17 In Fig. 2.12a, the 2DDWave clocking scheme is sketched. It forms one of the simplest floor plans, where each antidiagonal is assigned the same clock number. This way, the incoming information flow to a tile is solely possible from the northern and western directions, while the outgoing information flow from a tile always has to utilize the eastern or southern directions. This inherently restricts the scheme in multiple ways, since, e.g., (1) sequential systems cannot be realized due to the lack of feedback loops and (2) neither MAJ gates nor 3-output fan-outs are possible due to the maximum input and output degree of 2 for each tile. The latter issue occurs in the USE clocking scheme sketched in Fig. 2.12b as well. While USE does allow feedback, its tiles’ maximum input and output degree is also limited to 2. The RES scheme sketched in Fig. 2.12c overcomes this restriction and allows for feedback, MAJ gates, and 3-output fan-outs in certain tiles. However, due to the increased degree in some tiles, the degree in other tiles must, naturally, be lower as this still is a two-dimensional grid structure. Therefore, FCN systems tend to become more widespread in the RES scheme and, consequently, have higher area costs and longer critical paths as confirmed by an experimental evaluation [70]. While predefined clocking schemes seem to impose a restriction on the freedom of cell placement, contrarily, allow to abstract from cell dynamics and to consider
- 45. 30 2 Preliminaries Fig. 2.13 The QCA ONE gate library [148]. (a) MAJ. (b) AND. (c) OR. (d) Inverter. (e) Straight wire. (f) Bent wire. (g) Fan-out. (h) Crossing the FCN concept on the logic level. To this end, several gate libraries have been proposed that provide carefully simulated implementations of elementary Boolean functions, e.g., [68, 132, 148]. These libraries have been designed in such a way that their basic gates are of uniform size and, thereby, fit on one tile each. In the remainder of this work, without loss of generality, the 5×5 QCA ONE gate library is used as a running example for visualizations [148]. Its elementary gates are depicted in Fig. 2.13. To this end, each gate is visualized on an arbitrarily clocked tile. As a matter of course, all gates can be used with any clock number. Some approaches, furthermore, allow the routing of multiple wire segments through the same tile as long as they bypass each other with a spacing of at least one cell [57]. This concept is sometimes referred to as multi-wire routing. More complex gates, e.g., XOR, can be assembled from these elementary building blocks as demonstrated in [148]. That is, given some Boolean function in terms of a logic network, an FCN system realizing that function can be obtained by mapping the logic network’s nodes onto a clocking scheme, connecting them with their signals accordingly, and applying an FCN gate library for technology mapping. 2.3.4 Circuit Layouts The task of assembling FCN cells by arrangement in the plane and, thereby, realizing certain functionality defined by a specification is called physical design, as known from conventional VLSI. Commonly, said specification is given in terms of a logic network. The resulting assembled FCN system is called an FCN circuit layout,
- 46. 2.3 Field-coupled Nanocomputing (FCN) 31 sometimes also shortened to FCN circuit or FCN layout. FCN circuit layouts can be considered on different abstraction levels. As discussed in the preceding section, they can be obtained by directly arranging logic networks in the plane, assigning clock numbers, and, in a final step, applying gate libraries for technology mapping. In this scenario, concrete cell positions are only determined in the step of technology mapping, while the placement of logic network nodes and routing of their signals are a more abstract logic-level consideration. A logic network mapped to a clocking scheme is referred to as a gate-level FCN circuit layout, while the layout obtained from technology mapping is called a cell-level FCN circuit layout.6 This work mainly considers the obtainment of tile-based gate-level FCN circuit layouts from specifications, since the subsequent technology mapping is a straight- forward process. Therefore, unless explicitly stated, otherwise, the term FCN circuit layout or its shortened variants refer to these tile-based gate-level implementations throughout this book. In the following, a naming scheme for FCN circuit layouts is briefly defined to standardize nomenclature for the remainder of this work. Afterward, challenges in the task of physical design are illustrated. FCN circuit layouts can be considered as (partial) grid graphs. Definition 2.19 A w × h grid graph is defined as Gw,h := (V, E), where V = {0, . . . , w − 1} × {0, . . . , h − 1} and E = {{(i, j), (i, j)} | |i − i| + |j − j| = 1, 0 ≤ i, i ≤ w, 0 ≤ j, j ≤ h}. Its vertices are, thereby, tuples of indices in the horizontal and vertical directions: (x, y) refers to the vertex at horizontal position x and vertical position y, where (0, 0) is the top left vertex. Definition 2.20 A gate-level FCN circuit layout L of size w × h is a (partial) grid graph Gw,h together with a logic network N = (, I, , O) and three mappings p, r, and c, which are called placement, routing, and clocking. The placement p assigns logic network nodes to layout tiles. The routing r assigns logic network signals to paths in the layout. Finally, the clocking c assigns clock numbers to layout tiles. Thereby, a gate-level FCN circuit layout is defined as L := (Gw,h, N, p, r, c). Vertices of layouts are called tiles with their set being denoted T . Edges connecting tiles define spatial adjacency, and thus, their set is denoted A. A tile with a logic network node assigned via p is called a gate. A tile, which is contained in a path to which a logic network signal is assigned via r, is called a wire segment. A tile that is neither a gate nor a wire segment is empty. If a layout contains empty tiles only, the layout is empty. Analogously to the definition of logic networks, the notation t ∈ L is used in this work to refer to a tile t = (x, y) ∈ T of layout L with the number of all tiles denoted by |L|. A layout inherits primary inputs and primary outputs from its logic network N. A clocking scheme S can be used as the mapping c of L. In this case, L is said to be S-clocked. Otherwise, L is irregularly clocked. Since the clocking restricts 6 Not to be confused with tile-based and cell-based designs, which are clocking paradigms as discussed in the previous section.
- 47. 32 2 Preliminaries data flow directions, it is possible that tiles, despite being adjacent, cannot exchange information. Two tiles t1 and t2 are adjacent if {t1, t2} ∈ A. The set of all outgoing tiles to which some tile t can pass information is denoted t+, while the set of all incoming tiles from which some tile t can accept information is denoted t−. It holds that ∀t, t ∈ L : t ∈ t+ ⇐⇒ {t, t} ∈ A∧(c(t)−c(t)) mod clk = 1. Analogously, ∀t, t ∈ L : t ∈ t− ⇐⇒ {t, t} ∈ A ∧ (c(t) − c(t)) mod clk = 1. To this end, clk is a constant defining the maximum clock number, e.g., clk = 4 in a QCA context and clk = 3 for NML.7 Correspondingly, the notations A+ and A− are used to refer to all outgoing and incoming adjacencies in a clocked layout, respectively. To the best of the authors’ knowledge, FCN circuit layouts have not been formally defined in the literature. Therefore, the detailed restrictions for the non- trivial p, r, and c are given in Sect. 3.1 as a contribution of this book. An illustration is given in the following example for intuition already. Example 2.18 The logic network depicted in Fig. 2.14a represents the 1-bit multi- plexer (2:1 MUX) function. It is a ternary Boolean function defined as f = as +bs. Thereby, it implements an if s then b else a. Its primary input s fans out to two consecutive nodes, namely, x4 and x6. To realize such a condition in FCN technologies, a fan-out wire as shown in Figs. 2.7b and 2.13g has to be utilized. Figure 2.14b displays a functionally equivalent logic network, where the primary input’s fan-out was substituted by a designated fan-out node labeled F. Figure 2.14c shows a mapping of said substituted logic network onto a 3 × 3 tiles clocked layout. Finally, technology mapping using the QCA ONE library yields the FCN circuit layout visualized in Fig. 2.14d. Primary input cells are colored blue, and the primary output cell is colored orange. While the process of technology mapping is rather trivial, the placement and routing of logic networks is not.8 Since the conceptualization of FCN, many circuit layouts have been generated manually from logical descriptions, e.g., as aforemen- tioned, [55, 98, 144]. In most cases, however, practically relevant circuits exceed human-graspable complexity, which excludes this practice from large-scale design of FCN layouts. Although there are some algorithmic solutions available, these approaches produce results of limited quality and do not scale [27, 34, 57, 181]. The planar nature of FCN technologies with only limited capabilities for wire crossings is a restricting factor in the physical design of circuit layouts that challenges placement and routing algorithms. However, it is not the only one. As thoroughly reviewed in the preceding section, the necessity for clocking in both combinational and sequential circuit layouts leads to the emergence of a striking property, namely the inherent need for signal synchronization. 7 From a technical perspective, it makes sense to enforce clk ≥ 3 because no directed information flow is possible otherwise. 8 Formal proofs for this conjecture are given in Sect. 3.2.
- 48. 2.3 Field-coupled Nanocomputing (FCN) 33 Fig. 2.14 Possible implementations of a 2:1 MUX. (a) Logic network. (b) Fan-out substitution. (c) Gate-level FCN layout. (d) Cell-level FCN layout Example 2.19 Figure 2.15 depicts a QCA circuit of size 4 × 3 tiles with three primary inputs x1, x2, and x3 as well as one primary output f . At first glance, it could be assumed that the circuit implements the MAJ function f = x1, x2, x3, because the gate assigned to the tile at position (3, 1) is a MAJ gate, while all the other tiles host wire segments, which feed the gate’s inputs. However, since the tile at position (3, 0) is controlled by clock 4 and its adjacent tile at position (3, 1) is controlled by clock 3 (marked with a red A), no signal propagation from the former to the latter is possible. Thus, the circuit layout does not comply with its specification because signals, which are applied to the primary input x1, are not properly forwarded to the MAJ gate.
- 49. 34 2 Preliminaries Fig. 2.15 Synchronization issues in FCN technologies The fact that data flow is only possible from tiles controlled by clock i to those controlled by clock (i + 1) mod clk for some maximum clock number clk is called the local synchronization constraint. However, the clocking mechanism does not only propel data flow but also assigns a notion of timing. Thereby, a second obstacle arises. Example 2.20 The local synchronization issue is not the only deficiency in the layout depicted in Fig. 2.15. Signals from primary input x2 at position (0, 2) pass five tiles to arrive at the convergence MAJ gate tile (3, 1), while signals from primary input x3 at tile position (3, 2) pass only a single tile (marked with a red B). This way, x2’s signal information arrives desynchronized with a delay of one full clock cycle. The fact that the number of passed tiles for any two signals along their paths from the primary inputs to a common gate has to be equal is called the global synchronization constraint. While the local synchronization constraint can be effectively tackled by relying on predefined clocking schemes, satisfying global synchronization can become increasingly difficult in larger layouts with numerous signals that fan out and reconverge. As it is shown in the following chapter, the process of physical design for FCN technologies is highly non-trivial. Furthermore, the existing literature in the field
- 50. 2.3 Field-coupled Nanocomputing (FCN) 35 does not provide sophisticated algorithms for automatic obtainment of FCN circuit layouts. Due to the peculiarity of FCN technology constraints, conventional VLSI methods are also not suited in this domain. However, the availability of solutions to the arising physical design problems is crucial for the applicability of all field- coupled nanotechnologies.
- 51. Chapter 3 Theoretical Groundwork Physical design bridges the gap between mostly pure logical specifications and physically fabricable circuitry. The conventional VLSI design flow contains place- ment, signal routing, clock tree insertion, and timing closure. The underlying formal problems of these steps have been extensively studied over the past decades, which have led to academic findings and the discovery of applicable algorithms (cf. [94, 106] for an overview). However, these problems are yet to be theoretically investigated for the FCN domain. A handful of rather greedy solutions are available to tackle the domain- specific physical design problems with their tightened routing and synchronization constraints, e.g., [27, 34, 57, 181]. Due to the lack of clear establishment of the underlying formal problems at the time, these solutions suffer from scalability or quality issues. It is therefore unknown whether these impairments were caused by insufficient methodology or complexity reasons. Theoretical findings aid in the development of efficient algorithms or reveal that such algorithms do not exist. Also in the latter case, valuable knowledge is acquired: (1) one can stop wasting resources on trying to find efficient methods or on running greedy approaches, (2) the formal problem definition acquired in the process provides a specification for tackling the intractable problem with satisfiability engines (cf. Chap. 4), and (3) similarities to other (possibly well- studied) problems become apparent so that findings of their approximations can be utilized (cf. Chap. 5). This chapter provides a fundamental basis for any future theoretical and practical work in the field [189]. In Sect. 3.1, a formal and sound definition of the tile- based placement and routing problem for FCN circuit layouts is given. Section 3.2 presents intractability proofs (under the assumption P = NP) for the decision and the optimization variant of the problem in question for various configurations, i.e., the relaxation of certain requirements based on real-world design decisions. The theoretical findings established in this chapter are directly applied in Chaps. 4, 5, and 6 that present exact, scalable, and one-pass solutions, respectively. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 M. Walter et al., Design Automation for Field-coupled Nanotechnologies, https://doi.org/10.1007/978-3-030-89952-3_3 37
- 52. 38 3 Theoretical Groundwork 3.1 FCN Placement and Routing Problem Definition In this section, a formal definition of the placement and routing problem for tile- based gate-level FCN circuit layouts is given [189]. As reviewed in Sect. 2.3, placement, signal routing, and timing closure are highly interdependent in the FCN domain. For this reason, they can be best formulated as a joint problem. First, the decision problem variant is introduced and then extended to an optimization problem. Definition 3.1 Let the decision problem of tile-based gate-level FCN placement and routing be called FCNPR. Its inputs are an empty, unclocked layout L = (G, N, p, r, c) of fixed size, i. e., |L| tiles, and a constant clk ∈ N that represents the number of clock phases in the technology. To keep this problem definition as generic as possible, here, G is not restricted to a grid graph or any regular topological shape. There must, however, be a relation A ⊆ T × T that defines adjacency between the tiles. The logic network N can represent any Boolean function but it is assumed that there exists a gate library that contains uniform single-tile implementations of all utilized logic node types. Alternatively, N has first to be substituted to conform to this restriction. FCNPR evaluates to true for L and clk iff there exists a 3-tuple of injective mappings (p, r, c), where p : → T is the gate placement, r : → PL is the wire routing,1 and c : T → {1, . . . , clk} is the clock number assignment, such that the following constraints hold: 1. Routing constraint: Each signal connecting the nodes xi and xj in the logic network is routed on the layout in such a way that it starts at the tile t1, where xi is placed, ends at the tile tn where xj is placed, and does not cross any gate (crossing other wire segments, however, is allowed). This can be formally expressed as ∀σ = (xi, xj ) ∈ : ((r(σ) = τ = {t1, . . . , tl}) ⇒ (t1 = p(xi) ∧ tl = p(xj ))) ∧ ∀x ∈ N : p(x) / ∈ τ {t1, tl}. 2. Local Synchronization Constraint: For each routed signal, the clock numbers must be assigned to the affected tiles such that they are consecutively numbered. This can be formulated as: ∀σ = (xi, xj ) ∈ : (r(σ) = {t1, . . . , tl}) ⇒ ∀k ∈ {2, . . . , l} : ((c(tk) − c(tk−1)) mod clk = 1). 3. Global Synchronization Constraint: All two paths in the logic network, starting at some primary inputs and sharing a common last node, must pass through the same amount of tiles when routed on the layout to compensate delay differences. This can be formally expressed as: ∀p1, p2 ∈ PN (x), p1 = {xi, . . . , x}, and p2 = {xj , . . . , x} : |r(xi, x)| + c(p(xi)) = |r(xj , x)| + c(p(xj )), where ∀x ∈ N : (x, xi), (x, xj ) / ∈ , and p1, p2 are disjoint except for x. Additionally, PN is defined analogously to PL, while |P| denotes the length of a path P. 1 Let PL denote the set of all cycle-free paths in L and let paths be ordered (multi-)sets of tiles.
- 53. 3.2 Intractability Proofs for FCN Placement and Routing 39 Thus far, only the question for the existence of valid solutions is formulated. However, designers are also often interested in optimal solutions for problem instances. Therefore, the optimization variant of FCNPR is introduced, which is called FCNOPR. Definition 3.2 FCNOPR is an optimization problem. Its inputs and constraints are those of FCNPR as given in Definition 3.1. Additionally, an optimization direction ≷ ∈ {min, max} and a measure m(i, s) as a function that maps solutions of an instance s ∈ S(i) = (p, r, c) to a quality value q ∈ N are provided, whose computation must be in FP, i. e., must be computable in polynomial time. FCNOPR returns an optimal solution s∗ ∈ S(i) with respect to ≷ and m if one exists, and false otherwise. A suitable measure could be the number of occupied tiles, which one might want to minimize: m(i, s) := σ∈ |r(σ)|. In this definition, the number of wire segments is respected exclusively, because this is the only variable factor while the number of gates has to stay the same, as by definition of FCNPR. Alternatively, when working on a geometric layout like a grid graph, the bounding box area of the whole design can be used as a minimization measure. For grids, the definition would look like this: m(i, s) := (maxx(T ∗) − minx(T ∗)) · (maxy(T ∗)−miny(T ∗)), where T ∗ is the set that contains all tiles occupied by either a node or a signal, i. e., T ∗ := x∈N {p(x)}∪ σ∈ r(σ). The functions minx/y and maxx/y return the minimum and maximum x- and y-position of the given set’s tiles, respectively. This section formulated the placement and routing problem for tile-based FCN circuits as a decision problem called FCNPR and as an optimization problem called FCNOPR. With these definitions at hand, it becomes possible to reason about their complexity, and by that, to gain theoretical insight. Complexity proofs for both problem variants are given in the next section. 3.2 Intractability Proofs for FCN Placement and Routing In this section, it is proven that both problem variants introduced in the previous section are intractable in various configurations under the (to date still unproven but widely accepted) assumption that P = NP. That is, no deterministic Turing machine exists that solves either problem in polynomial time. To obtain this conclusion, it is shown that FCNPR is NP-complete and FCNOPR is NP-hard. NP-completeness is only defined for decision problems and, conse- quently, cannot be shown for FCNOPR. Lemma 3.1 FCNPR is in NP Proof Assume a non-deterministic Turing machine that guesses the 3-tuple (p, r, c) for a given empty layout L with a logic network N and a constant clk, and additionally checks if it complies with all constraints. Such a check runs in polynomial time because it must consider |L| tiles at most once.
- 54. 40 3 Theoretical Groundwork FCNPR’s NP-hardness is shown next by a polynomial-time reduction from the well-known Hamiltonian path problem (HPP) to FCNPR. Definition 3.3 HPP is a decision problem that was shown to be NP-complete [63]. It receives a (directed) graph G = (V, E) as input. Its output is true iff there exists a path in G that contains each vertex exactly once. Lemma 3.2 FCNPR is NP-hard. Proof To a given instance of HPP, an instance of FCNPR is constructed in polynomial time, so that they are equisatisfiable, i. e., a polynomial-time reduction HPP ≤P FCNPR is conducted. It follows directly that iff an oracle provided a solution for the FCNPR instance, a solution for the HPP instance can be deduced. Thus, HPP cannot be harder than FCNPR. The reduction is as follows. Given a directed graph G = (V, E) with m vertices. It is to be decided whether HPP returns true for G, i. e., if G is an element of the language LHPP. Construct a logic network N = (, I, , O) in a way that = V , I = {x1}, = {(x1, x2), (x2, x3), . . . , (xm−1, xm)}, and O = {f }, with f = xm, xi ∈ ∪ I, i. e., a chain of all m nodes.2 This can be done in linear time. In the following, G serves as a layout for N. Since the number of G’s vertices and N’s nodes is identical, a bijective gate placement p is possible. It is, thus, also is injective by definition and, consequently, satisfies FCNPR’s requirement. If the wire routing r can be employed while meeting the routing constraint, a Hamiltonian path has been found. This means, if the nodes are placed in a way that they are directly adjacent on the layout if they are adjacent in the logic network, the routing constraint can be fulfilled. Nonetheless, the local synchronization constraint must be met as well, to truly satisfy FCNPR. If the embedding is possible thus far, c can be chosen so that the tile onto which node xi is placed is assigned clock number i mod clk, because propagating information through a chain is exclusively possible this way. Finally, the global synchronization constraint is trivially satisfied because there are no two paths that are disjoint except for their last node in the logic network. As a consequence, HPP holds for G iff FCNPR holds for G with N, i. e., iff it is possible to embed the m-node chain in G. Thus, FCNPR is NP-hard. Example 3.1 To provide a visual intuition of how the node chain embedding works, which is the core of the reduction, the task of finding a Hamiltonian path in a 3 × 3 grid graph is considered as an example. The graph consists of 9 vertices, i.e., a 9- node chain is created, like the one shown in Fig. 3.1a. If it is possible to embed this chain in the grid graph, i. e., determining mappings p and r, a Hamiltonian path has been found that starts at the vertex where the first node is placed and ends at the vertex where the last node is placed. This is depicted in Fig. 3.1b. As it can be seen, determining the clocking c becomes trivial afterward by consecutively clock-numbering along with the chain, hence, satisfying the local synchronization 2 It is assumed that there is a respective node supported by a gate library. Thus for, the identity function, i. e., wire segments, or inverters can be employed.
- 55. Another Random Scribd Document with Unrelated Content
- 59. The Project Gutenberg eBook of In Darkest Africa, Vol. 1; or, The Quest, Rescue, and Retreat of Emin, Governor of Equatoria
- 60. This ebook is for the use of anyone anywhere in the United States and most other parts of the world at no cost and with almost no restrictions whatsoever. You may copy it, give it away or re-use it under the terms of the Project Gutenberg License included with this ebook or online at www.gutenberg.org. If you are not located in the United States, you will have to check the laws of the country where you are located before using this eBook. Title: In Darkest Africa, Vol. 1; or, The Quest, Rescue, and Retreat of Emin, Governor of Equatoria Author: Henry M. Stanley Release date: September 6, 2013 [eBook #43654] Most recently updated: October 23, 2024 Language: English Credits: Produced by Chuck Greif and the Online Distributed Proofreading Team at http://www.pgdp.net (This file was produced from images generously made available by the Posner Memorial Collection (http://posner.library.cmu.edu/Posner/)) *** START OF THE PROJECT GUTENBERG EBOOK IN DARKEST AFRICA, VOL. 1; OR, THE QUEST, RESCUE, AND RETREAT OF EMIN, GOVERNOR OF EQUATORIA ***
- 61. Every attempt has been made to replicate the original as printed. The footnotes follow the text. Some illustrations have been moved from mid-paragraph for ease of reading. (etext transcriber's note)
- 63. COPYRIGHT 1890 BY CHARLES SCRIBNER'S SONS IN DARKEST AFRICA OR THE QUEST, RESCUE, AND RETREAT OF EMIN GOVERNOR OF EQUATORIA BY HENRY M. STANLEY WITH TWO STEEL ENGRAVINGS, AND ONE HUNDRED AND FIFTY ILLUSTRATIONS AND MAPS IN TWO VOLUMES Vol. I I will not cease to go forward until I come to the place where the two seas meet, though I travel ninety years.—Koran, chap. xviii., v. 62. NEW YORK CHARLES SCRIBNER'S SONS 1890 [All rights reserved] Copyright, 1890, by CHARLES SCRIBNER'S SONS Press of J. J. Little Co., Astor Place, New York.
- 64. CONTENTS OF VOLUME I. PAGE Prefatory Letter to Sir William Mackinnon, Chairman of the Emin Pasha relief expedition 1 CHAPTER I. INTRODUCTORY CHAPTER. The Khedive and the Soudan—Arabi Pasha—Hicks Pasha's defeat—The Mahdi—Sir Evelyn Baring and Lord Granville on the Soudan—Valentine Baker Pasha— General Gordon: his work in the Upper Soudan—Edward Schnitzler (or Emin Effendi Hakim) and his Province— General Gordon at Khartoum: and account of the Relief Expedition in 1884 under Lord Wolseley—Mr. A. M. Mackay, the missionary in Uganda—Letters from Emin Bey to Mr. Mackay, Mr. C. H. Allen, and Dr. R. W. Felkin, relating to his Province—Mr. F. Holmwood's and Mr. A. M. Mackay's views on the proposed relief of Emin —Suggested routes for the Emin Relief Expedition—Sir Wm. Mackinnon and Mr. J. F. Hutton—The Relief Fund and preparatory details of the Expedition—Colonel Sir Francis De Winton—Selection of officers for the Expedition—King Leopold and the Congo Route— Departure for Egypt 11 CHAPTER II. EGYPT AND ZANZIBAR. Surgeon T. H. Parke—Views of Sir Evelyn Baring, Nubar Pasha, Professor Schweinfurth and Dr. Junker on the Emin Relief Expedition—Details relating to Emin Pasha 49
- 65. and his Province—General Grenfell and the ammunition —Breakfast with Khedive Tewfik: message to Emin Pasha—Departure for Zanzibar—Description of Mombasa town—Visit to the Sultan of Zanzibar—Letter to Emin Pasha sent by messenger through Uganda— Arrangements with Tippu-Tib—Emin Pasha's Ivory—Mr. MacKenzie, Sir John Pender, and Sir James Anderson's assistance to the Relief Expedition CHAPTER III. BY SEA TO THE CONGO RIVER. The Sultan of Zanzibar—Tippu-Tib and Stanley Falls— On board s.s. Madura—Shindy between the Zanzibaris and Soudanese—Sketches of my various Officers— Tippu-Tib and Cape Town—Arrival at the mouth of the Congo River—Start up the Congo—Visit from two of the Executive Committee of the Congo State—Unpleasant thoughts 67 CHAPTER IV. TO STANLEY POOL. Details of the journey to Stanley Pool—The Soudanese and the Somalis—Meeting with Mr. Herbert Ward— Camp at Congo la Lemba—Kindly entertained by Mr. and Mrs. Richards—Letters from up river—Letters to the Rev. Mr. Bentley and others for assistance—Arrival at Mwembi—Necessity of enforcing discipline—March to Vombo—Incident at Lukungu Station—The Zanzibaris— Incident between Jephson and Salim at the Inkissi River —A series of complaints—The Rev. Mr. Bentley and the steamer Peace—We reach Makoko's village— Leopoldville—Difficulties regarding the use of the Mission steamers—Monsieur Liebrichts sees Mr. Billington—Visit to Mr. Swinburne at Kinshassa— Orders to, and duties of, the officers 79
- 66. CHAPTER V. FROM STANLEY POOL TO YAMBUYA. Upper Congo scenery—Accident to the Peace—Steamers reach Kimpoko—Collecting fuel—The good-for-nothing Peace—The Stanley in trouble—Arrival at Bolobo—The Relief Expedition arranged in two columns—Major Barttelot and Mr. Jameson chosen for command of Rear Column—Arrival at Equator and Bangala Stations—The Basoko villages: Baruti deserts us—Arrival at Yambuya 99 CHAPTER VI. AT YAMBUYA. We land at Yambuya villages—The Stanley leaves for Equator Station—Fears regarding Major Barttelot and the Henry Reed—Safe arrival—Instructions to Major Barttelot and Mr. Jameson respecting the Rear Column— Major Barttelot's doubts as to Tippu-Tib's good faith—A long conversation with Major Barttelot—Memorandum for the officers of the Advance Column—Illness of Lieutenant Stairs—Last night at Yambuya: statements as to our forces and accoutrements 111 CHAPTER VII. TO PANGA FALLS. An African road—Our mode of travelling through the forests—Farewell to Jameson and the Major—160 days in the forest—The Rapids of Yambuya—Attacked by natives of Yankonde—Rest at the village of Bahunga— Description of our march—The poisoned skewers— Capture of six Babali—Dr. Parke and the bees—A tempest in the forest—Mr. Jephson puts the steel boat together—The village of Bukanda—Refuse heaps of the villages—The Aruwimi river scenery—Villages of the Bakuti and the Bakoka—The Rapids of Gwengweré— The boy Bakula-Our chop and coffee—The islands 134
- 67. near Bandangi—The Baburu dwarfs—The unknown course of the river—The Somalis—Bartering at Mariri and Mupé—The Aruwimi at Mupé—The Babé manners, customs, and dress—Jephson's two adventures—Wasp Rapids—The chief of the Bwamburi—Our camp at My- yui—Canoe accident—An abandoned village—Arrival at Panga Falls—Description of the Falls CHAPTER VIII. FROM TANGA FALLS TO UGARROWWA'S. Another accident at the Rapids—The village of Utiri— Avisibba settlement—Enquiry into a murder case at Avisibba—Surprised by the natives—Lieutenant Stairs wounded—We hunt up the enemy—The poisoned arrows —Indifference of the Zanzibaris—Jephson's caravan missing—Our wounded—Perpetual rain—Deaths of Khalfan, Saadi, and others—Arrival of caravan—The Mabengu Rapids—Mustering the people—The Nepoko river—Remarks by Binza—Our food supply—Reckless use of ammunition—Half-way to the Albert Lake—We fall in with some of Ugarrowwa's men—Absconders— We camp at Hippo Broads and Avakubi Rapids—The destroyed settlement of Navabi—Elephants at Memberri —More desertions—The Arab leader, Ugarrowwa—He gives us information—Visit to the Arab settlement—First specimen of the tribe of dwarfs—Arrangements with Ugarrowwa 171 CHAPTER IX. UGARROWWA'S TO KILONGA-LONGA'S. Ugarrowwa sends us three Zanzibari deserters—We make an example—The 'Express' rifles—Conversation with Rashid—The Lenda river—Troublesome rapids— Scarcity of food—Some of Kilonga-Longa's followers— Meeting of the rivers Ihuru and Ituri—State and numbers of the Expedition—Illness of Captain Nelson—We send 211
- 68. couriers ahead to Kilonga-Longa's—The sick encampment—Randy and the guinea fowl—Scarcity of food—Illness caused by the forest pears—Fanciful menus—More desertions—Asmani drowned—Our condition in brief—Uledi's suggestion—Umari's climb— My donkey is shot for food—We strike the track of the Manyuema and arrive at their village CHAPTER X. WITH THE MANYUEMAAT IPOTO. The ivory hunters at Ipoto—Their mode of proceeding— The Manyuema headmen and their raids—Remedy for preventing wholesale devastations—Crusade preached by Cardinal Lavigerie—Our Zanzibar chiefs—Anxiety respecting Captain Nelson and his followers—Our men sell their weapons for food—Theft of rifles—Their return demanded—Uledi turns up with news of the missing chiefs—Contract drawn up with the Manyuema headmen for the relief of Captain Nelson—Jephson's report on his journey—Reports of Captain Nelson and Surgeon Parke —The process of blood brotherhood between myself and Ismaili—We leave Ipoto 236 CHAPTER XI. THROUGH THE FOREST TO MAZAMBONI'S PEAK. In the country of the Balessé—Their houses and clearings —Natives of Bukiri—The first village of dwarfs—Our rate of progress increased—The road from Mambungu's —Halts at East and West Indékaru—A little storm between Three o'clock and Khamis—We reach Ibwiri —Khamis and the vile Zanzibaris—The Ibwiri clearing —Plentiful provisions—The state of my men; and what they had recently gone through—Khamis and party explore the neighbourhood—And return with a flock of goats—Khamis captures Boryo, but is released—Jephson 255
- 69. returns from the relief of Captain Nelson—Departure of Khamis and the Manyuema—Memorandum of charges against Messrs. Kilonga-Longa amp; Co. of Ipoto— Suicide of Simba—Sali's reflections on the same— Lieutenant Stairs reconnoitres—Muster and reorganisation at Ibwiri—Improved condition of the men —Boryo's village—Balessé customs—East Indenduru— We reach the outskirts of the forest—Mount Pisgah—The village of Iyugu—Heaven's light at last; the beautiful grass-land—We drop across an ancient crone—Indésura and its products—Juma's capture—The Ituri river again —We emerge upon a rolling plain—And forage in some villages—The mode of hut construction—The district of the Babusessé—Our Mbiri captives—Natives attack the camp—The course of the Ituri—The natives of Abunguma—Our fare since leaving Ibwiri— Mazamboni's Peak—The east Ituri—A mass of plantations—Demonstration by the natives—Our camp on the crest of Nzera-Kum—Be strong and of a good courage—Friendly intercourse with the natives—We are compelled to disperse them—Peace arranged—Arms of the Bandussuma CHAPTER XII. ARRIVALAT LAKE ALBERT AND OUR RETURN TO IBWIRI. We are further annoyed by the natives—Their villages fired—Gavira's village—We keep the natives at bay— Plateau of Unyoro in view—Night attack by the natives —The village of Katonza's—Parley with the natives—No news of the Pasha—Our supply of cartridges—We consider our position—Lieutenant Stairs converses with the people of Kasenya Island—The only sensible course left us—Again attacked by natives—Scenery on the lake's shore—We climb a mountain—A rich discovery of grain—The rich valley of Undussuma—Our return journey to Ibwiri—The construction of Fort Bodo 319
- 70. CHAPTER XIII. LIFE AT FORT BODO. Our impending duties—The stockade of Fort Bodo— Instructions to Lieutenant Stairs—His departure for Kilonga-Longa's—Pested by rats, mosquitoes, amp;c. —Nights disturbed by the lemur—Armies of red ants— Snakes in tropical Africa—Hoisting the Egyptian flag— Arrival of Surgeon Parke and Captain Nelson from Ipoto —Report of their stay with the Manyuema—Lieutenant Stairs arrives with the steel boat—We determine to push on to the Lake at once—Volunteers to convey letters to Major Barttelot—Illness of myself and Captain Nelson— Uledi captures a Queen of the Pigmies—Our fields of corn—Life at Fort Bodo—We again set out for the Nyanza 350 CHAPTER XIV. TO THE ALBERT NYANZAA SECOND TIME. Difficulties with the steel boat—African forest craft— Splendid capture of pigmies, and description of the same —We cross the Ituri River—Dr. Parke's delight on leaving the forest—Camp at Bessé—Zanzibari wit—At Nzera-Kum Hill once more—Intercourse with the natives —Malleju, or the Bearded One, being first news of Emin—Visit from chief Mazamboni and his followers— Jephson goes through the form of friendship with Mazamboni—The medicine men, Nestor and Murabo— The tribes of the Congo—Visit from chief Gavira—A Mhuma chief—The Bavira and Wahuma races—The varying African features—Friendship with Mpinga— Gavira and the looking-glass—Exposed Uzanza—We reach Kavalli—The chief produces Malleju's letter— Emin's letter—Jephson and Parke convey the steel boat to the lake—Copy of letter sent by me to Emin through Jephson—Friendly visits from natives 373
- 71. CHAPTER XV. THE MEETING WITH EMIN PASHA. Our camp at Bundi—Mbiassi, the chief of Kavalli—The Balegga granaries—Chiefs Katonza and Komubi express contrition—The kites at Badzwa—A note from Jephson —Emin, Casati and Jephson walk into our camp at old Kavalli—Descriptions of Emin Pasha and Captain Casati —The Pasha's Soudanese—Our Zanzibaris—The steamer Khedive—Baker and the Blue Mountains—Drs. Junker and Felkin's descriptions of Emin—Proximity of Kabba Rega—Emin and the Equatorial Provinces—Dr. Junker's report of Emin—I discuss with Emin our future proceedings—Captain Casati's plans—Our camp and provisions at Nsabé—Kabba Rega's treatment of Captain Casati and Mohammed Biri—Mabruki gored by a buffalo —Emin Pasha and his soldiers—My propositions to Emin and his answer—Emin's position—Mahomet Achmet—The Congo State—The Foreign Office despatches 393 CHAPTER XVI. WITH THE PASHA—continued. Fortified stations in the Province—Storms at Nsabé—A nest of young crocodiles—Lake Ibrahim—Zanzibari raid on Balegga villages—Dr. Parke goes in search of the two missing men—The Zanzibaris again—A real tornado— The Pasha's gifts to us—Introduced to Emin's officers— Emin's cattle forays—The Khedive departs for Mswa station—Mabruki and his wages—The Pasha and the use of the sextant—Departure of local chiefs—Arrival of the Khedive and Nyanza steamers with soldiers—Made arrangements to return in search of the rear-column—My message to the troops—Our Badzwa road—A farewell dance by the Zanzibaris—The Madi carriers' disappearance—First sight of Ruwenzori—Former 418
- 72. circumnavigators of the Albert Lake—Lofty twin-peak mountain near the East Ituri River—Aid for Emin against Kabba Rega—Two letters from Emin Pasha—We are informed of an intended attack on us by chiefs Kadongo and Musiri—Fresh Madi carriers—We attack Kadongo's camp—With assistance from Mazamboni and Gavira we march on Musiri's camp which turns out to be deserted— A phalanx dance by Mazamboni's warriors—Music on the African Continent—Camp at Nzera-kum Hill— Presents from various chiefs—Chief Musiri wishes for peace CHAPTER XVII. PERSONAL TO THE PASHA. Age and early days of Emin Pasha—Gordon and the pay of Emin Pasha—Last interview with Gordon Pasha in 1877—Emin's last supply of ammunition and provisions —Five years' isolation—Mackay's library in Uganda— Emin's abilities and fitness for his position—His linguistic and other attainments—Emin's industry—His neat journals—Story related to me by Shukri Agha referring to Emin's escape from Kirri to Mswa—Emin confirms the story—Some natural history facts related to me by Emin—The Pasha and the Dinka tribe—A lion story—Emin and bird studies 422 CHAPTER XVIII. START FOR THE RELIEF OF THE REAR COLUMN. Escorted by various tribes to Mukangi—Camp at Ukuba village—Arrival at Fort Bodo—Our invalids in Ugarrowwa's care—Lieut. Stairs' report on his visit to bring up the invalids to Fort Bodo—Night visits by the malicious dwarfs—A general muster of the garrison—I decide to conduct the Relief force in person—Captain Nelson's ill-health—My little fox-terrier Randy— 452
- 73. Description of the fort—The Zanzibaris—Estimated time to perform the journey to Yambuya and back—Lieut. Stairs' suggestion about the steamer Stanley— Conversation with Lieut. Stairs in reference to Major Barttelot and the Rear Column—Letter of instructions to Lieut. Stairs CHAPTER XIX. ARRIVALAT BANALYA: BARTTELOT DEAD! The Relief Force—The difficulties of marching—We reach Ipoto—Kilonga Longa apologises for the behaviour of his Manyuema—The chief returns us some of our rifles—Dr. Parke and fourteen men return to Fort Bodo— Ferrying across the Ituri River—Indications of some of our old camps—We unearth our buried stores—The Manyuema escort—Bridging the Lenda River—The famished Madi—Accidents and deaths among the Zanzibaris and Madi—My little fox-terrier Randy— The vast clearing of Ujangwa—Native women guides— We reach Ugarrowwa's abandoned station—Welcome food at Amiri Falls—Navabi Falls—Halt at Avamburi landing-place—Death of a Madi chief—Our buried stores near Basopo unearthed and stolen—Juma and Nassib wander away from the Column—The evils of forest marching—Conversation between my tent-boy, Sali, and a Zanzibari—Numerous bats at Mabengu village—We reach Avisibba, and find a young Zanzibari girl— Nejambi Rapids and Panga Falls—The natives of Panga —At Mugwye's we disturb an intended feast—We overtake Ugarrowwa at Wasp Rapids and find our couriers and some deserters in his camp—The head courier relates his tragic story—Amusing letter from Dr. Parke to Major Barttelot—Progress of our canoe flotilla down the river—The Batundu natives—Our progress since leaving the Nyanza—Thoughts about the Rear Column—Desolation along the banks of the river—We 468
- 74. reach Banalya—Meeting with Bonny—The Major is dead—Banalya Camp CHAPTER XX. THE SAD STORY OF THE REAR COLUMN. Tippu-Tib—Major E. M. Barttelot—Mr. J. S. Jameson— Mr. Herbert Ward—Messrs. Troup and Bonny—Major Barttelot's Report on the doings of the Rear Column— Conversation with Mr. Bonny—Major Barttelot's letter to Mr. Bonny—Facts gleaned from the written narrative of Mr. Wm. Bonny—Mr. Ward detained at Bangala— Repeated visits of the Major to Stanley Falls—Murder of Major Barttelot—Bonny's account of the murder—The assassin Sanga is punished—Jameson dies of fever at Bangala Station—Meeting of the advance and rear columns—Dreadful state of the camp—Tippu-Tib and Major Barttelot—Mr. Jameson—Mr. Herbert Ward's report 498 APPENDIX. Copy of Log of Rear Column 527
- 75. LIST OF ILLUSTRATIONS VOLUME I. STEEL ENGRAVING. Portrait of Henry M. Stanley Frontispiece (From a Photograph by Elliott Fry, 1886) FULL-PAGE ILLUSTRATIONS. Facing page Group—Mr. Stanley and his Officers. 1 The Steel Boat Advance 80 In the Night and Rain in the Forest 146 The Fight with the Avisibba Cannibals 174 The River Column Ascending the Aruwimi River with the Advance and Sixteen Canoes. 184 Wooden Arrows of the Avisibba 180 The Pasha is Coming 196 The Relief of Nelson and Survivors at Starvation Camp 250 Gymnastics in a Forest Clearing 258 Iyugu; a Call to Arms 286 Emerging from the Forest 292 First Experiences with Mazamboni's People. View from Nzera Kum Hill 306 View of the South End of Albert Nyanza 324 Sketch-Map: Return to Ugarrowa's. By Lieutenant Stairs 365 Emin and Casati Arrive at Lake Shore Camp 396 A Phalanx Dance by Mazamboni's Warriors 438 Meeting with the Rear Column at Banalya 494 OTHER ILLUSTRATIONS. Portrait of Emin Pasha 18 Portrait of Captain Nelson 39 Portrait of Lieutenant Stairs 40
- 76. Portrait of William Bonny 41 Portrait of A. J. Mounteney Jephson 42 Portrait of Surgeon Parke, A. M. D. 50 Portrait of Nubar Pasha 51 Portrait of The Khedive Tewfik 55 Portrait of Tippu-Tib 68 Maxim Automatic Gun 83 Launching the Steamer Florida 96 Stanley Pool 100 Baruti Finds his Brother 109 A Typical Village on the Lower Aruwimi 112 Landing at Yambuya 113 Diagram Of Forest Camps 130 Marching Through the Forest 135 The Kirangozi, or Foremost Man 137 Head-Dress—Crown of Bristles 160 Paddle of the Upper Aruwimi or Ituri 160 Wasps' Nests 164 Fort Island, Near Panga Falls 168 Panga Falls 169 View of Utiri Village 172 Leaf-Bladed Paddle of Avisibba 174 A Head-Dress of Avisibba Warriors 178 Coroneted Avisibba Warrior—Head-Dress 179 Cascades of the Nepoko 193 View of Bafaido Cataract 202 Attacking an Elephant in the Ituri River 203 Randy Seizes the Guinea Fowl 224 Kilonga Longa's Station 234 Shields of the Balessé 256 View of Mount Pisgah from the Eastward 281 Villages of the Bakwuru on a Spur of Pisgah 283 A Village at the Base of Pisgah 284 Chief of the Iyugu 285 Pipes of Forest Tribes 290
- 77. Shields of Babusessé 299 Suspension Bridge Across the East Ituri 304 Shield of the Edge of the Plains 317 The South End of the Albert Nyanza, Dec. 13, 1887 318 Corn Granary of the Babusessé 342 A Village of the Baviri: Europeans Tailoring 345 Great Rock Near Indétonga 348 Exterior View of Fort Bodo 349 Interior View of Fort Bodo 351 Plan of Fort Bodo and Vicinity, by Lieutenant Stairs 354 The Queen of the Dwarfs 368 Within Fort Bodo 371 One of Mazamboni's Warriors 384 Kavalli, Chief of the Babiassi 389 Milk Vessel of the Wahuma 392 The Steamers Khedive and Nyanza on Lake Albert 426 View of Banalya Curve 493 Portrait of Major Barttelot 499 Portrait of Mr. Jameson 501 MAP. A Map of the Great Forest Region, Showing the Route of the Emin Pasha Relief Expedition from the River Congo to Victoria Nyanza. By Henry M. Stanley. In Pocket.
- 78. GROUP OF MR. STANLEY AND OFFICERS.
- 79. IN DARKEST AFRICA. PREFATORY LETTER My Dear Sir William, I have great pleasure in dedicating this book to you. It professes to be the Official Report to yourself and the Emin Relief Committee of what we have experienced and endured during our mission of Relief, which circumstances altered into that of Rescue. You may accept it as a truthful record of the journeyings of the Expedition which you and the Emin Relief Committee entrusted to my guidance. I regret that I was not able to accomplish all that I burned to do when I set out from England in January, 1887, but the total collapse of the Government of Equatoria thrust upon us the duty of conveying in hammocks so many aged and sick people, and protecting so many helpless and feeble folk, that we became transformed from a small fighting column of tried men into a mere Hospital Corps to whom active adventure was denied. The Governor was half blind and possessed much luggage, Casati was weakly and had to be carried, and 90 per cent. of their followers were, soon after starting, scarcely able to travel from age, disease, weakness or infancy. Without sacrificing our sacred charge, to assist which was the object of the Expedition, we could neither deviate to the right or to the left, from the most direct road to the sea. You who throughout your long and varied life have steadfastly believed in the Christian's God, and before men have professed your devout thankfulness for many mercies vouchsafed to you, will better understand than many others the feelings which animate me when I find myself back again in civilization, uninjured in life or health, after passing through so many stormy and distressful periods. Constrained at the darkest hour to humbly confess that without God's help I was helpless, I vowed a vow in the forest solitudes that I would confess His aid before men. A silence as of death was round about me; it was midnight; I was weakened by illness, prostrated with fatigue and worn with anxiety for my white and black companions, whose fate was a mystery. In this physical and mental distress
- 80. I besought God to give me back my people. Nine hours later we were exulting with a rapturous joy. In full view of all was the crimson flag with the crescent, and beneath its waving folds was the long-lost rear column. Again, we had emerged into the open country out of the forest, after such experiences as in the collective annals of African travels there is no parallel. We were approaching the region wherein our ideal Governor was reported to be beleaguered. All that we heard from such natives as our scouts caught prepared us for desperate encounters with multitudes, of whose numbers or qualities none could inform us intelligently, and when the population of Undusuma swarmed in myriads on the hills, and the valleys seemed alive with warriors, it really seemed to us in our dense ignorance of their character and power, that these were of those who hemmed in the Pasha to the west. If he with his 4000 soldiers appealed for help, what could we effect with 173? The night before I had been reading the exhortation of Moses to Joshua, and whether it was the effect of those brave words, or whether it was a voice, I know not, but it appeared to me as though I heard: Be strong, and of a good courage, fear not, nor be afraid of them, for the Lord thy God He it is that doth go with thee, He will not fail thee nor forsake thee. When on the next day Mazamboni commanded his people to attack and exterminate us, there was not a coward in our camp, whereas the evening before we exclaimed in bitterness on seeing four of our men fly before one native, And these are the wretches with whom we must reach the Pasha! And yet again. Between the confluence of the Ihuru and the Dui rivers in December 1888, 150 of the best and strongest of our men had been despatched to forage for food. They had been absent for many days more than they ought to have been, and in the meantime 130 men besides boys and women were starving. They were supported each day with a cup of warm thin broth, made of butter, milk and water, to keep death away as long as possible. When the provisions were so reduced that there were only sufficient for thirteen men for ten days, even of the thin broth with four tiny biscuits each per day, it became necessary for me to hunt up the missing men. They might, being without a leader, have been reckless, and been besieged by an overwhelming force of vicious dwarfs. My following consisted of sixty-six men, a few women and children, who, more active than the others, had assisted the thin fluid with the berries of the phrynium and the amomum, and such fungi as could be discovered in damp places,
- 81. and therefore were possessed of some little strength, though the poor fellows were terribly emaciated. Fifty-one men, besides boys and women, were so prostrate with debility and disease that they would be hopelessly gone if within a few hours food did not arrive. My white comrade and thirteen men were assured of sufficient for ten days to protract the struggle against a painful death. We who were bound for the search possessed nothing. We could feed on berries until we could arrive at a plantation. As we travelled that afternoon we passed several dead bodies in various stages of decay, and the sight of doomed, dying and dead produced on my nerves such a feeling of weakness that I was well-nigh overcome. Every soul in that camp was paralysed with sadness and suffering. Despair had made them all dumb. Not a sound was heard to disturb the deathly brooding. It was a mercy to me that I heard no murmur of reproach, no sign of rebuke. I felt the horror of silence of the forest and the night intensely. Sleep was impossible. My thoughts dwelt on these recurring disobediences which caused so much misery and anxiety. Stiff-necked, rebellious, incorrigible human nature, ever showing its animalism and brutishness, let the wretches be for ever accursed! Their utter thoughtless and oblivious natures and continual breach of promises kill more men, and cause more anxiety, than the poison of the darts or barbs and points of the arrows. If I meet them I will— But before the resolve was uttered flashed to my memory the dead men on the road, the doomed in the camp, and the starving with me, and the thought that those 150 men were lost in the remorseless woods beyond recovery, or surrounded by savages without hope of escape, then do you wonder that the natural hardness of the heart was softened, and that I again consigned my case to Him who could alone assist us. The next morning within half-an-hour of the start we met the foragers, safe, sound, robust, loaded, bearing four tons of plantains. You can imagine what cries of joy these wild children of nature uttered, you can imagine how they flung themselves upon the fruit, and kindled the fires to roast and boil and bake, and how, after they were all filled, we rode back to the camp to rejoice those unfortunates with Mr. Bonny. As I mentally review the many grim episodes and reflect on the marvellously narrow escapes from utter destruction to which we have been subjected during our various journeys to and fro through that immense and gloomy extent of primeval woods, I feel utterly unable to attribute our salvation to any other cause than to a gracious Providence who for some
- 82. purpose of His own preserved us. All the armies and armaments of Europe could not have lent us any aid in the dire extremity in which we found ourselves in that camp between the Dui and Ihuru; an army of explorers could not have traced our course to the scene of the last struggle had we fallen, for deep, deep as utter oblivion had we been surely buried under the humus of the trackless wilds. It is in this humble and grateful spirit that I commence this record of the progress of the Expedition from its inception by you to the date when at our feet the Indian Ocean burst into view, pure and blue as Heaven when we might justly exclaim It is ended! What the public ought to know, that have I written; but there are many things that the snarling, cynical, unbelieving, vulgar ought not to know. I write to you and to your friends, and for those who desire more light on Darkest Africa, and for those who can feel an interest in what concerns humanity. My creed has been, is, and will remain so, I hope, to act for the best, think the right thought, and speak the right word, as well as a good motive will permit. When a mission is entrusted to me and my conscience approves it as noble and right, and I give my promise to exert my best powers to fulfil this according to the letter and spirit, I carry with me a Law, that I am compelled to obey. If any associated with me prove to me by their manner and action that this Law is equally incumbent on them, then I recognize my brothers. Therefore it is with unqualified delight that I acknowledge the priceless services of my friends Stairs, Jephson, Nelson and Parke, four men whose devotion to their several duties were as perfect as human nature is capable of. As a man's epitaph can only be justly written when he lies in his sepulchre, so I rarely attempted to tell them during the journey, how much I valued the ready and prompt obedience of Stairs, that earnestness for work that distinguished Jephson, the brave soldierly qualities of Nelson, and the gentle, tender devotion paid by our Doctor to his ailing patients; but now that the long wanderings are over, and they have bided and laboured ungrudgingly throughout the long period, I feel that my words are poor indeed when I need them to express in full my lasting obligations to each of them. Concerning those who have fallen, or who were turned back by illness or accident, I will admit, with pleasure, that while in my company every one
- 83. seemed most capable of fulfilling the highest expectations formed of them. I never had a doubt of any one of them until Mr. Bonny poured into my ears the dismal story of the rear column. While I possess positive proofs that both the Major and Mr. Jameson were inspired by loyalty, and burning with desire throughout those long months at Yambuya, I have endeavoured to ascertain why they did not proceed as instructed by letter, or why Messrs. Ward, Troup and Bonny did not suggest that to move little by little was preferable to rotting at Yambuya, which they were clearly in danger of doing, like the 100 dead followers. To this simple question there is no answer. The eight visits to Stanley Falls and Kasongo amount in the aggregate to 1,200 miles; their journals, log books, letters teem with proofs that every element of success was in and with them. I cannot understand why the five officers, having means for moving, confessedly burning with the desire to move, and animated with the highest feelings, did not move on along our tract as directed; or, why, believing I was alive, the officers sent my personal baggage down river and reduced their chief to a state of destitution; or, why they should send European tinned provisions and two dozen bottles of Madeira down river, when there were thirty-three men sick and hungry in camp; or, why Mr. Bonny should allow his own rations to be sent down while he was present; or, why Mr. Ward should be sent down river with a despatch, and an order be sent after him to prevent his return to the Expedition. These are a few of the problems which puzzle me, and to which I have been unable to obtain satisfactory solutions. Had any other person informed me that such things had taken place I should have doubted them, but I take my information solely from Major Barttelot's official despatch (See Appendix). The telegram which Mr. Ward conveyed to the sea requests instructions from the London Committee, but the gentlemen in London reply, We refer you to Mr. Stanley's letter of instructions. It becomes clear to every one that there mystery here for which I cannot conceive a rational solution, and therefore each reader of this narrative must think his own thoughts but construe the whole charitably. After the discovery of Mr. Bonny at Banalya, I had frequent occasions to remark to him that his goodwill and devotion were equal to that shown by the others, and as for bravery, I think he has as much as the bravest. With his performance of any appointed work I never had cause for dissatisfaction, and as he so admirably conducted himself with such perfect and respectful obedience while with us from Banalya to the Indian Sea, the
- 84. more the mystery of Yambuya life is deepened, for with 2,000 such soldiers as Bonny under a competent leader, the entire Soudan could be subjugated, pacified and governed. It must thoroughly be understood, however, while reflecting upon the misfortunes of the rear-column, that it is my firm belief that had it been the lot of Barttelot and Jameson to have been in the place of, say Stairs and Jephson, and to have accompanied us in the advance, they would equally have distinguished themselves; for such a group of young gentlemen as Barttelot, Jameson, Stairs, Nelson, Jephson, and Parke, at all times, night or day, so eager for and rather loving work, is rare. If I were to try and form another African State, such tireless, brave natures would be simply invaluable. The misfortunes of the rear-column were due to the resolutions of August 17th to stay and wait for me, and to the meeting with the Arabs the next day. What is herein related about Emin Pasha need not, I hope, be taken as derogating in the slightest from the high conception of our ideal. If the reality differs somewhat from it no fault can be attributed to him. While his people were faithful he was equal to the ideal; when his soldiers revolted his usefulness as a Governor ceased, just as the cabinet-maker with tools may turn out finished wood-work, but without them can do nothing. If the Pasha was not of such gigantic stature as we supposed him to be, he certainly cannot be held responsible for that, any more than he can be held accountable for his unmilitary appearance. If the Pasha was able to maintain his province for five years, he cannot in justice be held answerable for the wave of insanity and the epidemic of turbulence which converted his hitherto loyal soldiers into rebels. You will find two special periods in this narrative wherein the Pasha is described with strictest impartiality to each, but his misfortunes never cause us to lose our respect for him, though we may not agree with that excess of sentiment which distinguished him, for objects so unworthy as sworn rebels. As an administrator he displayed the finest qualities; he was just, tender, loyal and merciful, and affectionate to the natives who placed themselves under his protection, and no higher and better proof of the esteem with which he was regarded by his soldiery can be desired than that he owed his life to the reputation for justice and mildness which he had won. In short, every hour saved from sleep was devoted before his final deposition to some useful purpose conducive to increase of knowledge, improvement of humanity, and gain to civilization.
- 85. You must remember all these things, and by no means lose sight of them, even while you read our impressions of him. I am compelled to believe that Mr. Mounteney Jephson wrote the kindliest report of the events that transpired during the arrest and imprisonment of the Pasha and himself, out of pure affection, sympathy, and fellow-feeling for his friend. Indeed the kindness and sympathy he entertains for the Pasha are so evident that I playfully accuse him of being either a Mahdist, Arabist, or Eminist, as one would naturally feel indignant at the prospect of leading a slave's life at Khartoum. The letters of Mr. Jephson, after being shown, were endorsed, as will be seen by Emin Pasha. Later observations proved the truth of those made by Mr. Jephson when he said, Sentiment is the Pasha's worst enemy; nothing keeps Emin here but Emin himself. What I most admire in him is the evident struggle between his duty to me, as my agent, and the friendship he entertains for the Pasha. While we may naturally regret that Emin Pasha did not possess that influence over his troops which would have commanded their perfect obedience, confidence and trust, and made them pliable to the laws and customs of civilization, and compelled them to respect natives as fellow- subjects, to be guardians of peace and protectors of property, without which there can be no civilization, many will think that as the Governor was unable to do this, that it is as well that events took the turn they did. The natives of Africa cannot be taught that there are blessings in civilization if they are permitted to be oppressed and to be treated as unworthy of the treatment due to human beings, to be despoiled and enslaved at will by a licentious soldiery. The habit of regarding the aborigines as nothing better than pagan abid or slaves, dates from Ibrahim Pasha, and must be utterly suppressed before any semblance of civilization can be seen outside the military settlements. When every grain of corn, and every fowl, goat, sheep and cow which is necessary for the troops is paid for in sterling money or its equivalent in necessary goods, then civilization will become irresistible in its influence, and the Gospel even may be introduced; but without impartial justice both are impossible, certainly never when preceded and accompanied by spoliation, which I fear was too general a custom in the Soudan. Those who have some regard for righteous justice may find some comfort in the reflection that until civilization in its true and real form be introduced into Equatoria, the aborigines shall now have some peace and
- 86. rest, and that whatever aspects its semblance bare, excepting a few orange and lime trees, can be replaced within a month, under higher, better, and more enduring auspices. If during this Expedition I have not sufficiently manifested the reality of my friendship and devotion to you, and to my friends of the Emin Relief Committee, pray attribute it to want of opportunities and force of circumstances and not to lukewarmness and insincerity; but if, on the other hand, you and my friends have been satisfied that so far as lay in my power I have faithfully and loyally accomplished the missions you entrusted to me in the same spirit and to the same purpose that you yourself would have performed them had it been physically and morally possible for you to have been with us, then indeed am I satisfied, and the highest praise would not be equal in my opinion to the simple acknowledgment of it, such as Well done. My dear Sir William, to love a noble, generous and loyal heart like your own, is natural. Accept the profession of mine, which has been pledged long ago to you wholly and entirely. Henry M. Stanley. To Sir William Mackinnon, Bart., of Balinakill and Loup, in the County of Argyleshire, The Chairman of the Emin Pasha Relief Committee. c. c. c.
- 87. CHAPTER I. INTRODUCTORY CHAPTER. The Khedive and the Soudan—Arabi Pasha—Hicks Pasha's defeat—The Mahdi—Sir Evelyn Baring and Lord Granville on the Soudan—Valentine Baker Pasha—General Gordon: his work in the Upper Soudan—Edward Schnitzler (or Emin Effendi Hakim) and his province—General Gordon at Khartoum: and account of the Belief Expedition in 1884, under Lord Wolseley—Mr. A. M. Mackay, the missionary in Uganda —Letters from Emin Bey to Mr. Mackay, Mr. C. H. Allen, and Dr. R. W. Felkin, relating to his Province—Mr. F. Holmwood's and Mr. A. M. Mackay's views on the proposed relief of Emin —Suggested routes for the Emin Relief Expedition—Sir Wm. Mackinnon and Mr. J. F. Hutton—The Relief Fund and Preparatory details of the Expedition—Colonel Sir Francis De Winton—Selection of officers for the Expedition—King Leopold and the Congo Route—Departure for Egypt. Only a Carlyle in his maturest period, as when he drew in lurid colours the agonies of the terrible French Revolution, can do justice to the long catalogue of disasters which has followed the connection of England with Egypt. It is a theme so dreadful throughout, that Englishmen shrink from touching it. Those who have written upon any matters relating to these horrors confine themselves to bare historical record. No one can read through these without shuddering at the dangers England and Englishmen have incurred during this pitiful period of mismanagement. After the Egyptian campaign there is only one bright gleam of sunshine throughout months of oppressive darkness, and that shone over the immortals of Abu- Klea and Gubat, when that small body of heroic Englishmen struggled shoulder to shoulder on the sands of the fatal desert, and won a glory equal to that which the Light Brigade were urged to gain at Balaclava. Those were fights indeed, and atone in a great measure for a series of blunders, that a
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