DESIGN OF A 16-BIT HARVARD STRUCTURED RISC PROCESSOR IN CADENCE 45nmTECHNOLOGY
- 1. CONTENTS o OBJECTIVE o INTRODUCTION o EXISTING METHOD o PROPOSED METHOD o METHODOLOGY o RISC PROCESSOR DESIGN o CONTROL UNIT ASM CHART o RESULTS o ADVANTAGES o APPLICATIONS o CONCLUSION o FUTURE SCOPE o REFERENCES
- 2. OBJECTIVE o The 16-bit RISC Processor is designed to execute computing tasks with the simplest instructions in the shortest amount of time possible. o The design and implementation of a 4-stage pipelining is based on low power processor. Low power was obtained by using Clock Gating Technique.
- 3. INTRODUCTION o Based on the Speed and Performance the Microprocessors and Microcontrollers are designed under two categories 1. RISC (Reduced Instruction Set of Computers ) 2. CISC (Complex Instruction of Computers) o RISC architecture has high power efficiency which is used in portable applications. o CISC instructions execute more complex instructions all at once upon memory.
- 4. EXISTING METHOD o RISC CPU architecture has been designed at higher technological nodes like 250nm,180nm,90nm. o To reduce power dissipation and increase speed of operation, still there is a need to design RISC CPU at advanced technological nodes.
- 5. PROPOSED METHOD o In VLSI, enhancement can be made in two ways. That are 1.Technological advancement. 2.Architectural advancement. o Now by incorporating the instruction set, the RISC processor is designed at 45nm technology.
- 6. METHODOLOGY Literature Survey and Problem Statement Required Specifications of RISC processor Defining Objectives Select desired topology/Architecture Derive Suitable Parameter Values Designing and Simulation Meet the required Specifications Specifications are met Implementation Optimization Techniques
- 7. RISC pipeline stages and meaning Pipeline stage Meaning Fetch CPU receives instruction Decode CPU understands instruction Execute CPU performs computation Access CPU access required data from registers or memory Write back CPU stores result to registers or memory
- 8. INSTRUCTION SET 1. Arithmetic( Two’s Complement)ALU OPERATION : ADD, SUB 2. Logical ALU Operations : AND, OR, XOR, NOT, SLA, SRA 3. Memory Operations : LI, LW, SW 4. Conditional Branch Operations : BIZ, BINZ 5. Program Count Jump Operations : JAL, JMP, JR
- 10. CONTROL UNIT o Program Counter :The program counter stores the program(s) that the processor is running and will run in the future. o Instruction Register :The Instruction Register (IR) stores the current instruction, not the memory location. It’s main purpose is to provide information about the instruction to the Control Unit. o Controller :The controller is the main operator in the design. It sends control signals to both the Data path and Memory units to execute the instruction.
- 11. MEMORY UNIT o 2:1 8-BIT MUX 21 : The main function of the MUX is to select the input address of the Memory submodule with the PC_addr from the PC or D_addr from the Control Unit. The Control Unit selects the output of the MUX with D_addr_sel. o 256x16-BIT MAIN MEMORY : This submodule contains the RISC Processor’s onboard memory. With 256 rows, the 16-bit memory takes in an 8-bit address to select the address space. It receives two control signals, D_rd and D_wr, for reading and writing operations respectively.
- 12. DATA PATH UNIT o 3:1 16-BIT MUX : The MUX controls three different data lines into the Register Bank: the output from the ALU, Memory from the Memory Bank, and the 8-bit immediate from the Control Unit. o 16x16-BIT REGISTER BANK : The Register Bank consists of 16, 16-bit registers for general purpose. Given the RISC processor’s “load-store” approach to memory access, the register bank is extensively used for all instructions. o 16-BIT ALU : The 16-bit ALU is tasked with applying a logical or arithmetic operation on two operands that stem from the Register Bank. o RF_RP_ZERO : The RF_rp_zero submodule serves as combinational circuit to check if the output Rp from the Register Bank is zero.
- 13. 16-BIT RISC PROCESSOR ARCHITECTURE
- 14. CONTROL UNIT ASM CHART
- 15. TOOLS USED • SOFTWARE: CADENCE • LANGUAGE: VERILOG HDL
- 16. Fig: Control signals for ten instructions RESULTS
- 17. Fig: Memory and Data path Simulation
- 18. Fig: Instruction Register Simulation
- 19. ADVANTAGES o Performance is good. o Processor uses several transistors. o Allows the instruction to utilize open space on a microprocessor. o It is very simple as compared with another processor.
- 20. APPLICATIONS o Video & Image Processing o Instrumentation o Super mini and CAD Machines o Telecommunication o Terminals
- 21. CONCLUSION o A 16-bit RISC Processor has been implemented with Harvard architecture and 4-stage pipelining structure in one clock cycle. o This design can be used for portable devices such as Laptops, Mobiles and Tablets etc., The RISC architecture is simulated and synthesized using Cadence RTL Compiler.
- 22. FUTURE SCOPE o In future, this design bits may be increased up to 64-bits. We can compare those RISC structures in various technology libraries like slow, fast and typical includes different technologies so that can improve the area, power and delay of the designs.
- 23. REFERENCES o Rajesh Kumar B and Santha Kumar, "Implementation of a 16-Bit RISC Processor for Convolution Application", Advanced in Electronic and Electric Engineering, vol. 4, pp. 441-446, 2014. o Samiappa Sakthikumaran, S Salivahanan and V S Kanchana Baaskaran, "16-Bit RISC Processor Design for Convolution Applications", IEEE- International Conference on Recent Trends in Information Technology, pp. 394-397, Jun. 2011. o Ramandeep Kaur and Anuj, "8-Bit RISC Processor using Verilog HDL", Anuj et al Int. Journal of Engineering Research and Applications, vol. 4, pp. 417-422, Mar. 2014
- 24. Thank You