Design of Mux and decoder using VHDL
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The document describes a VHDL code for an 8-to-1 multiplexer. The multiplexer has 8 inputs, 3 select lines, and 1 output. The VHDL code uses a case statement to select the appropriate input pin to connect to the output pin based on the value on the select lines.
Design of Mux and decoder using VHDL
- 1. 2:4 Decoder CODE: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX8_1 IS PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC); END MUX8_1; ARCHITECTURE BEH123 OF MUX8_1 IS BEGIN PROCESS(DIN,SEL) BEGIN CASE SEL IS WHEN"000"=>DOUT<=DIN(0); WHEN"001"=>DOUT<=DIN(1); WHEN"010"=>DOUT<=DIN(2); WHEN"011"=>DOUT<=DIN(3); WHEN"100"=>DOUT<=DIN(4); WHEN"101"=>DOUT<=DIN(5); WHEN"110"=>DOUT<=DIN(6); WHEN"111"=>DOUT<=DIN(7); WHEN OTHERS=>DOUT<='Z'; END CASE; END PROCESS; END BEH123;
- 2. OUTPUT:
- 3. 8:1 Multiplexer CODE: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX8_1 IS PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC); END MUX8_1; ARCHITECTURE BEH123 OF MUX8_1 IS BEGIN PROCESS(DIN,SEL) BEGIN CASE SEL IS WHEN"000"=>DOUT<=DIN(0); WHEN"001"=>DOUT<=DIN(1); WHEN"010"=>DOUT<=DIN(2); WHEN"011"=>DOUT<=DIN(3); WHEN"100"=>DOUT<=DIN(4); WHEN"101"=>DOUT<=DIN(5); WHEN"110"=>DOUT<=DIN(6); WHEN"111"=>DOUT<=DIN(7); WHEN OTHERS=>DOUT<='Z'; END CASE; END PROCESS; END BEH123;
- 4. Output: